fujitsu semiconductor controller manual mn705 - 00009 - 3 v0 - e fujitsu semiconductor confidential fr81s 32- bit microcontroller mb91590 series hardware manual following url introduces the information for effective develop ment of fujitsu semiconductor microco ntrollers . helpful information is being released for the customers who are considering, or have adopted our microco ntrollers . http://edevice.fujitsu.com/micom/en - support/ fujitsu semiconductor limited
mb9 1590 series fujitsu semiconductor limited fujitsu semiconductor confidential i preface thank you for your continued use of fujitsu semiconductor products. read this manual and "data sheet" thoroughly before using products in the mb91 590 series. ? purpose of this manual and intended readers this series is fujitsu 32 - bit microcontroller designed for automotive and industrial control. it contains the fr81s cpu that is compatible with the fr family. the fr81s cpu has a high level performance among the fr family by enhancing instruction pipeline and load store processing, and improving internal bus transfer. it is best suited for application control for automotive. this manual expl ains the function, operation, and the usage for the engineer who develops the product by actually using this series. ? trademark fr is an abbreviation for the fujitsu risc controller, which is a product of fujitsu s emiconductor limited. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. ? sample programs and development environment fujitsu semiconductor offers sample programs free of charge for using the peripheral functions of the fr81s family. fujitsu semiconductor also makes available descriptions of the development environment required for the mb9 1590 series. feel free to use them to verify the operational specifications and usage of this fujitsu semiconductor microcontroller. ? microcontroller support information: http://edevice.fujitsu.com/micom/en - support/ * : note that the sample programs are subject to change without notice. since they are offered as a way to demonstrate standard operations and usage, evaluate them sufficiently before running them on your system. fujitsu semiconductor assumes no responsibility for any damage that may occur as a result of using a sample program. mn705-00009-3v0-e ( 3 )
mb9 1590 series ? the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. ? the information, such as descriptions of function and application circuit examples, in this docu ment are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the informati on. ? any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu s emiconductor or any third party or does fujitsu semiconductor warrant non - infringement of any third - party's intellectual property right or other right by using such information. fujitsu semiconductor assumes no liability for any infringement of the intelle ctual property rights or other rights of third parties which would result from the use of information contained herein. ? the products described in this document are designed, developed and manufactured as contemplated for general use, including without limi tation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, ai r traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any third par ty for any claims or damages arising in connection with above - mentioned uses of the products. ? any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? exportation/release of any products described in this document may require necessary procedures in a ccordance with the regulations of the foreign exchange and foreign trade control law of japan and/or us export control laws. ? the company names and brand names herein are the trademarks or registered trademarks of their respective owners. copyright ? 201 1 fujitsu semiconductor limited all rights reserved. fujitsu semiconductor limited mn705-00009-3v0-e ( 4 )
mb9 1590 series fujitsu semiconductor limited fujitsu semiconductor confidential iii how to use this manual ? finding a function the following methods can be used to search for the explanation of a desired function in this manual: ? search from the table of the contents the table of the cont ents lists the manual contents in the order of description. ? search from the register the register list for this device has been described. you can look up the name of a desired register on the list to find the address of its location or the page that explains it. the address where each register is located is not described in the text. to verify the address of a register, see " b. i/o map " of " appendix ". ? search from the index you can look up the keyword such as the name of a peripheral function in the index to find the explanation of the function. ? about the chapters basically, this manual explains 1 peripheral function per chapter. ? terminology this manual uses the following terminology. ter m explanation word indicates access in units of 32 bits. half word indicates access in units of 16 bits. byte indicates access in units of 8 bits. ? how to read this manual ? primary terms the following explains the primary terms used in this series ter m explanation xbs a 32 - bit width, high - sp eed internal bus. the bus master is used for access from the cpu (for instruction fetch), the cpu (for data reading or writing), or the on - chip bus. the bus slave is used to access to the on - chip bus, ram (via the xbs built - in wild register), and flash mem ory. the bus has a crossbar switch configuration, and a circuit from each bus master to each bus slave can operate simultaneously. on - chip bus a 32 - bit width, high - speed internal bus. it has a 2 - layer structure for xbs and dma, and they can operate simult aneously. the bus master of the xbs layer is accessed from the xbs. the bus master of the dma layer is accessed from the dma. the bus slave of both layers has an external bus interface, can, 16/32 - bit peripheral bus bridge and others. the bus slave of only dma layer has an access to the xbs. 32 - bit peripheral a 32 - bit width, low - speed internal bus. mn705-00009-3v0-e ( 5 )
mb9 1590 series ter m explanation bus it connects to various types of peripherals. 16- bit peripheral bus (r - bus) a 16 - bit width, low - speed internal bus. it connects to various types of peripher als. the 32 - bit width access to this bus is divided into 16 bits x 2. external bus (external bus) 8/16 - bit width, low - speed external bus. it connects to memory devices, asic and others. this series is the bus master, and a device connected to the external bus is a bus slave. main clock (mclk) this is the reference clock for lsi operation, and it is supplied from the high - speed system oscillator. it is connected to the timer for main oscillation stabilization wait, the clock generator (pll) and others. su b clock (sbclk) this is the reference clock for lsi operation, and it is supplied from the low - speed system oscillator. it is connected to the timer for sub oscillation stabilization wait and others. it can be used by the dual clock products only. cr osci llation the clock for watchdog timer 1 (hardware watchdog) pll clock (pllclk) the main clock is multiplied by pll. cpu clock (cclk) the clock for peripherals operating under the xbs. on - chip bus clock (hclk) the clock for peripherals operating under th e on - chip bus . peripheral clock (pclk) the clock for peripherals operating under the 32 - bit peripheral bus and 16- bit peripheral bus . external bus clock (tclk) the reference clock for an external bus interface connected to the x - bus and for the external clock output. it is generated from the base clock by the clock generator. main clock mode the operation mode based on the main clock. the main clock mode has the main run , main sleep, main stop, oscillation stabilization wait run , oscillation stabil ization wait reset, and program reset state. main run the main clock mode is selected, and all circuits are operable. oscillation stabilization wait time when the clock is switched from the stop state to the oscillation state, the clock takes the osc illation stabilization time. during the oscillation stabilization wait time, the clock is not supplied. ocd the on - chip debugger for this series ocd u the ocd interface built in this product. ocd tool the ocd tool can be connected to the debug i/f pin of this device. chip reset sequence in the chip reset sequence, the connection of ocd tool is checked. it takes ( 1026 +3) pclk cycles. power shutdown the power supply to the target circuit is stopped, and power consumption is decreased. always power supply on block it is not a target division for the power shutdown. pmu power management unit the power shutdown is controlled. pmu exists in always on block. fujitsu semiconductor limited mn705-00009-3v0-e ( 6 )
mb9 1590 series fujitsu semiconductor limited fujitsu semiconductor confidential v ter m explanation sscg sscg mean "spread spectrum clock generator". when the clock in electronic equipment generates a single frequency, the radiation because of the frequency and the higher harmonics wave grows. it is a technology to suppress the peak of emi to low. sscg is a technology that suppresses the peak of emi to low by the clock frequency change slightly and oscillates it (= frequency modulation). when the clock in electronic equipment generates a single frequency, the radiation because of the frequency and the higher harmonics wave grows. sscg is a technology that does working that suppresses the peak of emi to low especially depending that makes the clock frequency change slightly and oscillates it (= frequency modulation). mn705-00009-3v0-e ( 7 )
mb9 1590 series ? access unit and address position address block +0 +1 +2 +3 000060 h ssr0[r/w] b, h, w 00001000 sidr0[r] b, h, w sodr0[w] b , h, w xxxxxxxx scr0[r/w] b, h, w 00000100 smr0[r/w] b, h, w 00000 -0- uart0 000064 h utim0[r] h (utimr0[w]h) 00000000 00000000 drcl0[w] b xxxxxxx utimc0[r/w] b 0-- 00001 u- timer0 although three types of access (byte, half - word, and word access) are enabled, some registers have access restrictions. for details, see "appendix", or section " 4. detailed register description" of each chapter. b, h, w : byte access, half - word access, and word access are enabled. b : byte access (use the byte access only.) h : half - word access (use the half - word access only.) w : word access (use the word access only.) b, h : byte access and half - word access only (the word access is not allowed.) h, w : half - word access and word access only (the byte access is not allowed.) (reference) the following explains the address position during access. ? during word access, the address is a multiple of 4 (the lowest order 2 bits are forcibly set to "00"). ? during half - word access, the address is a multiple of 2 (th e lowest order 1 bit is forcibly set to "0"). ? during byte access, the address remains unchanged. therefore, if the ssr0 register is set to the half - word access, for example, ssr0 + sidr0 (sodr0) register at address 060 h is accessed. (if the address offsets are +1 and +2 (for example, sidr0+scr0), the half - word access is not allowed.) register name offset read only byte access , half - word access, word access write only initial value readable/writable address offset value/register name fujitsu semiconductor limited mn705-00009-3v0-e ( 8 )
mb9 1590 series fujitsu semiconductor limited fujitsu semiconductor confidential vii ? access unit and bit position 4.3 serial status register the register indicates the uart state. (example) ssr0 (uart0) : address 0060 h (access : byte, half - word, word) bit 7 6 5 4 3 2 1 0 pe ore fre rdrf tdre bds rie tie initial value 0 0 0 0 1 0 0 0 attribute r/w r/wx r/wx r/wx r/wx r/w r/w r/w if the access unit is changed, the bit position changes . if the address offset is +0: (example of ssr0 register) ac cess size address bit position word 060 h +0 h 7 6 5 4 3 2 1 0 half - word 060 h +0 h 15 14 13 12 11 10 9 8 word 060 h +0 h 31 30 29 28 27 26 25 24 b it name pe ore fre rdrf tdre bds rie tie if the address offset is +1: (example of sidr0 register) access size add ress bit position word 060 h +1 h 7 6 5 4 3 2 1 0 half - word 060 h +0 h 7 6 5 4 3 2 1 0 word 060 h +0 h 23 22 21 20 19 18 17 16 b it name d7 d6 d5 d4 d3 d2 d1 d0 if the address offset is +2: (example of scr0 register) access size address bit position word 060 h + 2 h 7 6 5 4 3 2 1 0 half - word 060 h +2 h 15 14 13 12 11 10 9 8 word 060 h +0 h 15 14 13 12 11 10 9 8 b it name pen p sbl c l a/d rec rxe txe if the address offset is +3: (example of smr0 register) access size address bit position word 060 h +3 h 7 6 5 4 3 2 1 0 half - word 060 h +2 h 7 6 5 4 3 2 1 0 word 060 h +0 h 7 6 5 4 3 2 1 0 b it name md1 md0 cs2 cs1 cs0 - scke - register name register abbreviation address target peripheral function bit position access unit mn705-00009-3v0-e ( 9 )
mb9 1590 series ? meaning of bit attribute symbols r : read enabled w : write enabled rm : reading operation during read - modify - write (rmw) operation "/" (slash) r/w : read and write enabled. (the read value is the written value.) "," (comma) r, w : the read and written values differ from each other. (the read value is different from the written value.) r0 : the read value is "0". r1 : the read value is "1" . w0 : this bit must always be written to "0". w1 : this bit must always be written to "1". (rm0) : "0" is read by read - modify - write (rmw) operation. (rm1) : "1" is read by read - modify - write (rmw) operation. rx : the read value is undefined. (a res erved bit or an undefined bit) wx : w riting does not affect on the operation. (undefined bit) ? r/w writing examples ? r/w : read and write enabled (the read value is the written value.) ? r,w : read and write enabled (the read value is differ ent from the written value.) ? r,rm/w : read and write enabled (the read value is different from the written value. the written value is read by read - modify - write (rmw) instruction. ) an example is a port data register. ? r(rm1), w : read and write enabled (the read value is different from the written value. for read - modify - write (rmw) instructions, "1" will be read out. ) an example is an interrupt request flag. ? r,wx : read only (read enabled. writing has no effect on operation. ) ? r1,w : write only (write enabled. the read value is "1".) ? r0,w : write only (write enabled. the read value is "0".) ? rx,w : write only (write enabled. the read value is undefined. ) ? r0,w0 : reserved bit (the written value is "0". the read value is the written value.) ? r0,w0 : reserved bit (the written value is "0". the read value is "0".) ? r1,w0 : reserved bit (the written value is "0". the read value is "1".) ? rx,w0 : reserved bit (the written value i s "0". the read value is undefined. ) ? r / w1 : reserved bit (the written value is "1". the read value is the written value.) ? r1,w1 : reserved bit (the written value is "1". the read value is "1".) ? r0,w1 : reserved bit (the written value is "1". the read value is "0".) ? rx,w1 : reserved bit (the written value is "1". the read value is undefined. ) ? rx,wx : undefined bit (the read value is undefined. writing has no effect on operation. ) ? r0,wx : undefined bit (the read value is "0". writing has no effect on operation. ) fujitsu semiconductor limited mn705-00009-3v0-e ( 10 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 1 ) contents chapter 1 : overview ..................................................................................................... 1 1. overview ................................................................................................................................ 2 2. features ................................................................................................................................ . 3 2.1. fr81s cpu core ................................................................................................................. 4 2.2. peripheral functions ............................................................................................................. 5 3. product line - up ...................................................................................................................... 8 4. function overview ............................................................................................................... 16 5. block diagram ...................................................................................................................... 19 6. cpu ...................................................................................................................................... 20 6.1. general - purpose registers ................................................................................................ 21 6.2. dedicated registers ........................................................................................................... 22 7. pin ass ignment .................................................................................................................... 23 8. package dimensions ........................................................................................................... 25 9. explanation of pin functions ............................................................................................... 27 10. pins of each function ........................................................................................................... 44 10.1. pins of ad converter .......................................................................................................... 45 10.2. pins of can (ch.0 to ch.2) .................................................................................................. 46 10.3. pins of external interrupt input (ch.0 to ch.15) ................................................................... 47 10.4. pins of lin - uart (ch.2 to ch.7) ......................................................................................... 48 10.5. pins of multi - function serial interface (ch.0, ch.1) .............................................................. 49 10.6. pins of ppg (ch.0 to ch.23 ) ................................................................................................ 50 10.7. pin of real time clock ....................................................................................................... 52 10.8. pins of stepping motor controller (ch.0 to ch.5) ................................................................ 53 10.9. pins of output compare (ch.0 to ch.3) ............................................................................... 54 10.10. pins of input capture (ch.0 to ch.5) .................................................................................... 55 10.11. pins of sound generator (ch.0 to ch.4 ) ............................................................................... 56 10.12. pins of free - run timer (ch.0, ch.1) ..................................................................................... 57 10.13. pins of base timer (ch.0, ch.1) ........................................................................................... 58 10.14. pins of reload timer (ch.0 to ch.3) ..................................................................................... 59 10.15. pins of external bus interface (gdc external memory i/f) ................................................ 60 10.16. pins of spi interface (gdc external memory i/f) .............................................................. 61 10.17. pins of port function (general - purpose i/o) ...................................................................... 62 10.18. pins of gdc (capture rgb mode) ..................................................................................... 65 10.19. pins of gdc (capture 656 mode) ....................................................................................... 66 10.20. pins of gdc (capture othe r) .............................................................................................. 67 10.21. pins of gdc (display) ......................................................................................................... 68 10.22. pins of gdc (ntsc) ........................................................................................................... 69 10.23. pin of gdc (other) .............................................................................................................. 70 10.24. pins of other ....................................................................................................................... 71 11. i/o circuit types ................................................................................................................. 72 chapter 2 : handling the device .............................................................................. 77 1. handling precautions ........................................................................................................... 78 2. handling device ................................................................................................................... 82 3. application notes ................................................................................................................. 85 3.1. function switching of a multiplexed port ........................................................................... 86 3.2. low - power consumption mode .......................................................................................... 87 3.3. notes when writing data in a register having the status flag ........................................ 88 mn705-00009-3v0-e ( 11 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 2 ) chapter 3 : cpu ............................................................................................................... 89 1. overview .............................................................................................................................. 90 2. features ............................................................................................................................... 91 3. cpu operating description ................................................................................................ . 93 4. pipeline operation ............................................................................................................... 95 5. floating point operation processing ................................................................................... 96 6. data structure ...................................................................................................................... 97 7. addressing ........................................................................................................................... 98 8. programming model ............................................................................................................. 99 8.1. general - purpose registers, dedicated registers, and floating point registers ............ 100 8.2. system register ............................................................................................................... 101 9. reset and eit processing ................................................................................................ . 102 9.1. reset ................................................................................................................................ 103 9.2. eit processing ................................................................................................................. 104 9.3. vector table ...................................................................................................................... 105 10. memory protection function (mpu) .............................................................................. 107 10.1. overview ........................................................................................................................... 108 10.2. list of registers ................................................................................................................ 109 10.3. description of registers .................................................................................................... 110 10.3.1. mpu control register (mpucr) ............................................................................... 111 10.3.2. instruction access protection v iolation address register (ipvar) ........................... 114 10.3.3. instruction access protection violation status register (ipvsr) .............................. 115 10.3.4. data access protection violation address register (dpvar) ................................... 117 10.3.5. data access protection violation status register (dpvsr) ..................................... 118 10.3.6. data access error address register (dear) ........................................................... 120 10.3.7. data access error status register (desr) .............................................................. 121 10.3.8. protection area base address register 0 to 7 (pabr0 to pabr7) .......................... 123 10.3.9. protection area control register 0 to 7 (pacr0 to pacr7) .................................... 124 10.4. ope rations of memory protection function (mpu) .......................................................... 128 10.4.1. setting up memory protection areas ........................................................................ 129 10.4.2. instruction access protection violation ..................................................................... 130 10.4.3. data access protection violation .............................................................................. 131 10.4.4. data access errors ................................................................................................... 132 10.4.5. memory protection operation by delay slot ............................................................ 133 10.4.6. dear and desr update ......................................................................................... 134 10.4.7. notes ......................................................................................................................... 135 chapter 4 : operation mode .................................................................................... 137 1. overview ............................................................................................................................ 138 2. features ............................................................................................................................. 139 3. configuration ...................................................................................................................... 140 4. register .............................................................................................................................. 141 5. operation ........................................................................................................................... 142 5.1. md0, md1, md2, p127 pins settings .............................................................................. 143 5.2. fetching the operat ion mode ........................................................................................... 144 5.3. explanation of each operation mode ............................................................................... 145 mn705-00009-3v0-e ( 12 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 3 ) chapter 5 : clock ........................................................................................................ 147 1. overview ............................................................................................................................ 148 2. features ............................................................................................................................. 150 3. configuration ...................................................................................................................... 151 4. registers ............................................................................................................................ 156 4.1. division configuration register 0 : divr0 (division clock configuration register 0) ....... 158 4.2. division configuration register 1 : divr1 (division clock configuration register 1) ....... 159 4.3. division configuration register 2 : divr2 (division clock configuration register 2) ....... 160 4.4. clock source selection register : cselr (clock source selection register) ................ 161 4 .5. clock source monitor register : cmonr (clock source monitor register) ................... 164 4.6. main timer control register : mtmcr (main clock timer control register) .................. 166 4.7. sub timer control register : stmcr (sub clock timer control register) ...................... 168 4.8. pll setting r egister : pllcr (pll configuration register) ........................................... 170 4.9. clock stabilization selection re gister : cstbr (clock stabilization selection register) 173 4.10. pll clock oscillation timer control register : ptmcr (pll clock osc timer control register) ....................................................................................................................................... 175 4.11. pl l/sscg clock selection register : ccpsselr (cctl pll/sscg clock selection register) .......................................................................................................................................... 176 4.12. pll/sscg output clock division setting register : ccpsdivr (cctl pll/sscg clock division register) ........................................................................................................................ 177 4.13. pll feedback division setting register : ccpllfbr (cctl pll fb clock division register) .......................................................................................................................................... 179 4.14. sscg feedback division setting register 0 : ccssfbr0 (cctl sscg fb clock division register 0) .................................................................................................................................... 180 4.15. sscg feedback division setting register 1 : ccssfbr1 (cctl sscg fb clock division register 1) .................................................................................................................................... 181 4.16. sscg configuration setting register 0 : ccssccr0 (cctl sscg config. register 0) . 182 4.17. sscg configuration setting register 1 : ccssccr1 (cctl sscg config. register 1) . 184 4.18. clock gear configuration setting register 0 : cccgrcr0 (cctl clock gear conf ig. register 0) .......................................................................................................................................... .......................................................................................................................................... 185 4.19. clock gear configuration setting register 1 : cccgrcr1 (cctl clock gear config. register 1) .................................................................................................................................... 187 4.20. clock gear configuration setting register 2 : cccgrcr2 (cctl clock gear config. register 2) .................................................................................................................................... 188 4.21. rtc/pmu clock selection register : ccrtselr (cctl rtc pmu clock selection register) .......................................................................................................................................... 189 4.22. pmu clock division setting register 0 : ccpmucr0 (cctl pmu clock division register 0) .......................................................................................................................................... 191 4.23. pmu clock division setting register 1 : ccpmucr1 (cctl pmu clock division register 1) .......................................................................................................................................... 192 4.24. sync/async control register : sacr (sync/async control register) ............................. 194 4.25. peripheral interface clock divider : picd (peripheral interface clock divider) ............... 195 4.26. gdc pll control register : gpllcr .............................................................................. 197 4.27. gdc pll timer setting register : ptimc r: .................................................................... 198 4.28. gdc pll external division setting register : pedivcr ................................................ 199 4.29. gdc pll multiplier setting register : pdivcr ............................................................... 201 4.30. gdc pll_sscg multiplier setting register 0 : sdivcr0 .............................................. 202 4.31. gdc pll_sscg multiplier setting register 1 : sdivcr1 .............................................. 203 4.32. gdc pll_sscg spread spectrum setting register 0 : ssscr0 .................................. 204 4.33. gdc pll_sscg spread spectrum setting register 1 : ssscr1 .................................. 206 4.34. gdc pll clock gear setting register 0 : pgrcr0 ....................................................... 207 4.35. gdc pll clock gear setting register 1 : pgrcr1 ....................................................... 209 4.36. gdc pll clock gear setting register 2 : pgrcr2 ........................................................ 211 4.37. gdc pll_sscg clock gear setting register 0 : sgrcr0 ........................................... 212 4.38. gdc pll_sscg clock gear setting register 1: sgrcr1 ............................................ 214 4.39. gdc pll _sscg clock gear setting register 2 : sgrcr2 .......................................... 216 mn705-00009-3v0-e ( 13 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 4 ) 5. operation ........................................................................................................................... 217 5.1. osci llation control ............................................................................................................ 218 5.1.1. main clock (mclk) ................................................................................................... 219 5.1.2. sub clock (sbclk) .................................................................................................. 220 5.1.3. pll/sscg clock (pllssclk) ................................................................................. 221 5.1.4. limitations when pll/sscg clock is used .............................................................. 224 5.2. oscillation stabilization wait ............................................................................................. 226 5.2.1. conditions for generating stabilization wai t time .................................................... 227 5.2.2. selecting stabilization wait time .............................................................................. 228 5.2.3. end of the stabilization wait time ............................................................................ 229 5.3. selecting the source clock (srcclk) ............................................................................ 230 5.3.1. selecting the source clock at the time of initialization ............................................ 231 5.3.2. procedure of switching the source clock .................................................................. 232 5.4. timer ................................................................................................................................ . 237 5.4.1. main clock oscillation stabilization wait timer (main timer) ................................... 238 5.4.2. sub clock oscillation stabilization wait timer (sub timer) ..................................... 239 5.4.3. pll/sscg clock oscillation stabilization wait timer (pll timer) ........................... 240 5.4.4. setting ....................................................................................................................... 241 5.4.5. procedure for setting the timer interrupt ................................................................ . 242 5.4.6. timer operations ...................................................................................................... 243 5.4.7. watch mode and timer interrupt .............................................................................. 244 5.5. notes when clocks conflict .............................................................................................. 245 5.6. the clock gear circuit ..................................................................................................... 246 5.6.1. procedure of gear up ............................................................................................... 247 5.6.2. procedure of gear dow n .......................................................................................... 248 5.7. operations during mdi communications ......................................................................... 249 5.8. about pmu clock (pmuclk) ........................................................................................... 250 chapter 6 : clock reset state transitions ...................................................... 253 1. overview ............................................................................................................................ 254 2. device states and transitions ........................................................................................... 255 2.1. diagram of state transitions ............................................................................................ 256 2.2. explanation of each states .............................................................................................. 2 58 2.3. priority of state transition requests ................................................................................ 260 3. d evice state and regulator mode corresponding to those states ................................... 261 chapter 7 : reset ......................................................................................................... 263 1. overview ............................................................................................................................ 264 2. features ............................................................................................................................. 265 3. configuration ...................................................................................................................... 266 4. registers ............................................................................................................................ 268 4.1. reset source register : rstrr (reset result register) ............................................. 269 4.2. reset control register : rstcr (reset control register) ............................................ 271 4.3. cpu abnormal operation register : cpuar (cpu abnormal operation register) ......... 272 4.4. pmu status register : pmustr (power management unit status register) ................. 274 5. operation description ........................................................................................................ 275 5.1. reset level ....................................................................................................................... 276 5.1.1. initialize reset (init) ................................................................................................ 277 5.1.2. reset (rst) .............................................................................................................. 278 5.2. reset factor ..................................................................................................................... 279 5.2.1. power - on reset ........................................................................................................ 280 mn705-00009-3v0-e ( 14 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 5 ) 5.2.2. rstx pin input ......................................................................................................... 281 5.2.3. watchdog reset 0 .................................................................................................... 282 5.2.4. watchdog reset 1 .................................................................................................... 283 5.2.5. external low - voltage detection reset ..................................................................... 284 5.2.6. illegal standby mode transition detection reset ..................................................... 285 5.2.7. internal low - voltage detection reset ...................................................................... 286 5.2.8. flash security violation reset .................................................................................. 287 5.2.9. software reset (rstcr:srst) ............................................................................... 288 5.2.10. recovery from standby (power interception) ........................................................... 289 5.3. reset acceptance ............................................................................................................ 290 5.3.1. generation of reset request ................................................................................... 291 5.3.2. acceptance of reset request .................................................................................. 292 5.3.3. reset issue delay counter ....................................................................................... 293 5.3.4. irregular reset .......................................................................................................... 294 5.4. reset issue ....................................................................................................................... 295 5.4.1. power - on reset (sinit)............................................................................................ 296 5.4.2. initialize reset (ini t) ................................................................................................ 298 5.4.3. reset (rst) .............................................................................................................. 299 5.5. reset sequence ............................................................................................................... 300 5.5.1. reset cycle ............................................................................................................... 301 5.5.2. reset release .......................................................................................................... 302 5.5.3. operating mode fix .................................................................................................. 303 5.5.4. transition of bus control .......................................................................................... 304 5.5.5. reset vector fetch ................................................................................................... 305 5.5.6. reset and forced break ........................................................................................... 306 5.6. notes ................................................................................................................................ 307 chapter 8 : dma controller (dmac) ..................................................................... 309 1. overview ............................................................................................................................ 310 2. features .............................................................................................................................. 311 3. configuration ...................................................................................................................... 312 4. registers ............................................................................................................................ 313 4.1. dma control register: dmacr (dma control register) ................................................. 316 4.2. dma channel control register 0 to 15: dccr0 to 15 (dma channel control register 0 to 15 ) .......................................................................................................................................... 3 18 4.3. dma channel status register 0 to 15 : dcsr0 to 15 : (dma channel status register 0 to 15 ) .......................................................................................................................................... 324 4.4. dma transfer count register 0 to 15 : dtcr0 to 15 : (dma transfer count register 0 to 15 ) .......................................................................................................................................... 326 4.5. dma transfer source register 0 to 15 : dsar0 to 15 : (dma source address register 0 to 15 ) .......................................................................................................................................... 327 4.6. dma transfer destination register 0 to 15 : ddar0 to 15 (dma destination address register 0 to 15 ) ........................................................................................................................... 329 4.7. dma transfer suppression nmi flag register : dnmir (dma - halt by nmi register) .... 331 4.8. dma transfe r suppression level register : dilvr (dma - halt by interrupt level register) . .......................................................................................................................................... 332 5. operation ........................................................................................................................... 334 5.1. dma operation enable ..................................................................................................... 335 5.2. separate items for each channel .................................................................................... 336 5.3. operations ........................................................................................................................ 340 6. dma usage examples ....................................................................................................... 35 2 mn705-00009-3v0-e ( 15 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 6 ) chapter 9 : generation and clearing of dma transfer requests .......... 355 1. overview ............................................................................................................................ 356 2. features ............................................................................................................................. 357 3. configuration ...................................................................................................................... 358 4. registers ............................................................................................................................ 359 4.1. dma request clear register 0 : icsel0 (interrupt clear select register 0) ................. 361 4.2. dma request clear register 1 : icsel1 (interrupt clear select register 1) ................. 362 4.3. dma request clear register 2 : icsel2 (interrupt clear select register 2) ................. 363 4.4. dma request clear register 3 : icsel3 (interrupt clear select register 3) ................. 364 4.5. dma request clear register 4 : icsel4 (interrupt clear select register 4) ................. 365 4.6. dma request clear register 5 : icsel5 (interrupt clear select register 5) ................. 366 4.7. dma request clear register 6 : icsel6 (interrupt clear select register 6) ................. 367 4.8. dma request clear register 7 : icsel7 (interrupt clear select register 7) ................. 368 4.9. dma request clear register 8 : icsel8 (interrupt clear select register 8) ................. 369 4.10. dma request clear register 9 : icsel9 (interrupt clear select register 9) ................. 370 4.11. dma request clear register 10 : icsel10 (interrupt clear select register 10) ........... 371 4.12. dma r equest clear register 11 : icsel11 (interrupt clear select register 11) ............ 372 4.13. dma request clear register 12 : icsel12 (interrupt clear select register 12) ........... 373 4.14. dma request clear register 13 : icsel13 (interrupt clear select register 13) ........... 374 4.15. dma request clear register 14 : icsel14 (interrupt clear select register 14) ........... 375 4.16. dma request clear register 15 to 18 : icsel15 to 18 (interrupt clear select register 15 to 18) .......................................................................................................................................... 376 4.17. dma request clear register 19 : icsel19 (interrupt clear select register 19) ........... 377 4.18. dma request clear register 20 : icsel20 (interrupt clear select register 20) ........... 378 4.19. dma request clear register 21 : icsel21 (interrupt clear select register 21) ........... 379 4.20. dma request clear register 22 : icsel22 (interrupt clear select register 22) ........... 380 4.21. io transfer request setting register 0 to 15 : iorr0 to 15 (io triggered dma request register for ch. 0 to 15) ................................................................................................................ 381 5. operation ............................................................................................................................ 384 5.1. configuration .................................................................................................................... 385 5.2. notes ................................................................................................................................ 386 chapter: 10 fixedvector function ....................................................................... 387 1. overview ............................................................................................................................ 388 2. o peration explanation ....................................................................................................... 389 chapter: 11 i/o ports .................................................................................................. 391 1. overview ............................................................................................................................ 392 2. f eatures ............................................................................................................................. 393 3. configuration ..................................................................................................................... 394 4. registers ............................................................................................................................ 395 4.1. port data register 00 to 13, a to h : pdr00 to pdr13, pdra to pdrh (port data register 00- 13,a - h) .................................................................................................................................... 398 4.2. data direction register 00 to 13, a to h : ddr00 to ddr13, ddra to ddrh (data direction register 00 - 13,a - h) ...................................................................................................... 400 4.3. port function register 00 to 13, a to h : pfr00 to pfr13, pfra to pfrh (port function register 00 - 13,a - h) ..................................................................................................................... 402 4.4. input data direct register 00 to 13, a to h : p ddr00 to pddr13, pddra to pddrh (port data direct register 00 - 13,a - h) .................................................................................................. 404 4.5. port pull - up/down control register 00 to 13, a to h : ppcr00 to ppcr13, ppcra to ppcrh (port pull - up/down control register 00 - 13,a - h) ............................................................ 406 mn705-00009-3v0-e ( 16 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 7 ) 4.6. port pull - up/down enable register 00 to 13, a to h : pper00 to pper13, ppera to pperh (port pull - up/down enable register 00 - 13,a - h) ............................................................. 408 4.7. port input level selection register 00 to 13, a to h : pilr00 to pilr13, pilra to pilrh (port input level register 00 - 13, a - h) ......................................................................................... 410 4.8. extended port input level selection register 06 to 13 : epilr06 to epilr13 (extended port input level register 06 - 13) .................................................................................................. 412 4.9. port output drive register 06 to 13 : podr06 to podr13 (port output drive register 06- 13) .......................................................................................................................................... 413 4.10. extended port output drive register 06 to 08 : epodr06 to epodr08 (extended port output drive register 06 - 08) ....................................................................................................... 415 4.11. extended port output drive register for graphic digital interface: epodrgd .......... 416 4.12. extended port output drive register for graphic flash interface: epodrgf ........... 417 4.13. extended port function register 00 to 55 : epfr00 to epfr55 (extended port function register 00 - 55) ............................................................................................................................. 419 4.13.1. extended port function register 00, 01 : epfr00, epfr01 (extended port function register 00, 01) ......................................................................................................... 420 4.13.2. extended port function register 02 to 05 : epfr02 to epfr05 (extended port function register 02 - 05) .......................................................................................................... 421 4.13.3. extended port function register 06 to 09, 33, 34 : epfr06 to epfr09, epfr33, epfr34 (extended port function register 06 - 09,33,34) ........................................................ 423 4.13.4. extended port function register 10 to 15, 45, 46 : epfr10 to epfr15, epfr45, epfr46 (extended port function register 10 - 15,45,46) ........................................................ 426 4.13.5. extended port function register 21 to 23 : epfr21 to epfr23 (extended port function register 21 - 23) .......................................................................................................... 429 4.13.6. extended port function register 24 : epfr24 (extended port function register 24) .............................................................................................................................. 430 4.13.7. extended port function register 25 : epfr25 (extended port function register 25) .............................................................................................................................. 431 4.13.8. extended port function register 26 : epfr26 (extended port function register 26) .............................................................................................................................. 432 4.13.9. extended port function register 27, 30 : epfr27, epfr30 (extended port function register 27,30) .......................................................................................................... 433 4.13.10. extended port function register 28 : epfr28 (extended port function register 28) .............................................................................................................................. 434 4.13.11. extended port function register 29 : epfr29 (extended port function register 29) .............................................................................................................................. 435 4.13.12. extended port function register 35, 36 : epfr35, epfr36 (extended port function register 35,36) .......................................................................................................... 436 4.13.13. extended port function register 48 to 50 : epfr48 to epfr50 (extended port function register48 - 50) ........................................................................................................... 438 4.13.14. extended port function register 51, 52 : epfr51, epfr52 (extended port function register 51,52) .......................................................................................................... 440 4.13.15. extended port function register 55 : epfr55 (extended port function register 55) .............................................................................................................................. 441 4.13.16. extended port function register 16 to 20, 31, 32, 37 to 44, 47, 53, 54 : epfr16 to epfr20, epfr31, epfr32, epfr37 to epfr44, epfr 47, epfr53, epfr54(extended port function register 16 - 20, 31, 32, 37 - 44, 47, 53, 54) ................................................................ . 442 4.14. port input enable register : porten(port enable register) ................................... 446 5. operation ........................................................................................................................... 447 5.1. pin i/o assig nment ........................................................................................................... 448 5.1.1. peripheral i/o (bidirectional) pin assignment ........................................................... 449 5.1.2. peripheral input assignment ..................................................................................... 450 5.1.3. peripheral output assignment .................................................................................. 451 5.1.4. external bus assignment .......................................................................................... 452 5.1.5. port function (input) assignment ............................................................................. 453 5.1.6. port function (output) a ssignment .......................................................................... 454 5.1.7. ad converter input assignment ............................................................................... 455 5.2. epfr setting priority ........................................................................................................ 456 mn705-00009-3v0-e ( 17 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 8 ) 5.3. notes on input i/o relocation setting .............................................................................. 457 5.4. input interception by gporten ...................................................................................... 458 5.5. notes on pins with the ad converter function ................................................................ 459 5.6. setting when using the base timer tioa1 pin ............................................................... 460 5.7. operation at wake up from power shutdown ................................................................ . 461 5.8. notes on switching the port function ................................................................................ 462 chapter 12 : interrupt control (interrupt controller) ........................... 463 1. overview ............................................................................................................................ 464 2. features ............................................................................................................................. 465 3. configuration ...................................................................................................................... 466 4. registers ............................................................................................................................ 467 4.1. inte rrupt control registers 00 to 47 : icr00 to icr47 (interrupt control register 00 to 47): .......................................................................................................................................... 468 5. operation ........................................................................................................................... 469 chapter 13 : external interrupt input ............................................................... 471 1. overview ............................................................................................................................ 472 2. features ............................................................................................................................. 473 3. configuration ...................................................................................................................... 474 4. registers ............................................................................................................................ 475 4.1. external interrupt factor register 0/1 : eirr0/eirr1 (external interrupt request register 0/1) .......................................................................................................................................... 476 4.2. external interrupt enable register 0/1 : enir0/enir1 (enable interrupt request register 0/1) .......................................................................................................................................... 477 4.3. external interrupt request level register 0/1 : elvr0/elvr1 (external interrupt level register 0/1) ................................................................................................................................ . 478 5. operation ........................................................................................................................... 479 6. setting ................................................................................................................................ 481 7. q&a .................................................................................................................................... 482 8. notes .................................................................................................................................. 483 chapter 14 : nmi input ................................................................................................ . 485 1. overview ............................................................................................................................ 486 2. features ............................................................................................................................. 487 3. configuration ...................................................................................................................... 488 4. register .............................................................................................................................. 489 5. o peration ........................................................................................................................... 490 6. usage example .................................................................................................................. 491 chapter 15 : delay interrupt .................................................................................. 493 1. o verview ............................................................................................................................ 494 mn705-00009-3v0-e ( 18 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 9 ) 2. features ............................................................................................................................. 495 3. configuration ...................................................................................................................... 496 4. registers ............................................................................................................................ 497 5. operation ........................................................................................................................... 498 6. restrictions ........................................................................................................................ 499 chapter 16 : interrupt request batch read .................................................... 501 1. overview ............................................................................................................................ 502 2. features ............................................................................................................................. 503 3. configuration ...................................................................................................................... 504 4. registers ............................................................................................................................ 505 4.1. interrupt request batch read register 0 upper - order : irpr0h (interrupt request peripheral read register 0h) ....................................................................................................... 507 4.2. interrupt request batch read register 0 lower - order : irpr0l (interrupt request peripheral read register 0l) ........................................................................................................ 508 4.3. interrupt request batch read register 1 upper - order : irpr1h (interrupt request peripheral read register 1h) ....................................................................................................... 509 4.4. interrupt request batch read register 1 lower - order : irpr1l (interrupt request peripheral read register 1l) ........................................................................................................ 510 4.5. interrupt request batch read register 2 upper - order : irpr2h (interrupt request peripheral read register 2h) ........................................................................................................ 511 4.6. interrupt request batch read register 2 lower - order : irpr2l (interrupt request peripheral read register 2l) ........................................................................................................ 512 4.7. interrupt request batch read register 3 upper - order : irpr3h (interrupt request peripheral read register 3h) ....................................................................................................... 513 4.8. interrupt request batch read register 3 lower - order : irpr3l (interrupt request peripheral read register 3l) ........................................................................................................ 514 4.9. interrupt request batch read register 4 upper - order : irpr4h (interrupt request peripheral read register 4h) ....................................................................................................... 51 5 4.10. interrupt request batch read register 4 lower - order : irpr4l (interrupt request peripheral read register 4l) ........................................................................................................ 516 4.11. interrupt request batch read register 5 upper - order : irpr5h (interrupt request peripheral read register 5h) ....................................................................................................... 517 4.12. interrupt request batch read register 5 lower - order : irpr5l (interrupt request peripheral read register 5l) ........................................................................................................ 518 4.13. interrupt request batch read register 6 upper - order : irpr6h (interrupt request peripheral read register 6h) ....................................................................................................... 519 4.14. interrupt request batch read register 6 lower - order : irpr6l (interrupt request peripheral read register 6l) ........................................................................................................ 520 4.15. interrupt request batch read register 7 upper - order : irpr7h (interrupt request peripheral read register 7h) ....................................................................................................... 521 4.16. interrupt request batch read register 7 lower - order : irpr7l (interrupt request peripheral read register 7l) ........................................................................................................ 522 4.17. interrupt request batch read register 8 upper - order irpr8h (interrupt request peripheral read register 8h) ....................................................................................................... 523 4.18. i nterrupt request batch read register 8 lower - order : irpr8l (interrupt request peripheral read register 8l) ........................................................................................................ 524 4.19. interrupt request batch read register 9 upper - order : irpr9h (interrupt request peripheral read register 9h) ....................................................................................................... 525 4.20. interrupt request batch read register 9 lower - order : irpr9l (interrupt request peri pheral read register 9l) ........................................................................................................ 526 4.21. interrupt request batch read register 12 upper - order : irpr12h (interrupt request peripheral read register 12h) ..................................................................................................... 527 mn705-00009-3v0-e ( 19 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 10 ) 4.22. interrupt request batch read register 12 lower - order : irpr12l (interrupt request peripheral read register 12l) ...................................................................................................... 528 4.23. interrupt request batch read register 13 upper - order : irpr13h (interrupt request peripheral read register 13h) ..................................................................................................... 529 4.24. interrupt request batch read register 13 lower - order : irpr13l (interrupt request peripheral read register 13l) ...................................................................................................... 530 4.25. interrupt request batch read register 14 upper - order : irpr14h (interrupt request peripheral read register 14h) ..................................................................................................... 531 4.26. interrupt request batch read register 14 lower - order : irpr14l (interrupt request peripheral read register 14l) ...................................................................................................... 532 4.27. interrupt request batch read register 15 upper - order : irpr15h (interrupt request peripheral read register 15h) ..................................................................................................... 533 5. operation ........................................................................................................................... 534 chapter 17 : ppg ........................................................................................................... 535 1. overview ............................................................................................................................ 536 2. features ............................................................................................................................. 537 3. configuration ...................................................................................................................... 538 4. registers ............................................................................................................................ 539 4.1. ppg cycle setting register : pcsr ................................................................................ 543 4.2. ppg duty setting register : pdut .................................................................................. 544 4.3. ppg control status register : pcn ................................................................................. 545 4.4. general control register 10 - 13 : gcn10 to gcn13 ....................................................... 548 4.5. general control register 14, 15 : gcn14, gcn15 ......................................................... 550 4.6. general control register 20 - 25 : gcn20 to gcn25 ....................................................... 551 4.7. ppg timer register : ptmr ............................................................................................ 552 4.8. ppg0 output division setting register : ppgdiv ........................................................... 553 5. operation ........................................................................................................................... 554 5.1. pwm operation ................................................................................................................ 555 5.2. one - shot operation .......................................................................................................... 557 5.3. restart operation ............................................................................................................. 559 6. setting ................................................................................................................................ 560 7. q&a .................................................................................................................................... 562 7.1. how to set (rewrite) cycle an d duty values ................................................................... 563 7.2. how to enable/stop ppg operation? .............................................................................. 564 7.3. how to set ppg operation mode (pwm/one - shot) ........................................................ 565 7.4. h ow to restart .................................................................................................................. 566 7.5. type and selection of count clock .................................................................................. 567 7.6. how to fix the ppg pin output level .............................................................................. 568 7.7. type and selection of ac tivation trigger .......................................................................... 569 7.8. how to reverse the output polarity ................................................................................. 571 7.9. how to change a pin to a ppg output pin ...................................................................... 572 7.10. how to generate activation trigger .................................................................................. 573 7.11. how to stop ppg operation ............................................................................................. 574 7.12. interrupt - related registers ................................................................................................ 575 7.13. type and selection of interrupts ....................................................................................... 576 7.14. how to enable/disable/clear interrupt ............................................................................. 577 8. sample programs .............................................................................................................. 578 9. notes .................................................................................................................................. 582 mn705-00009-3v0-e ( 20 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 11 ) chapter 18 : watchdog timer .................................................................................. 58 3 1. overview ............................................................................................................................ 58 4 2. features ............................................................................................................................. 58 5 3. configuration ...................................................................................................................... 58 6 4. registers ............................................................................................................................ 58 7 4.1. watchdog control register 0 : wdtcr0 (watchdog timer configuration register 0) ... 58 8 4.2. watchdog timer 0 clear register : wdtcpr0 (watchdog timer clear pattern register 0) .......................................................................................................................................... 59 0 4.3. watchdog timer 1 cycle information register : wdtcr1 (watchdog timer cycle information register 1) ................................................................................................................. 59 1 4.4. watch dog timer 1 clear register : wdtcpr1 (watchdog timer clear pattern register 1) .......................................................................................................................................... 59 2 5. operation ........................................................................................................................... 59 3 6. usage example .................................................................................................................. 59 5 chapter 19 : base timer ............................................................................................. 597 1. overview ............................................................................................................................ 598 2. features ............................................................................................................................. 599 2.1. 16/32 - bit reload timer ..................................................................................................... 600 2.2. 16- bit pwm timer ............................................................................................................. 601 2.3. 16/32 - bit pwc timer ........................................................................................................ 602 2.4. 16- bit ppg timer .............................................................................................................. 603 3. configuration ...................................................................................................................... 604 4. registers ............................................................................................................................ 605 4.1. common registers ........................................................................................................... 607 4.1.1. timer registers 0, 1 : btxtmr (base timer 0/1 timer register) ............................ 608 4.1.2. timer control registers 0, 1 : btxtmcr (base timer 0/1 timer control reg ister) 609 4.1.3. i/o selection register : btsel01 (base timer select register ch.0 and ch.1) ....... 614 4.1.4. simultaneous software activation register : btsssr (base timer software synchronous start register) ..................................................................................................... 615 4.2. registers for 16/32 - bit reload timer ................................................................................ 616 4 .2.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) ............... 617 4.2.2. cycle setting registers 0, 1 : btxpcsr (base timer 0/1 pulse counter start register) .................................................................................................................................. 618 4.3. registers for 16 - bit pwm timer ....................................................................................... 619 4.3.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) ............... 620 4.3.2. c ycle setting registers 0, 1 : btxpcsr (base timer 0/1 pulse counter start register) .................................................................................................................................. 622 4.3.3. duty setting registers 0, 1 : btxpdut (base timer 0/1 pulse duty register) ....... 623 4.4. registers for 16 - bit ppg timer ........................................................................................ 624 4.4.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) ............... 625 4.4.2. l width setting registers 0, 1 : btxprll (base timer 0/1 pulse length of "l" register) .................................................................................................................................. 626 4.4.3. h width setting registers 0, 1 : btxprlh (base timer 0/1 pulse length of "h" register) .................................................................................................................................. 627 4.5. 16/32 - bit pwc timer register .......................................................................................... 628 4.5.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) ............... 629 4.5.2. data buffer registers 0, 1 : btxdtbf (base timer 0/1 data buffer register) ....... 631 5. operation ........................................................................................................................... 63 2 5.1. selection of timer function .............................................................................................. 633 5.2. i/o allocation .................................................................................................................... 634 5.3. 32- bit mode operation ...................................................................................................... 637 mn705-00009-3v0-e ( 21 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 12 ) 5.3.1. 32- bit mode function ................................................................................................ 638 5.3.2. 32- bit mode setting ................................................................................................... 639 5.3.3. 32- bit mode operation .............................................................................................. 640 5.4. 16/32 - bit reload timer operation .................................................................................... 641 5.4.1. overview ................................................................................................................... 643 5.4. 2. operation in reload mode ........................................................................................ 644 5.4.3. operation in one - shot mode .................................................................................... 647 5.4.4. 32- bit timer mode operation .................................................................................... 649 5.4.5. interrupts ................................................................................................................... 651 5.4.6. precautions for using this device ............................................................................. 652 5.5. 16- bit pwm timer operation ............................................................................................ 653 5.5.1. overview ................................................................................................................... 654 5.5.2. operation in relo ad mode ........................................................................................ 655 5.5.3. operation in one - shot mode .................................................................................... 659 5.5.4. interrupt ..................................................................................................................... 661 5.5.5. precautions for using this device ............................................................................. 662 5.6. 16- bit ppg timer operation ............................................................................................. 663 5.6.1. overview ................................................................................................................... 664 5.6.2. pulse width calculation method ............................................................................... 665 5.6.3. operation in reload mode ........................................................................................ 666 5.6.4. operation in one - shot mode .................................................................................... 670 5.6.5. interrupts ................................................................................................................... 673 5.6.6. application notes ...................................................................................................... 674 5.7. 16/32 - bit pwc timer operation ....................................................................................... 675 5.7.1. overview ................................................................................................................... 677 5.7.2. operation during pwc measurement ....................................................................... 681 5.7.3. 32- bit timer mode operation .................................................................................... 684 5.7.4. interrupt ..................................................................................................................... 686 5.7.5. app lication notes ...................................................................................................... 687 chapter 20 : reload timer ........................................................................................ 689 1. overview ............................................................................................................................ 690 2. features ............................................................................................................................. 691 3. configuration ...................................................................................................................... 692 4. registers ............................................................................................................................ 693 4.1. control status register : tmcsr (timer control and status register) ........................... 694 4.2. 16- bit timer register : tmr (16bit timer register) .......................................................... 698 4.3. 16- bit timer reload register a, 16 - bit timer reload register b : tmrlra, tmrlrb(16bit timer reload register a/b) ........................................................................................................ 699 5. operation ........................................................................................................................... 701 5.1. setting ............................................................................................................................... 702 5.1.1. count source ............................................................................................................ 703 5.1.2. timer underflow period ............................................................................................. 704 5.1.3. trigger ....................................................................................................................... 705 5.1.4. gate .......................................................................................................................... 706 5.1.5. counter operation selection .................................................................................... 707 5.1.6. tout pin level setting ............................................................................................ 708 5.2. operation procedure ........................................................................................................ 710 5.2.1. activation ................................................................................................................... 711 5.2.2. retrigger ................................................................................................................... 713 5.2.3. underflow/reload ..................................................................................................... 715 5.2.4. generation of interrupt requests ............................................................................. 716 5.2.5. concurrent operation of register write and a timer activation .............................. 717 5.3. operations of each counter ............................................................................................. 718 5.3.1. single one - shot operation ....................................................................................... 719 mn705-00009-3v0-e ( 22 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 13 ) 5.3.2. single reload operation ........................................................................................... 721 5.3.3. dual one - shot operation .......................................................................................... 723 5.3.4. dual reload operation ............................................................................................. 725 5.3.5. compare one - shot operation .................................................................................. 727 5.3.6. compare reload operation ...................................................................................... 730 5.3.7. capture mode ........................................................................................................... 733 5.4. cascade input .................................................................................................................. 736 5.5. priority of concurrent operations ..................................................................................... 737 6. application note ................................................................................................................. 738 6.1. single one - shot timer ...................................................................................................... 740 6.2. reload timer .................................................................................................................... 743 6.3. ppg .................................................................................................................................. 746 6.4. pwm ................................................................................................................................ . 750 6.5. pwc ................................................................................................................................ . 753 chapter 21 : free - run timer ..................................................................................... 7 55 1. overview ............................................................................................................................ 756 2. features ............................................................................................................................. 757 3. configuration ...................................................................................................................... 758 4. registers ............................................................................................................................ 759 4.1. timer control register (upper bit) : tccsh ................................................................... 760 4.2. timer control register (lower bit) : tccsl .................................................................... 762 4.3. compare clear register : cpclr ................................................................................... 764 4.4. timer data register : tcdt ............................................................................................. 765 5. operation ........................................................................................................................... 766 5.1. count operation of the free - run timer ............................................................................ 767 5.2. counting up ...................................................................................................................... 768 5.3. timer clear ....................................................................................................................... 769 5.4. each clear operations of the free - run timer .................................................................. 770 5.5. timer interrupt .................................................................................................................. 771 6. setting ................................................................................................................................ 772 7. q&a .................................................................................................................................... 773 7.1. how to select internal clock dividers .............................................................................. 774 7.2. how to select the external clock ..................................................................................... 775 7.3. how to enable/disable the count operation of the free - run timer ................................ 776 7.4. how to clear the free - run timer ...................................................................................... 777 7.5. about interrupt related registers .................................................................................... 778 7.6. how to enable compare clear interrupt .......................................................................... 779 7.7. how to stop the free - run timer operation ...................................................................... 780 8. sample program ................................................................................................................ 781 9. notes .................................................................................................................................. 782 chapter 22 : output compare ................................................................................. 783 1. overview ............................................................................................................................ 784 2. features ............................................................................................................................. 785 3. configuration diagram ....................................................................................................... 786 4. registers ............................................................................................................................ 787 4.1. free - run timer selection register : ocfs ....................................................................... 788 4.2. output control register (upper bit) : ocsh ..................................................................... 789 mn705-00009-3v0-e ( 23 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 14 ) 4.3. output control register (lower bit) : ocsl ..................................................................... 791 4.4. compare register : occp ................................................................................................ 793 5. operation ........................................................................................................................... 794 5.1. output compare output (independent invert) cmod = "0" .............................................. 795 5.2. output compare output (coordinated invert) cmod = "1" .............................................. 796 5.3. output compare operation timing ................................................................................... 797 5.3.1. compare register write ............................................................................................. 798 5.3.2. compare match, interrupt .......................................................................................... 799 5.3.3. pin output .................................................................................................................. 800 6. setting ................................................................................................................................ 801 7. q&a .................................................................................................................................... 802 7.1. how can i set the compare value? ................................................................................. 803 7.2. how can i set the compare mode? (example with ocu 1) ............................................. 804 7.3. how can i enable/disable the compare operation? (example with ocu0, ocu1) ....... 805 7.4. how can i set the compare pin output initial level? (example with ocu0, ocu1) ...... 806 7.5. how can i set the compare pin ocu0, ocu1 for output? ............................................. 807 7.6. how can i cl ear the free - run timer? ............................................................................... 808 7.7. how can i enable the compare operation? ..................................................................... 809 7.8. interrupt related register? ............................................................................................... 810 7.9. interrupt type? ................................................................................................................... 811 7.10. how can i enable the interrupt? ................................................................................... 812 7.11. calculation method for the compare value? ................................................................ . 813 7.11.1. toggle output p ulse ................................................................................................... 814 7.11.2. pwm output ............................................................................................................... 815 8. sample program ................................................................................................................ 816 9. notes .................................................................................................................................. 818 chapter 23 : input capture ...................................................................................... 819 1. overview ............................................................................................................................ 820 2. features ............................................................................................................................. 821 3. configuration ...................................................................................................................... 822 4. registers ............................................................................................................................ 823 4.1. input capture data register : ipcp .................................................................................. 825 4.2. free - run timer selection register : icf s ......................................................................... 826 4.3. input capture control register : ics ................................................................................. 828 4.4. lin synch field switching register : lsyns .............................................................. 830 5. operation ........................................................................................................................... 832 5.1. capture and interrupt timings ........................................................................................... 833 5.2. edge detection specifications for input capture and their operations ........................... 834 6. setting ................................................................................................................................ 836 7. q&a .................................................................................................................................... 837 7.1. effective edge polarity of external input: types and how to select ................................ . 838 7.2. how to enable external input pins (icu0, icu1, icu2, icu3, icu4, icu5) ..................... 839 7.3. about interrupt related registers ..................................................................................... 840 7.4. about interrupt types ........................................................................................................ 841 7.5. how to enable interrupt ..................................................................................................... 842 7.6. how to measure the pulse width of the input signal ........................................................ 843 8. sample program ................................................................................................................ 844 9. notes .................................................................................................................................. 845 mn705-00009-3v0-e ( 24 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 15 ) chapter 24 : real - time clock(rtc) ........................................................................ 847 1. overview ............................................................................................................................ 848 2. features ............................................................................................................................. 849 3. configuration ...................................................................................................................... 850 4. registers ............................................................................................................................ 851 4.1. rtc control register : wtcr .......................................................................................... 852 4 .2. sub - second register : wtbr ........................................................................................... 857 4.3. day/hour/minute/second register : wtdr/ wthr/wtmr/ wtsr ................................ 858 5. operation ........................................................................................................................... 860 6. setting ................................................................................................................................ 862 7. q&a .................................................................................................................................... 863 7.1. how to set the 0.5 second count interval? ...................................................................... 864 7.2. how to initialize the real - time clock? ............................................................................... 865 7.3. how to se t/update number of days (day) and time (hour/minute/second)? ................. 866 7.4. how to start/stop the count of the real - time clock? ....................................................... 867 7.5. how to confirm that the real - time clock is running? ..................................................... 868 7.6. how to know the number of days and time? .................................................................. 869 7.7. how to stop the real - time clock? .................................................................................... 870 7.8. how to calibrate the real - time clock? ............................................................................. 871 7.9. what are interrupt related registers? ............................................................................. 872 7.10. what are the interrupt types and how to select them? ................................................. 873 7.11. how to enable interrupts? ................................................................................................ 874 8. sample program ................................................................................................................ 875 9. notes .................................................................................................................................. 876 ch apter 25 : rtc/wdt1 calibration ....................................................................... 877 1. overview ............................................................................................................................ 878 2. features ............................................................................................................................. 879 3. configuration ...................................................................................................................... 880 4. registers ............................................................................................................................ 881 4.1. calibration unit control register 0 : cucr0 (calibration unit control register 0) .......... 882 4.2. sub clock timer data register : cutd0 (calibration unit timer data register 0) ........... 883 4.3. main oscillation timer result register 0 : cutr0 (calibration unit timer result register 0) ........................................................................................................................................... 884 4.4. calibration unit control register 1 : cucr1 (calibration unit control register 1) .......... 885 4.5. cr clock timer data register : cutd1 (calibration unit timer data register 1) ............ 886 4.6. main oscillation timer result register 1 : cutr1 (calibration unit timer result register 1) ........................................................................................................................................... 887 4.7. cr oscillation trimming setting register : crtr (cr oscillator calibration trimming register ) ....................................................................................................................................... 888 5. operation ........................................................................................................................... 889 5.1. real - time clock (rtc) calibration ................................................................................... 890 5.2. wdt1 calibration (cr clock calibration) ......................................................................... 891 5.3. notes ................................................................................................................................ . 892 chapter 26 : power consumption control ........................................................ 893 mn705-00009-3v0-e ( 25 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 16 ) 1. overview ............................................................................................................................ 894 2. features ............................................................................................................................. 895 3. configuration ...................................................................................................................... 896 4. registers ............................................................................................................................ 898 4.1. standby control register : stbcr (standby mode control register) ............................ 899 4.2. pmu control register : pmuctlr (power management unit control register) ............ 901 4.3. power on timing control register : pwrtmctl (power on timing control register) 902 4.4. pmu interrupt flag register 0 : pmuintf0 (power management unit interrupt flag0 register) ........................................................................................................................................ 903 4.5. pmu interrupt flag register 1 : pmuintf1 (power management unit interrupt flag1 register) ........................................................................................................................................ 904 4.6. pmu interrupt flag register 2 : pmuintf2 (power management unit interrupt flag2 register) ........................................................................................................................................ 905 4.7. gdc status register : gstr (gdc status register) ........................................................ 907 4.8. gdc control register : gctlr (gdc control register) ................................................. 908 5. operation ........................................................................................................................... 909 5.1. clock control ..................................................................................................................... 910 5.2. list of clock supply in low - power consumption mode ..................................................... 911 5.3. sleep mode ....................................................................................................................... 912 5.4. standby mode : watch mode ............................................................................................ 914 5.5. standby mode : watch mode with power - shutdown ......................................................... 916 5.6. standby mode : stop mode ............................................................................................... 919 5.7. standby mode : stop mode with power - shutdown ............................................................ 921 5.8. stop state of microcontroller ............................................................................................. 925 5.9. power - shutdown gdc unit ............................................................................................... 926 5.10. t ransition to illegal standby mode ................................................................................... 928 5.11. gdc regulator ................................................................................................................. 929 5.12. restrictions on power shutdown and normal standby control ....................................... 930 6. example of use .................................................................................................................. 933 chapter 27: low voltage detection (internal low - voltage detection) .................................................................................................................. 935 1. overview ............................................................................................................................ 936 2. features ............................................................................................................................. 93 7 3. configuration ...................................................................................................................... 938 4. registers ............................................................................................................................ 939 4.1. microcontroller unit internal low voltage detection register : lvd (low voltage detect internal power fall register) ........................................................................................................... 940 4.2. gdc unit internal low voltage detection register : glvd (gdc low voltage detect inter nal power fall register) ........................................................................................................................ 942 5. operation ........................................................................................................................... 944 5.1. internal low - voltage detection in microcontroller unit ...................................................... 945 5.2. internal low - voltage detection in gdc unit ...................................................................... 946 6. notes .................................................................................................................................. 947 chapter 28 : low voltage detection (external low - voltage detection) .................................................................................................................. 949 1. overvi ew ............................................................................................................................ 950 2. features ............................................................................................................................. 951 mn705-00009-3v0-e ( 26 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 17 ) 3. configuration ...................................................................................................................... 952 4. registers ............................................................................................................................ 953 4.1. microcontroller unit external low voltage detection rise detection register : lvd5r (low voltage detect external 5v rise register) ..................................................................................... 954 4.2. microcontroller unit external low voltage detection fall detection register : lvd5f (low voltage detect external 5v fall register) ...................................................................................... 955 4.3. gdc unit external low voltage detection rise detection register : glvd5r (gdc low voltage detect external 5v rise register) ................................................................................... 957 4.4. gdc unit external low voltage detection fall detection register : glvd5f (gdc low voltage detect external 5v fall register) ..................................................................................... 959 5. operation ........................................................................................................................... 961 5.1. microcontroller unit external low voltage detection ........................................................ 962 5.2. gdc unit external low voltage detection ........................................................................ 963 6. notes .................................................................................................................................. 964 chapter 29 : wild reg ister ....................................................................................... 965 1. overview ............................................................................................................................ 966 2. features ............................................................................................................................. 967 3. configuration ...................................................................................................................... 968 4. registers ............................................................................................................................ 969 4.1. wild register data enable register : wren (wild register data enable register) 971 4.2. wild register address register 00 to 15 : wrar00 to 15 (wild register address register 00 to 15) ....................................................................................................................................... 972 4.3. wild register data register 00 to 15 : wrdr00 to 15 (wild register data register 00 to 15) ........................................................................................................................................... 973 5. operation ........................................................................................................................... 974 6. usage example .................................................................................................................. 975 chapter 30: clock supervisor .............................................................................. 977 1. overview ............................................................................................................................ 978 2. configuration ...................................................................................................................... 979 3. register .............................................................................................................................. 980 4. oper ation ........................................................................................................................... 983 4.1. initial state ......................................................................................................................... 984 4.2. stopping cr oscillator and the clock supervisor function .............................................. 985 4.3. re - enabling the clock supervisor ..................................................................................... 986 4.4. sub clock mode ................................................................................................................ 987 4.5. stop mode ......................................................................................................................... 988 4.6. watch mode ...................................................................................................................... 989 4.7. checking the reset factor using the clock super visor ................................................... 990 4.8. return from cr clock ....................................................................................................... 991 chapter 31 : sound generator ............................................................................... 993 1. overview ............................................................................................................................ 994 2. features ............................................................................................................................. 995 3. configuration ...................................................................................................................... 996 mn705-00009-3v0-e ( 27 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 18 ) 4. registers ............................................................................................................................ 997 4.1. dma transfer update enable register : sgder (sg dma enable register) .............. 999 4.2. sound control register : sgcr (sg control register) .................................................. 1001 4.3. amplitude data register : sgar (sg amplitude register) ............................................ 1004 4.4. frequency data register : sgfr (sg frequency register) .......................................... 1005 4.5. tone outputs number register : sgnr (sg tone number register) ............................ 1006 4.6. cycle register : sgtc r (sg tone cycle register) ....................................................... 1007 4.7. increment decrement data register : sgidr (sg increment decrement register) ..... 1008 4.8. pwm cycles number data register : sgpcr (sg pwm cycle register) .................... 1009 4.9. dma transfer indirect register : sgdmar (sg dma register) .................................... 1 010 5. operation .......................................................................................................................... 1011 5.1. relation of amplitude data register (sgar) and pwm pulse ....................................... 1012 5.2. relation of frequency data register (sgfr) and tone pulse signals .......................... 1013 5.3. relation of pwm cycles number data register (sgpcr) and pwm cycle .................. 1014 5.4. relation o f dma transfer update enable register (sgder) and dma transfers count/dma transfer size/transfer byte location ..................................................................... 1015 5.4.1. dma transfers count ............................................................................................... 1016 5.4.2. dma transfer size ................................................................................................... 1017 5.4.3. transfer byte location for dma transfer indirect register ..................................... 1018 5.4.4. d ma transfer image ................................................................................................ 1021 5.5. operation of sound generator ........................................................................................ 1022 5.6. sound generator continuous operation by cpu ........................................................... 1024 5.7. sound generator operation coordinated with dma ....................................................... 1026 5.8. when dma transfer of 4 bytes 2 is performed n times ............................................. 1027 5.8.1. when dma tra nsfer of 2 bytes 2 is performed n times ...................................... 1030 5.8.2. when dma transfer of 1 byte 1 is performed n times ....................................... 1033 5.8.3. for dma transfer of 4 bytes 2 n times and dma transfer of 2 bytes 1 m times (transfer bytes number change during sound output) ....................................................... 1036 5 .8.4. for dma transfer of 4 bytes 2 n times and dma transfer of 4 bytes 2 m times (transfer bytes number and increment decrement setting change during sound output) 1039 chapter 32 : stepping motor controller ....................................................... 1043 1. overview .......................................................................................................................... 1044 2. features ........................................................................................................................... 1045 3. c onfiguration .................................................................................................................... 1046 4. registers .......................................................................................................................... 1047 4.1. pwm control register : pwc ......................................................................................... 1049 4.2. pwm1&2 compare register : pwc1/pwc2 .................................................................. 1051 4.3. pwm1 selection register : pws1 .................................................................................. 1052 4.4. pwm2 selection register : pws2 .................................................................................. 1053 5. operation ......................................................................................................................... 1055 5.1. pwm operation ............................................................................................................... 1056 5.2. pwm comp are register loading with the bs bit .......................................................... 1057 5.3. selection of motor drive signals ..................................................................................... 1059 6. setting .............................................................................................................................. 1060 7. q&a .................................................................................................................................. 1061 7.1. how to set cycle and duty ............................................................................................. 1062 7.2. how to enable/stop pwm operation .............................................................................. 1063 7.3. how to reflect the duty change ..................................................................................... 1064 7.4. type and selection of operating clock ........................................................................... 1065 7.5. how to change the motor drive signals ......................................................................... 1066 7.6. how to assign a pin as a pwm output pin ..................................................................... 1067 7.7. how to assign a pin as an a/d converter analog input pin ........................................... 1068 mn705-00009-3v0-e ( 28 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 19 ) 8. sample programs ............................................................................................................ 1069 9. notes ................................................................................................................................ 1070 chapter 33 : regulator control ........................................................................ 1071 1. overview .......................................................................................................................... 1072 2. features ........................................................................................................................... 1073 3. configuration .................................................................................................................... 1074 4. register ............................................................................................................................ 1075 4.1. regulator output voltage select register : regsel (regulator output voltage select register) ...................................................................................................................................... 1076 5. operation ......................................................................................................................... 1078 chapter 34 : bus performance counters ........................................................ 1079 1. overview .......................................................................................................................... 1080 2. features ........................................................................................................................... 1081 3. configuration .................................................................................................................... 1082 4. registers .......................................................................................................................... 1083 4.1. bpc - a control register : bpccra (bus performance counter control register a) ..... 1084 4.2. bpc - b control register : bpccrb (bus performance counter control register b) .... 1086 4.3. bpc - c control register : bpccrc (bus performance counter control register c) .... 1087 4.4. bpc - a count register : bpctra (bus performance counter register a) ................... 1088 4.5. bpc - b count register : bpctrb (bus performance counter register b) ................... 1089 4.6. bpc - c count register : bpctrc (bus performance counter register c) .................. 1090 5. operations ........................................................................................................................ 1091 5.1. setting ............................................................................................................................. 1092 5.2. starting and stopping ...................................................................................................... 1094 5.3. operation ......................................................................................................................... 1095 5.4. measurement and result processing ............................................................................. 1096 chapter 35 : crc ......................................................................................................... 1099 1. overview ........................................................................................................................... 1100 2. features ............................................................................................................................ 1101 3. configuration ..................................................................................................................... 1102 4. registers ........................................................................................................................... 1103 4.1. crc control register : crccr ....................................................................................... 1104 4.2. crc initial value register : crcinit .............................................................................. 1105 4.3. crc input data register : crcin ................................................................................... 1106 4.4. crc register : crcr ...................................................................................................... 1107 5. operation .......................................................................................................................... 1108 5.1. crc definition .................................................................................................................. 1109 5.2. reset operation ............................................................................................................... 1110 5.3. initiali zation ....................................................................................................................... 1111 5.4. byte and bit orders .......................................................................................................... 1112 5.5. crc calculation sequence .............................................................................................. 1113 5.6. examples .......................................................................................................................... 1114 mn705-00009-3v0-e ( 29 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 20 ) 5.6.1. example 1 crc16, fixed byte input ........................................................................ 1115 5.6.2. example 2 crc16, mixture of different input bit widths .......................................... 1117 5.6.3. example 3 crc32, byte order, big - endian .............................................................. 1118 5.6.4. example 4 crc32, byte order, little - endian ........................................................... 1119 chapter 36 : ramecc ................................................................................................ . 1121 1. overview ........................................................................................................................... 1122 2. features ............................................................................................................................ 1123 3. configuration ..................................................................................................................... 1124 4. registers ........................................................................................................................... 1126 4.1. ecc error control register xbs ram : eecsrx (ecc error control and status register xbs ram) ...................................................................................................................................... 1127 4.2. single - bit ecc error address register xbs ram : seearx (single bit ecc error address register xbs ram) ....................................................................................................................... 1128 4.3. double - bit ecc error address register xbs ram : deearx (double bit ecc error address register xbs ram) ....................................................................................................................... 1129 4.4. ecc false error generation address register xbs ram : efearx (ecc false error address register xbs ram) ......................................................................................................... 1130 4.5. ecc false error generation control register xbs ram : efecrx ( ecc false error control register xbs ram) ........................................................................................................... 1131 4.6. ecc error control register backup - ram : eecsra (ecc error control and status register backup - ram) ................................................................................................................. 1133 4.7. single - bit ecc error address register backup - ram : seeara (single bit ecc error address register backup - ram) ................................................................................................... 1134 4.8. double - bit ecc error address register backup - ram : deeara (double bit ecc er ror address register backup - ram) ................................................................................................... 1135 4.9. ecc false error generation address register backup - ram : efeara (ecc false error address register backup - ram) ................................................................................................ . 1136 4.10. ecc false error generation control register backup - ram : efecra (ecc false error control reg ister backup - ram) ................................................................................................... 1137 5. operation .......................................................................................................................... 1139 5.1. ecc generation ............................................................................................................... 1140 5.2. ecc inspection ................................................................................................................. 1141 5.3. interrupt by error detection .............................................................................................. 1142 5.4. test function .................................................................................................................... 1143 chapter 37 : multi function serial interface ................................................ 1145 1. overview ..................................................................................................................... 1146 2. features..................................................................................................................... . 1147 2.1. uart ................................................................................................................................ 1148 2.2. csio ................................................................................................................................ . 1149 2.3. lin - ua rt ......................................................................................................................... 1150 2.4. i 2 c ..................................................................................................................................... 1151 2.5. note .................................................................................................................................. 1152 3. configuration ............................................................................................................. 1153 4. registe rs..................................................................................................................... 1157 4.1. common registers ........................................................................................................... 1159 4.1.1. serial mode register : smr ...................................................................................... 1160 4.1.2. fifo control register 1 : fcr1 ................................................................................ 1163 4.1.3. fifo control register 0 : fcr0 ................................................................................ 1165 4.1.4. fifo byte register : fbyte ................................................................................... 1168 4.2. registers for u art .......................................................................................................... 1170 mn705-00009-3v0-e ( 30 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 21 ) 4.2.1. serial control register : scr ................................................................................... 1171 4.2.2. serial status register : ssr ..................................................................................... 1173 4.2.3. extended serial control register : escr ................................................................ . 1176 4.2.4. receive data register/transmit data register : rdr/tdr ..................................... 1178 4.2.5. baud rate generator register : bgr ........................................................................ 118 0 4.3. registers for csio ........................................................................................................... 1181 4.3.1. serial control register : scr ................................................................................... 1182 4.3.2. serial status register : ssr ..................................................................................... 1184 4.3.3. extended serial control register : escr ................................................................ . 1186 4.3.4. receive data register/transmit data register : rdr/tdr ..................................... 1187 4.3.5. baud rate generator register : bgr ........................................................................ 1189 4.4. registers for lin - uart .................................................................................................... 1190 4.4.1. serial control register : scr ................................................................................... 1191 4.4.2. serial status register : ssr ..................................................................................... 1193 4.4.3. extended serial control register : escr ................................................................ . 1196 4.4.4. receive data register/transmit data register : rdr/tdr ..................................... 11 98 4.4.5. baud rate generator register : bgr ....................................................................... 1200 4.5. registers for i 2 c .............................................................................................................. 1201 4.5.1. i 2 c bus control register : ibcr .............................................................................. 1202 4.5.2. serial status register : ssr .................................................................................... 1207 4.5.3. i 2 c bus status register : ibsr ................................................................................ 1210 4.5.4. receive data register/transmit data registe r : rdr/tdr .................................... 1214 4.5.5. baud rate generator register : bgr ....................................................................... 1216 4.5.6. i 2 c 7 - bit slave address mask register : ismk ........................................................ 1217 4.5.7. i 2 c 7 - bit slave bus address register : isba ........................................................... 1218 5. operation of uart........................................................... ......................................... 1219 5.1. interrupt of uart ............................................................................................................ 1220 5.1.1. list of interrupt of uart .......................................................................................... 1221 5.1.2. reception interrupts and flag setting timing .......................................................... 1222 5.1.3. interrupts when using reception fifo and flag setting timing ............................. 1224 5.1.4. transmi ssion interrupts and flag setting timing ..................................................... 1226 5.1.5. interrupts when using transmission fifo and flag setting timing ....................... 1227 5.2. operation of uart .......................................................................................................... 1228 5.2.1. transmission/reception data format ...................................................................... 1229 5.2.2. transmission operation ........................................................................................... 1231 5.2.3. reception operati on ................................................................................................ 1232 5.2.4. clock selection ......................................................................................................... 1233 5.2.5. start bit detection ..................................................................................................... 1234 5.2.6. stop bit ..................................................................................................................... 1235 5.2.7. error detection ......................................................................................................... 1236 5.2.8. parity bit ................................................................................................................... 1237 5.2.9. data signaling method ............................................................................................. 1238 5.2.10. data transfer method .............................................................................................. 1239 5.2.11. uart baud rate selection/setting ......................................................................... 1240 5.3. setup procedure and program flow ............................................................................... 1245 5.3.1. operation mode 0 (one - to - one connection) ........................................................... 1246 5.3.2. operation mode 1 (one - to - n connection) ............................................................... 1248 6. operation of csio........................................................................................... ........... 1251 6.1. interrupts of csio ............................................................................................................ 1252 6.1.1. list of interrupts of csio .......................................................................................... 1253 6.1.2. reception interrupts and flag setting timing .......................................................... 1254 6.1.3. interrupts when using reception fifo and flag setting timing ............................. 1255 6.1.4. transmission interrupts and flag se tting timing ..................................................... 1257 6.1.5. interrupts when using transmission fifo and flag setting timing ....................... 1258 6.2. operation of csio ........................................................................................................... 1259 6.2.1. normal transfer (i) ................................................................................................... 1260 6.2.2. normal transfer (ii) .................................................................................................. 1264 6.2.3. spi transfer (i) ......................................................................................................... 1268 mn705-00009-3v0-e ( 31 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 22 ) 6.2.4. spi transfer (ii) ........................................................................................................ 1272 6.2.5. bau d rate generation ............................................................................................. 1276 6.3. setup procedure and program flow ............................................................................... 1278 6.3.1. connections between chips .................................................................................... 1279 6.3.2. flowchart .................................................................................................................. 1280 7. operation of lin - uart............................................................................................... 1281 7.1. i nterrupts of lin - uart .................................................................................................... 1282 7.1.1. list of interrupts of lin - uart interface ................................................................... 1283 7.1.2. reception interrupts and flag setting timing .......................................................... 1285 7.1.3. interrupts when using reception fifo and flag setting timing ............................. 1288 7.1.4. transmission interrupts and flag settin g timing ..................................................... 1290 7.1.5. interrupts when using transmission fifo and flag setting timing ....................... 1291 7.2. operation of lin - uart ................................................................................................... 1292 7.2.1. master device operation ......................................................................................... 1293 7.2.2. slave device operation ........................................................................................... 1298 7.2.3. lin - uart baud rate selection/setting ................................................................... 1302 7.3. setup pro cedure and program flow ............................................................................... 1303 7.3.1. inter - cpu connection .............................................................................................. 1304 7.3.2. flowchart example ................................................................................................... 1305 8. operation of i 2 c.................................................................................................... . ..... 1309 8.1. interrupts of i 2 c ............................................................................................................... 1310 8.2. o peration for i 2 c interface communication .................................................................... 1312 8.2.1. i 2 c bus start condition ............................................................................................. 1313 8.2.2. i 2 c bus stop condition ............................................................................................. 1314 8.2.3. i 2 c bus repeated start condition ............................................................................ 1315 8.2.4. i 2 c bus error ............................................................................................................ 1316 8.2.5. baud rate generation ............................................................................................. 1317 8.3. i 2 c master mode .............................................................................................................. 1319 8.3.1. st art condition generation ....................................................................................... 1320 8.3.2. slave address output .............................................................................................. 1321 8.3.3. acknowledge reception by transmitting first byte ................................................. 1323 8.3.4. data transmission by master ................................................................................... 1329 8.3.5. data reception by master system ........................................................................... 1345 8.3.6. arbitration lost ......................................................................................................... 1352 8.3.7. wait of the master mode .......................................................................................... 1353 8.3.8. repetition start condition issue when dma mode enabled (ssr:dma=1) ............ 1354 8.4. i 2 c slave mode ................................................................................................................ 1355 8.4.1. detection of slave address matching ...................................................................... 1356 8.4.2. data direction bit ..................................................................................................... 1358 8.4.3. reception by slave device ...................................................................................... 1359 8.4.4. transmissio n by slave device ................................................................................. 1365 8.5. bus error ......................................................................................................................... 1366 8.5.1. bus error generation condition ............................................................................... 1367 8.5.2. bus error operation ................................................................................................ . 1368 8.6. example of i 2 c flowchart ................................................................................................ 1369 8.6.1. example of i 2 c flowchart (fifo memory not used) (when dma mode is disable (ssr: dma=0)) ................................................................................................................................ . 1369 8.6 .2. example of i 2 c flowchart (fifo memory not used) (when dma mode is enable (ssr: dma=1)) ................................................................................................................................ . 1372 chapter 38 : lin - uart ................................................................................................ 1377 1. overview..................................................................................................................... 1378 2. features..................................................................................................................... 1379 2.1. functions ......................................................................................................................... 1380 2.2. operation mode ............................................................................................................... 1381 mn705-00009-3v0-e ( 32 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 23 ) 3. configuration .............................................................................................................. 1382 3.1. block diagram of the lin - uart ..................................................................................... 1383 3.2. explanation of each block ............................................................................................... 1385 3.2.1. reload counter ........................................................................................................ 1386 3.2.2. reception control circuit ......................................................................................... 1387 3.2.3. reception shift register .......................................................................................... 1388 3.2.4. reception data reg ister (rdr) ............................................................................... 1389 3.2.5. transmission control circuit .................................................................................... 1390 3.2.6. transmission shift register ..................................................................................... 1391 3.2.7. transmission data register (tdr) .......................................................................... 1392 3.2.8. error detection circuit .............................................................................................. 1393 3.2.9. over - sampling circuit ............................................................................................... 1394 3.2.10. interrupt generation circuit ...................................................................................... 1395 3 .2.11. lin synch break/lin synch field detection circuit ................................................ 1396 3.2.12. lin synch break generation circuit ........................................................................ 1397 3.2.13. bus idle detection circuit ......................................................................................... 1398 3.2.14. serial mode register (smr) .................................................................................... 1399 3.2.15. serial control register (scr) .................................................................................. 1400 3.2.16. serial status register (ssr) .................................................................................... 1401 3.2.17. extended status control register (escr) .............................................................. 1402 3.2.18. extended communication control register (eccr) ............................................... 1403 4. registers..................................................................................................................... 1404 4.1. serial control register : scr .......................................................................................... 1407 4.2. serial mode register : smr ............................................................................................ 1410 4.3. serial status register :ssr ............................................................................................ 1413 4.4. reception data register / transmission data register : rdr / tdr ............................. 1416 4.4.1. reception data register : rdr ............................................................................... 1417 4.4.2. transmi ssion data register : tdr ........................................................................... 1418 4.5. extended status control register : escr ...................................................................... 1419 4.6. extended communication control register : eccr ....................................................... 1422 4.7. baud rate generator register : bgr ............................................................................. 1424 5. interrupts.............................................................................................................. . ..... 1425 5.1. overview .......................................................................................................................... 1426 5.1.1. interrupts of lin - uart ............................................................................................. 1427 5.1.2. reception interrupt ................................................................................................... 1428 5.1.3. transmission interrupt .............................................................................................. 1429 5.1.4. lin synch break interrupt ........................................................................................ 1430 5.1.5. lin synch field edge detection interrupt ................................................................ 1431 5.2. generation of reception interrupt and flag setting timing ............................................ 1432 5.2.1. generation of reception interrupt and flag setting timing ..................................... 1433 5.3. occurrence of transmission interrupt and flag timing .................................................. 1435 5.3.1. occurrence of transmission interrupt and flag timing ........................................... 1436 5.3.2. transmission interrupt request generation timing ................................................ 1437 6. baud rates................................................................................................................. 1438 6.1. selection of baud rates .................................................................................................. 1439 6.1 .1. baud rate obtained when a dedicated baud rate generator (reload counter) divides the frequency of the internal clock ........................................................................................ 1440 6.1.2. baud rate obtained when a dedicated baud rate generator (reload counter) divides the frequency of the external clock ...................................................................................... 1441 6 .1.3. baud rate due from external clock (one - to - one mode) ....................................... 1442 6.2. baud rate setting ........................................................................................................... 1443 6.2.1. baud rate calculations ............................................................................................ 1444 6.2.2. baud rate setting example for each clock frequency .......................................... 1445 6.2.3. use of the external clock ......................................................................................... 1447 6.2.4. reload counter operati on ....................................................................................... 1448 6.3. reload counter ............................................................................................................... 1449 6.3.1. reload counter functions ....................................................................................... 1450 mn705-00009-3v0-e ( 33 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 24 ) 6.3.2. count start ............................................................................................................... 1451 6.3.3. restart ...................................................................................................................... 1452 6.3.4. counter clear ........................................................................................................... 1453 6.3.5. simple timer use ..................................................................................................... 1454 7. operation.................................................................................................................... 1455 7.1. overview .......................................................................................................................... 1456 7.1.1. operation mode ....................................................................................................... 1457 7.1.2. connection method between cpus ......................................................................... 1458 7.1.3. synchronization system ........................................................................................... 1459 7.1.4. signaling system ..................................................................................................... 1460 7.1.5. transmission/reception start .................................................................................. 1461 7.1.6. stopping of transmission/reception ........................................................................ 1462 7.1.7. stopping of transmission/reception in progress .................................................... 1463 7.2. asynchronous mode (operation modes 0 and 1) ........................................................... 1464 7.2.1. transmission/reception data format ...................................................................... 1465 7.2.2. transmission operation ........................................................................................... 1466 7.2.3. reception operation ................................................................................................ 1467 7.2.4. clock usage ............................................................................................................. 1468 7.2.5. stop bit ..................................................................................................................... 1469 7.2.6. error detection ......................................................................................................... 1470 7.2.7. parity ........................................................................................................................ 1471 7.2.8. data signaling method ............................................................................................. 1472 7.2.9. data transfer method .............................................................................................. 1473 7.3. synchronous mode (operation mode 2) ......................................................................... 1474 7.3.1. transmission/reception data format ...................................................................... 1475 7.3.2. master/slave setting ................................................................................................ 1476 7.3.3. sampling edge selection ......................................................................................... 1477 7.3.4. clock supply ............................................................................................................ 1478 7.3.5. clock usage ............................................................................................................. 1479 7.3.6. delayed serial clock ................................................................................................ 1480 7.3.7. sequential serial clock ............................................................................................ 1481 7.3.8. parity ........................................................................................................................ 1482 7.3.9. data signaling method ............................................................................................. 1483 7.3.10. stop bit ..................................................................................................................... 1 484 7.3.11. error detection ......................................................................................................... 1485 7.3.12. communication start ................................................................................................ 1486 7.3.13. communication end ................................................................................................ . 1487 7.3.14. data transfer method .............................................................................................. 1488 7.4. lin mode (operation mode 3) ......................................................................................... 1489 7.4.1. transmission/reception data format ...................................................................... 1490 7.4.2. lin master operation ............................................................................................... 1491 7.4.3. lin slave operation ................................................................................................ . 1492 7.4.4. lin bus timing ......................................................................................................... 1493 7.4.5. baud rate calculation ............................................................................................. 1494 7.4.6. clock usage ............................................................................................................. 1495 7.4.7. data signaling method ............................................................................................. 1496 7.4.8. stop bit ..................................................................................................................... 1497 7.4.9. error detection ......................................................................................................... 1498 7.5. direct access to the serial pin ........................................................................................ 1499 7.6. bidirectional co mmunication function (normal mode) ................................................... 1500 7.6.1. connection between cpus ...................................................................................... 1501 7.6.2. communication procedure ....................................................................................... 1502 7.7. master/ slave mode communication function (multi - processor mode) ......................... 1503 7.7.1. connection between cpus ...................................................................................... 1504 7.7.2. function selection .................................................................................................... 1505 7.7.3. communication procedure ....................................................................................... 1506 7.8. lin communication function .......................................................................................... 1508 7.8.1. lin master/slave communication function ............................................................. 1509 mn705-00009-3v0-e ( 34 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 25 ) 7.8.2. lin device connection ............................................................................................ 1510 7.9. lin - uart sample flowchart in lin communication mode (operation mode 3) ............ 1511 7.9.1. lin - uart as a master device ................................................................................. 1512 7.9.2. lin - uart as a slave device ................................................................................... 1513 8. notes on usage........................................................................................................... 1514 8.1. operation enable ............................................................................................................ 1515 8.2. communication mode setting ......................................................................................... 1516 8.3. timing of enabling transmission interrupt ...................................................................... 1517 8.4. operation setting change ............................................................................................... 1518 8.5. detection of a lin synch break ...................................................................................... 1519 8.6. lin slave setting ............................................................................................................. 1520 8.7. program compatibility ..................................................................................................... 1521 8.8. address/data format selection bit (scr:ad) ................................................................ 1522 8.9. lin - uart sof tware reset .............................................................................................. 1523 8.10. detection of lin synch field in input capture ............................................................ 1524 9. notes on dmac linkage operation.............................................................. ............. 1525 9.1. transmission operation .................................................................................................. 1526 9.2. reception operation ....................................................................................................... 1527 chap ter 39 : can ......................................................................................................... 1529 1. overview ..................................................................................................................... 1530 2. features ..................................................................................................................... 1531 3. configuration ................................................................................................... . .......... 1532 4. registers..................................................................................................................... 1533 4.1. overview .......................................................................................................................... 1534 4.2. overall control registers ................................................................................................ 1541 4.2.1. can control register (ctrlr) ............................................................................... 1542 4.2.2. can status register (statr) .................................................................................. 1545 4.2.3. can error counter (errcnt) ................................................................................ 1548 4.2.4. can bit timing register (btr) ................................................................................ 1549 4.2 .5. can interrupt register (intr) ................................................................................. 1550 4.2.6. can test register (testr) .................................................................................... 1552 4.2.7. can prescaler extension register (brper) .......................................................... 1554 4.3. message interface register ............................................................................................ 1555 4.3.1. ifx command request register (ifxcreq) ........................................................... 1556 4.3.2. ifx command mask register (ifxc msk) ................................................................ 1559 4.3.3. ifx mask registers 1, 2 (ifxmsk1, ifxmsk2) ........................................................ 1563 4.3.4. ifx arbitration registers 1, 2 (ifxarb1, ifxarb2) ................................................. 1564 4.3.5. ifx message control register (ifxmctr) ............................................................... 1565 4.3.6. ifx data registers a1, a2, b1, b2 (ifxdta1, ifxdta2, ifxdtb1, ifxdtb2) ......... 1566 4.4. message object ............................................................................................................... 1567 4.4.1. configuration of message object ............................................................................. 1568 4.4.2. functions of message object ................................................................................... 1569 4.5. message handler registers ............................................................................................ 1574 4.5.1. can transmission request registers (treqr1, treqr2) .................................. 1575 4.5.2. can data update registers (newdt1, newdt2) ................................................ 1577 4.5.3. can interrupt pending registers (intpnd1, intpnd2) ........................................ 1579 4.5.4. can message valid registers (msgval1, msgval2) .......................................... 1581 4.6. can prescaler register (canpre) ................................................................................ 1583 5. operation.................................................................................................................... 1585 5.1. message object ............................................................................................................... 1586 5.1.1. message object ....................................................................................................... 1587 5.1.2. data transmission/reception with message ram .................................................. 1588 5.2. message transmission operation ................................................................................... 1589 mn705-00009-3v0-e ( 35 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 26 ) 5.2.1. message transmission ............................................................................................ 1590 5.2.2. transmission priority ................................................................................................ 1591 5.2.3. transmission message object setting ..................................................................... 1592 5.2.4. update of transmission message object ................................................................ 1593 5.3. message reception operation ........................................................................................ 1594 5.3.1. reception message acceptance filter ..................................................................... 1595 5.3.2. reception priority ..................................................................................................... 1596 5.3.3. data frame receptio n ............................................................................................. 1597 5.3.4. remote frame ......................................................................................................... 1598 5.3.5. reception message object setting .......................................................................... 1599 5.3.6. reception message processing ............................................................................... 1600 5.4. fifo buffer function ....................................................................................................... 1601 5.4.1. configuration of fifo buffer .................................................................................... 1602 5.4.2. message reception by fifo buffer ......................................................................... 1603 5.4.3. reading from fifo buffer ........................................................................................ 1604 5.5. interrupt function ............................................................................................................ 1606 5.6. bit timing and can system clock (fsys) generation ..................................................... 1607 5.7. test mode ........................................................................................................................ 1610 5.7.1. test mode setting ..................................................................................................... 1611 5.7.2. silent mode .............................................................................................................. 1612 5.7.3. loopback mode ........................................................................................................ 1613 5.7.4. combination of silent and loopback modes ........................................................... 1614 5.7.5. basic mode ............................................................................................................... 1615 5.7.6. software control of the can_tx pin ....................................................................... 1616 5.8. software initialization ....................................................................................................... 1617 chapter 40 : ad converter ..................................................................................... 1619 1. overview..................................................................................................................... 1620 2. features..................................................................................................................... . 1621 3. configuration....................................................................................................... . ...... 1622 4. registers.................................................................................................................... . 1623 4.1. analog input enable register : ader ............................................................................ 1624 4.2. a/d control status register (upper) : adcs1 ............................................................... 1625 4.3. a/d control status register (lower) : adcs0 ............................................................... 1628 4.4. data register : adcr0, adcr1 .................................................................................... 1631 4.5. c onversion time setting register : adct ..................................................................... 1632 4.6. a/d start/completion channel setting register : adsch, adech ............................... 1634 5. operation.................................................................................................................... 1637 5.1. single conversion operation ......................................................................................... 1638 5.2. scan conversion operation ........................................................................................... 1639 5.3. conversion mode ........................................................................................................... 1640 6. setting........................................................................................................................ 1642 7. q&a............................................................................................................................ 1644 7.1. conversion mode type and setting method? ................................................................ 1645 7.2. how can i specify the bit length? ................................................................................. 1646 7.3. how can i select channels? ......................................................................................... 1647 7.4. how can i set the conversion time? ............................................................................ 1650 7.5. how can i enable the analog pin input? ....................................................................... 1651 7.6. how can i select the a/d converter activation method? .............................................. 1653 7.7. how can i a ctivate the a/d converter? ......................................................................... 1654 7.8. how can i check the conversion completion? ............................................................. 1655 7.9. how can i read the conversion value? ........................................................................ 1656 7.10. how can i stop the a/d conversion operation forcibly? .............................................. 1657 7.11. interrupt - related register? ............................................................................................ 1658 mn705-00009-3v0-e ( 36 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 27 ) 7.12. interrupt t ype? ................................................................................................................ 1659 7.13. how can i enable/disable/clear the interrupt? ............................................................. 1660 8. sample program ........................................................................................................ 1661 9. notes........................................................................................................................... 1664 10. term definition for a/d converter ........................................................................... 1665 chapter 41 : flash memory .................................................................................... 1669 1. overview ..................................................................................................................... 1670 2. features ..................................................................................................................... 1671 3. configuration............................................................................................................. 1672 3.1. block diagram ................................................................................................................ 1673 3.2. sector configuration diagram ........................................................................................ 1674 3.3. sector number and flash macro number correspondence chart ................................ 1676 4. registers ..................................................................................................................... 1678 4.1. flash control register : fctlr (flash control register) ........................................... 1679 4.2. flash status register : fstr (flash status register) .................................................. 1681 4.3. flash interface control register : flifctlr(flash i/f control register) ..................... 1683 4.4. flash i/f feature extension register 1: fliffer1 ....................................................... 1684 4.5. flash i/f feature extension register 2: fliffer2 ....................................................... 1685 5. operation.................................................................................................................... 1686 5.1. access mode setting ...................................................................................................... 1687 5.1.1. configuring cpu - rom mode ................................................................................. 1688 5.1.2. configuring cpu programming mode .................................................................... 1689 5.2. programming flash memory by cpu ............................................................................. 1690 5.3. automatic algorithm ........................................................................................................ 1691 5.3.1 . command sequence .............................................................................................. 1692 5.3.2. automatic algorithm execution state ...................................................................... 1696 5.4. reset command ............................................................................................................. 1700 5.5. write command .............................................................................................................. 1701 5.6. chip erase command .................................................................................................... 1704 5.7. sector erase command ................................................................................................ . 1705 5.8. sector erase suspend command .................................................................................. 1708 5.9. security function ............................................................................................................ 1709 5.9.1. fl ash security on/off determination when reset released ................................ . 1710 5.9.2. flash security setting method ................................................................................. 1711 5.9.3. unlocking flash security ........................................................................................ 1712 5.9.4. f lash access restrictions when security is on .................................................... 1713 5.10. notes on using flash memory ................................................................................... 1714 chapter 42 : workflas h memory ......................................................................... 1715 1. overview..................................................................................................................... 1716 2. features..................................................................................................................... 1717 3. configuration....................................................................................................... . ...... 1718 3.1. block diagram ................................................................................................................ 1719 3.2. sector configuration diagram ........................................................................................ 1720 4. registers..................................................................................................................... 1721 4.1. workflash control register : dfctlr (workflash control register) ........................ 1722 4.2. workflash status register : dfstr (workflash status register) ............................... 1723 4.3. flash interface control register : flifctlr (flash i/f control register) .................... 1725 mn705-00009-3v0-e ( 37 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 28 ) 5. operation.................................................................................................................... 1726 5.1. access mode setting ...................................................................................................... 1727 5.1.1. configuring cpu - rom mode below ....................................................................... 1728 5.1.2. configuring cpu programming mode .................................................................... 1729 5.2. writing flash memory by cpu ....................................................................................... 1730 5.3. automatic algorithm ........................................................................................................ 1731 5.3.1. command sequence .............................................................................................. 1732 5.3.2. automatic algorithm execution state ...................................................................... 1735 5.4. reset command ............................................................................................................. 1739 5.5. write command .............................................................................................................. 174 0 5.6. chip erase command .................................................................................................... 1743 5.7. sector erase command ................................................................................................ . 1744 5.8. sector erase suspend command .................................................................................. 1747 5.9. security function ............................................................................................................ 1748 5.9.1. flash security on/off determination when reset released ................................ . 1749 5.9.2. flash security setting method ................................................................................ 1750 5.9.3. unlocking flash security ........................................................................................ 1751 5.9.4. flash access restrictions when security is on .................................................... 1752 5.10. notes on using flash memory ................................................................................... 1753 chapter 43 : on chip debugger (ocd) .................................................................. 1755 1. overview..................................................................................................................... 1756 2. features..................................................................................................................... . 1757 3. configuration........................................................................................................... . ..1758 3.1. debug i/f clock ............................................................................................................ 1760 3.1.1. debug i/f main clock (m_mclk) ......................................................................... 1761 3.1.2. debug i/f pll clock (m_pclk) ........................................................................... 1762 4. registers..................................................................................................................... 1763 4.1. dbg register ................................................................................................................. 1764 4.2. user io register ............................................................................................................. 1765 5. operation.................................................................................................................... 1766 5.1. ocdu operating mode .................................................................................................. 1767 5.1.1. opera ting mode ...................................................................................................... 1768 5.1.2. operating mode status transition .......................................................................... 1769 5.2. overview of debug i/f .................................................................................................. 1770 5.2.1. c hip reset sequence ............................................................................................. 1771 5.2.2. security function .................................................................................................... 1773 5.3. specification restrictions at connection to ocd tool of this series ............................ 1774 5.3.1. clock setting ........................................................................................................... 177 5 5.3.2. standby mode ......................................................................................................... 1776 5.3.3. can prescaler register .......................................................................................... 1777 5.3.4. clock reset state transitions ................................................................................. 1778 5.3.5. summary of specification restrictions ................................................................... 1780 5.4. ocd - dsu id code and mount type information on this series .................................. 1784 chapter: 44 gdc external control ................................................................... 1 785 1. overview..................................................................................................................... 1786 2. features ............................................................................................................... . ...... 1787 3. configuration ............................................................................................................... 1788 4. registers ..................................................................................................................... 1789 mn705-00009-3v0-e ( 38 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 29 ) 4.1. gdc control register : gdccr .................................................................................... 1790 4.2. gdc trigger register : gdctrgr ................................................................................ 1792 4.3. gdc swap setting register : gdcswpr ..................................................................... 1793 5. note............................................................................................................................. 1795 appendix........................................................................................................................ 1797 a. memory map............................................................................. ................................. 1798 b. i/o map ..................................................................................................................... 1805 c. list of interrupt vector.......................................................... ....................................... 1841 d. pin status in cpu status ......................................................................................... 1844 mn705-00009-3v0-e ( 39 )
mb91590 series fujitsu semiconductor limited fujit su semiconductor confidential ( 30 ) mn705-00009-3v0-e ( 40 )
chapter 1: overview 1 . overview fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 1 c hapter : overview this chapter explains the overview. 1. overview 2. features 3. product line - up 4. function overview 5. block diagram 6. cpu 7. pin assignment 8. package dimensions 9. explanation of pin functions 10. pins of each function 11. i/o circuit types code : 0 1 _mb91590_hm_e_ overview _009 _201111 28 mb91590 series mn705-00009-3v0-e 1
chapter 1: overview 1 . overview fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 2 1. overview this section explains feat ures of mb91590 series and b asic specification . m b91590 series is fujitsu 32 -b it microcontroller for application control for automotives. the fr81s cpu that is compatible with the fr family is used. mb91590 series mn705-00009-3v0-e 2
chapter 1: overview 2 . fea tures fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 3 2. fe a tures this section explains fe a tures of mb91590 series . 2.1 . fr81s cpu core 2.2 . peripheral f unctions mb91590 series mn705-00009-3v0-e 3
chapter 1: overview 2 . features fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 4 2.1. fr81s cpu core this section explains fr81s cpu c ore . ? 32- bit risc, load/store architecture, 5 - stage pipeline ? maximum operating frequency: 128 mhz (source oscillation = 4.0 mhz and 32 multiplied ( pll clock multiplication system )) ? general - purpose register : 32 bi ts, 16 sets ? 16- bit fixed length instructions ( basic instruction ), 1 instruction per cycle ? instructions appropriate to embedded applications ? memo ry - to - memory transfer instruction ? bit processing instruction ? barrel shift instruction etc. ? high - level languag e support instructions ? function entry/exit instructions ? register content multi - load and store instructions ? bit search instructions ? logical 1 detection, 0 detection, and change - point detection ? branch instructions with delay slot ? reduced overhead during b r an ch proces s ? register interlock function ? easy assembler writing ? built - in multiplier / instruction level support ? si gned 32 - bit multiplication : 5 cycles ? si gned 16 - bit multiplication : 3 cycles ? interrupt ( pc/ps saving ) ? 6 cycles ( 16 priority levels ) ? the h arvard architecture allows simultaneous execution of program and data access. ? instru ction compatibility with the fr fa mily ? bu ilt- in memory protection function ( mpu ) ? eight protection areas can b e specified commonly for instructions and the data. ? control a ccess privilege in both privilege mode and user mode. ? bu ilt- in fpu (f loating point arithmetic ) ? ieee754 compliant ? f loating - point register 32 - bit 16 sets mb91590 series mn705-00009-3v0-e 4
chapter 1: overview 2 . features fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 5 2.2. peripheral f unctions this section explains peripheral functions of mb91590 series . ? clock generation (e quipped with sscg function) ? main oscillation (4mhz) ? sub oscillat i on (32 k hz ) or none sub oscillat i on ? pll multiplication rate : 1 to 32 times ? built - in p rogram flash capacity 1024 + 64kb ? built - in data flash memory (workflash) 64kb ? built - in ram capacity ? main ram 64kb ? backup ram 8 kb ? general - purpose ports (5v pin) : 63 (dual clock products : 61) ? included i 2 c pseudo open drain ports : 4 ? general - purpose ports (3v pin ) : 9 3 ? included 48 combined external bus interface (for gdc external memory i/f) ? external bus in terface ? gdc external memory for i/f use ? 25- bit address, 16 - bit data ? power supply voltage fixed to 3.3v ? dma controller ? up to 16 channels can be started simultaneously. ? 2 transfer factors ( internal peripheral request and software ) ? a/d converter ( successiv e approximation type) ? 8/10 - bit resolution : 32 channels ? conversion time : 3 s ? external interrupt input: 16 channels ? level ("h" / "l"), or edge detection ( rising or falling ) enabled ? lin - uart ? 6 channels, ch.2 to ch.7 ? uart, synchronous mode, lin - uart mod e is selectable. ? lin protocol revision 2. 1 is supported ? spi( serial peripheral interface ) supported ( synchronous mode ) ? full - duplex double buffering system ? lin synch break detection ( linked to the input capture ) ? built - in dedicated baud rate generator ? dma transfer support ed ? multi - function serial i/o ( with built - in transmission/reception fifo ) : 2 channels < uart (asynchronous serial interface) > ? full - duplex double buffering system, 16 - byte transmission fifo, 16 - byte reception fifo ? parity or no parity is selectable . ? built - in dedicated baud rate generator ? an external clock can be used as the transfer clock ? parity, frame, and overrun error detect functions provided ? dma transfer support ed ? full - duplex double buffering sy stem, 16 - byte transmission fifo , 16 - byte reception fifo ? spi supported; master and slave systems supported; 5 to 9 - bit data length can be set. ? built - in dedicated baud rate generator (master operation) ? an external clock can be entered. (slave operation) ? o verrun error detect function is provided ? dma transfer support ed mb91590 series mn705-00009-3v0-e 5
chapter 1: overview 2 . features fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 6 ? full - duplex double buffering system, 16 - byte transmission fifo, 16 - byte reception fifo ? lin protocol revision 2. 1 supported ? master and slave systems supported ? framing error and overrun error detection ? lin synch break generation and detection; lin synch delimiter generation ? built - in dedicated baud rate generator ? an external clock can be adjusted by the reload counter ? dma transfer support ed < i 2 c > ? full - duplex double buffering system, 16 - byte transmission fifo, 16 - byte reception fifo ? standard mode ( max. 100kbps ) / high - speed mode ( max. 400kbps ) supported ? dma transfer supported ( for transmission only ) ? can controller (c - can) : 3 channels ? trans fer speed : up to 1mbps ? 64- transmission/reception message buffering : 1 channel, 32- transmission/reception message buffering : 2 channels ? ppg : 16 - bit 24 channels ? reload timer : 16 - bit 4 channels ? free - run timer : 32- bit 2 channels (can select each c hannel for input capture, output compare) 32- bit 2 channels (lsyn ( lin synch field detection ) for exclusive input capture) ? input capture : 32- bit 6 channels ( linked to the free - run timer ) lsyn ( lin synch field detected ) e xclusi ve 32 - bit 2 channels (linked to the free - run timer) ? output compare : 32 - bit 4 channels ( linked to the free - run timer ) ? sound generator : 5 channels ? frequency and amplitude sequencers provided ? stepping motor controller : 6 channels ? 8/10 - bit pwm ? high curr ent output supported (4 lines 6 channels) ? can refer back electromotive force from the motor using pin - shared a dc ? real - time clock (rtc) (for day, hours, minutes, seconds) ? main oscillation frequency or sub oscillation frequency (dual clock product only) can be selected for the operation clock ? calibration: a hardware watchdog of the cr oscillation drive and real - time clock (rtc) of the sub clock drive(dual clock product only) ? the cr oscillation frequency can be trimmed ? the main clock to sub clock (dual clo ck product only) ratio can be corrected by setting the real - time clock prescaler ? clock supervisor ? monitoring abnormality (damage of crystal etc.) of sub oscillation ( 32 k hz ) ( dual clock products ) of the outside and main oscillation ( 4 mhz ) ? when abnorma lity is detected, it switches to the cr clock. ? base timer : 2 channels ? 16- bit timer ? any of four pwm/ppg/pwc/reload timer functions can be selected and used ? a 32 - b it timer can be used in 2 channels of cascade mode ? crc generation ? watchdog timer ? hardware wat chdog ? software watchdog ? nm i ? interrupt controller ? interrupt request batch read ? multiple interrupt s from peripherals can be read by a series of register s . ? i/o relocation ? peripheral function pins can be reassigned. mb91590 series mn705-00009-3v0-e 6
chapter 1: overview 2 . features fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 7 ? low - power consumption mode ? sleep / stop / watch / sub run mode ? stop (power shutdown) / watch (power shutdown) mode ? gdc part self - support power supply ? power on reset/internal l ow - voltage detection reset ? low - voltage detection reset ? gdc ? internal/memory frequency : 81mhz ? the resolution of the displa y which can support : 800 480 at the maximum screen overlay of three simultaneous layers at the maximum (window) size of the resolution which can be supported va ries depending on color format. ? analog video input (ntsc) ? digital video input (rgb666/555) ? y uv input (bt.656) ? video image expansion/reduction /invert function is supported ? rgb digital output (6 - bit 3) ? built - in 2d rendering engine the line drawing is supported. the bit b lt function is supported. display list operation is supported 8bpp indirect color argb - 1555 direct color alpha blending, anti - aliasing ? built - in sprite engine equipped with automatic display function when booted maximum of 512 sprites are supported 32 special sprites capable of automatic animation are supported. the command list execution is supported. 1bpp, 2bpp, 4bpp, 8bpp indirect color argb - 1555, rgb - 565, argb - 8888 direct color the color format for each sprite can be set. horizontal invert, vertical invert alpha blending ? built - in memory (800kb) ? device package : lqfp - 208, hqfp - 208 ? cmos 90nm technology ? power supplies ? 5v/3.3v power supply ? the internal 1.2v is generated from 5v/3.3v with the depression circuit. ? for i/o of an external bus and gdc, 3.3v power supply used. ? for the other i/o, 5v power supply used. ? there is a constraint about power on sequence ( 5v 3.3v) . mb91590 series mn705-00009-3v0-e 7
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 8 3. product line - up this section show s p roduct l ine - up of this series. table 3-1 : product line - up product item mb91f591b/s mb91f591bh/s cpu core fr81s technology 90nm package lqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 80mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll f lash main 576kb sub 64kb ram main 40kb backup 8 kb vram 260kb watchdog timer 1ch hardwar e 1ch software clock supervisor initial value "o ff " initial value "on" external low voltage detection reset yes internal low voltage detection reset yes nmi function yes dma controller 16ch can 1ch ( 64msg) 2ch ( 32msg) usart linx6 mfsx2 a/d converte r (8 bit/10bit ) 1unit/32ch r eload timer (16bit) 4ch b ase timer (16bit) 2ch f ree - run timer (32bit) 2ch i nput capture (32bit) 6ch o utput compare (32bit) 4ch ppg timer (16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub comp ensation function yes crc generator yes mb91590 series mn705-00009-3v0-e 8
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 9 product item mb91f591b/s mb91f591bh/s stepp ing motor control 6ch stop mode ( with power - shutdown ) supported power supply voltage micom : 4.5 v to 5.5v gdc : 3.0 v to 3.6v operating temperature - 40 to + 105 c allowable power [mw] 1250 others flash pr oduct on chip debugger yes mb91590 series mn705-00009-3v0-e 9
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 10 product item mb91f592b/s mb91f592bh/s mb91f594b/s mb91f594bh/s cpu core fr81s technology 90nm package lqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 80mhz maximum gdc operating fr equency 81mhz built - in cr oscillator 100khz system clock on chip pll f lash main 576kb 1088kb sub 64kb ram main 40kb 64kb backup 8kb vram 800kb watchdog timer 1ch hardware 1ch software clock supervisor initial value " o ff " initial value " on " initi al value " o ff " initial value " on " external low voltage detection reset yes internal low voltage detection reset yes nmi function yes dma controller 16ch can 1ch ( 64msg) 2ch ( 32msg) usart linx6 mfsx2 a/d converter (8 bit/10bit ) 1unit/32ch r eload tim er (16bit) 4ch b ase timer (16bit) 2ch f ree - run timer (32bit) 2ch i nput capture (32bit) 6ch o utput compare (32bit) 4ch ppg timer (16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generator yes stepp ing motor control 6ch mb91590 series mn705-00009-3v0-e 10
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overvie w fujitsu semiconductor confidential 11 product item mb91f592b/s mb91f592bh/s mb91f594b/s mb91f594bh/s stop mode ( with power - shutdown ) supported power supply voltage micom : 4.5 v to 5.5v gdc : 3.0 v to 3.6v operating temperature - 40 to +105 c allowable power [mw] 1250 others flash product on chip debugger yes mb91590 series mn705-00009-3v0-e 11
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 12 produc t item mb91f596b/s mb91f596bh/s mb91f597b/s mb91f597bh/s cpu core fr81s technology 90nm package hqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 128mhz maximum gdc operating frequency 81mhz built - in cr oscillator 10 0khz system clock on chip pll f lash main 576kb sub 64kb ram main 40kb backup 8kb vram 260kb 800kb watchdog timer 1ch hardware 1ch software clock supervisor initial value " o ff " initial value " o n " initial value " o ff " initial value " on " external lo w voltage detection reset yes internal low voltage detection reset yes nmi function yes dma controller 16ch can 1ch ( 64msg) 2ch ( 32msg) usart linx6 mfsx2 a/d converter (8 bit/10bit ) 1unit/32ch r eload timer (16bit) 4ch b ase timer (16bit) 2ch f ree - run timer (32bit) 2ch i nput capture (32bit) 6ch o utput compare (32bit) 4ch ppg timer (16bit) 24ch sound generator 5ch real - time clock yes external interrupt 16ch cr/sub compensation function yes crc generator yes stepp ing motor control 6ch mb91590 series mn705-00009-3v0-e 12
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 13 produc t item mb91f596b/s mb91f596bh/s mb91f597b/s mb91f597bh/s stop mode ( w ith power - shutdown ) supported power supply voltage micom : 4.5 v to 5.5v gdc : 3.0 v to 3.6v operating temperature - 40 to + 105 c allowable power [mw] 2500 others flash product on chip debugger yes mb91590 series mn705-00009-3v0-e 13
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 14 product item mb91f599b/s mb91f599bh/s cpu core fr81 s technology 90nm package hqfp208 sub clock yes (non - s series) no (s series) maximum cpu operating frequency 128mhz maximum gdc operating frequency 81mhz built - in cr oscillator 100khz system clock on chip pll f lash 1088kb 1088kb 64kb 64kb ram 64kb 64kb 8kb 8kb vram 800kb watchdog timer 1ch hardware 1ch software clock supervisor initial value " off " initial value "on" external low voltage detection reset yes internal low voltage detection reset yes nmi function yes dma 16ch can 1ch ( 64msg ) 2ch ( 32msg) usart linx6 mfsx2 a/d c onverter (8 bit/10bit ) 1unit/32ch r eload timer (16bit) 4ch b ase timer (16bit) 2ch f ree - run timer (32bit) 2ch i nput capture (32bit) 6ch o utput compare (32bit) 4ch ppg timer (16bit) 24ch sound generator 5ch real - time c lock yes external interrupt 16ch cr/sub compensation function yes crc generator yes stepp ing motor control 6ch mb91590 series mn705-00009-3v0-e 14
chapter 1: overview 3 . product line - up fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 15 product item mb91f599b/s mb91f599bh/s stop mode ( with power - shutdown ) supported power supply voltage micom : 4.5 v to 5.5v gdc : 3.0 v to 3.6v operating temperature - 40 to + 105 c allowable power [mw] 2500 others flash product on chip debugger yes mb91590 series mn705-00009-3v0-e 15
chapter 1: overview 4 . function overview fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 16 4. function overview this section show s f unction o verview of mb91590 series. table 4-1 : function o verview function features cpu 32 - bit ri sc m icrocontroller fr81s cpu c ore built - in memory protection function (mpu) 8 chan n els built - in floating - point operation (fpu) clock main oscillation : 4mhz (up to a maximum of 8mhz ) sub oscillation : 32khz or none pll multiplication rate: up to 32 time s of multiplication built - in cr oscillator as the count clock of hardware watchdog timer i/o ports each bit can be programmed for i/o or peripheral signals input thresholds, driving capacity, and pull - up/pull - down can be set. external bus interface 25 - b it address, 16 - bit data output for gdc external memory i/f power supply voltage is fixed to 3.3v internal bus interface on chip bus : 32 - bit, m aximum operating frequency : 128 mhz peripheral bus interface m aximum operating frequency : 40mhz 32- bit periphe ral bus , or 16 - bit peripheral bus (r- bus) * both of them operate in the same frequency. f lash i nterface wild register function provided . however, usable only during nowait operation. 1wait necessary to be added if operation frequency exceeds 80mhz. small sector (64kb size) is also supported. dma c ontroller up to 16 c hannels can be started simultaneously. the transfer cause (internal peripheral request or software) is selectable . burst or b lock transfer mode is selectable . - when two or more interrupt s are in one interrupt vector, it can select from which interrupt to generate the dma request . - when two or more interrupt s are in one interrupt vector, the interrupt cleared at the dma transfer completion can be selected. base t imer 16 - bit timer any of four p wm/ppg/pwc/reload timer functions can be selected and used . a 32 - bit timer can be used in 2 channels of cascade mode for the reload timer/pwc function. free - run t imer 32 - bit up counter input capture 32 - bit capture registers to detect a rising edge, a fa lling edge, or both edges . when an edge of pin input is detected, the counter value of 32 - bit free - run timer is latched and an interrupt request is generated. lin synch break/synch field linkage : input capture ch.0 lin - uart ch.2 input capture ch.1 lin - uart ch.3 i nput capture ch.2 lin - uart ch .4 input capture ch.3 lin - uart ch .5 input capture ch.4 lin - uart ch .6 input capture ch.5 lin - uart ch .7 lsyn exclusive input capture ch.6 multi - function serial ch .0 lsyn exclusive input capture ch.7 multi - function serial ch .1 mb91590 series mn705-00009-3v0-e 16
chapter 1: overview 4 . function overview fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 17 function features output c ompare an interrupt signal is output during collating with the 32 - bit free - run timer. reload t imer 16 - bit reload time r operation ( the toggle output or one - shot output can be select ed) event count function can be select ed. ppg the cycle and duty used for the one - shot square wave output and pwm output can be changed by the software. operation clock frequency : can be sel ected from following 4 types : pclk 1, 1/2 2 , 1/2 4 , 1/2 6 delay interrupt an interrupt for task switching is generated . the cpu interrupt request can be generated or canceled by the software. external interrupt 16 channel , independent interrupt factor : rising edge / f alling edge / "l" l evel / "h" l evel can be selected. support of edge input detection when returned to standby state. a/d converter built - in a/d converter 1ch of resolution in 10 - bit or 8 - bit able to sample the analog value from 32ch inpu t port conversion time : 3 s external trigger activation can be activated by the internal timer (16 - bit reload timer) lin - uart full - duplex system asynchronous/synchronous transfer ( with start/stop bit s) b uilt- in dedicated baud rate generator lin p rotocol, slave node supported , a nd lin synch break/synch field detectable spi(serial peripheral interface) supported ver s ion 2. 1 supported . multi - function serial any of uart/csio/lin - uart/i 2 c - uart functions c an be selected and use d. transmission fifo (16 - byte ) and reception fifo ( 16 -b yte ) are provided . rece ive interrupt factor (3 types ) - rece ive error d etection ( p arity, overrun, and f rame error) - data which amount is set for fifo memory can be received . - data below the fifo memory capacity is received, and an idle period longer tha n 8 clocks of baud rate clock is detected . transmission interrupt factor (2 types ) - n o transmission operation. - empty transmission fifo memory (including the time of transmissi on ) spi(serial peripheral interface) supported lin protocol revision 2.1 sup ported interrupt c ontroller detect s an interrupt request . set s an interrupt level . interrupt request batch read a generation of multiple interrupts from peripherals can be read by a series of registers . can i nterface can specifications version 2.0, par t a and part b satisfied 64 m essage buffer s 1ch an nel , 32 message buffer s 2ch an nels p lural messages are supported. flexible composition of acceptance filter : entire bit compare entire bit mask 2 portion bit mask u p to 1mbps s upport ed. can prescaler is mounted for the can operation clock stepping m otor c ontroller high current output 4 lines the pwm cycle can be set to 15.625khz (when the peripheral clock operates in 16mhz). c an refer back electromotive force from the motor using pin - sh ared ad c mb91590 series mn705-00009-3v0-e 17
chapter 1: overview 4 . function overview fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 18 function features sound generator in addition to the frequency data and amplitude data setting, the followings can be set : - decrement or increment data, and execution cycle - tone output pulse count (output interval) real -t ime c lock day/hours/minutes/seconds re gister main or sub oscillation frequency can be selected for the operation clock. sub clock correction function - the sub clock cycle error is monitored by the main clock. - the detected error is reflected on the second counter set value. an interrupt ca n be generated in unit of 0.5 second, seconds, minutes, hours, or day. calibration the real - time clock of the sub clock drive is corrected by comparison with the main clock. the cr oscillation frequency can be corrected by the comparison with the main c lock. software watchdog it counts while cpu is working. stops counting when the cpu is stopped . cycle can be selected from 16 kinds of pclk (2 9 to 2 24 ) cycles hardware watchdog c r - based cpu operation detect counter used against program overrun period : 260ms to 416ms ( usually , 328ms , depending on the accuracy of the cr oscillation) the calibration is possible with "rtc/wdt1 correction" circuit. it is the one that width is at the cycle that originates in the difference of manufacturing. note that it i s not because the cycle can be arbitrarily set. crc generation the crc code is displayed in the result register by writing in the input register one by one. internal power supply low voltage detection reset is generated when 1.2v voltage of the faction is observed, and it falls below. an internal power supply voltage is observed, the low voltage is set, and the flag is set by detection. low - voltage detection reset generation at low voltage detection graphic device interface maximum resolution: 800 480 ntsc/rgb666/555/bt.656 input support ed rbg666 output support ed sprite engine mounted line engine mounted vram : 800kb low - power consumption mode sleep mode stop mode watch mode stop mode (power shutdown) watch mode (power shutdown) gdc part independence power supply sub run mode i/o r elocation relocation peripheral function and number of branches - ppg 24 channels ( 4 branches for ch.1, 3 branches for ch.0 and ch.2 to ch.10, no branches for ch.11 to ch.23) . - input capture 6 channels 3 branches - lin- uart 4 channels 2 branches ( no relocation for the remaining 2 channels ) - reload timer 4 channels 3 branche s nmi r equest non - maskable interrupt signal that is entered from nmix pin. debug interface built - in ocd (on chip debug unit) mb91590 series mn705-00009-3v0-e 18
chapter 1: overview 5 . block diagram fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 19 5. block diag ram this section show s b lock diagram of this series. figure 5-1 block d iagram from master to slave from master to slave camera pixel fifo line buffer sprite engine command decoder display controller bus bridge line engine frame buffer video capture ntsc decoder adc c la mp i/o ( digital rgb) i/o ram sig rld dma external bus pin (for gdc external memory) rd y, a 00 - 24 , w ex ,r ex , cs0x,cs1x, d0-15 i/o (ext. bus) ext. bus external lcd fr 81 s c pu core regulator power-on reset cr oscillator instruction mpu data d ebug i nterface xbs cross ba r s wi tch xbs on chip bus ram flash main flash workflash 64kb ram ec c control ( xbs -ram) can (3ch) bus bridge ext.bus i/f ram ecc control backup -ram can prescaler rtc/wdt1 calibration i/o port setting lin-uart (6ch) free-run timer (2ch) multi-function serial interface (2ch) input capture (6ch) output compare(4ch) base-timer (2ch) pp g ( 24 ch) a /d converter gd c external control stepping motor controller ( 6ch) reload timer (4ch) watchdog timer (sw and hw) generation and clear of dma transfer request interrupt request batch read interrupt controller delay interrupt rstx nmix wo t clock control (clock setting, main timer, sub timer, pll timer) low-voltage detection (ext. power supply low-voltage detection) low-voltage detection (int. power supply low-voltage detection) nmi clock supervisor real time clock external interrupt input ( 16 ch) bus bridge ( 32 -bit 16 -bit) sound generator (5ch) cr c 16-bit peripheral bus 16-bit peripheral bus 32-bit peripheral bus peripheral bus bridge operation mode register bus performance counter dmac bus master regi ster on chip bus layer 2 on chip bus layer 1 i/o port ca nr x0-2, cantx0-2 m d0 ,m d1 ,m d2 ,p 12 7 s go 0-4,sga0-4 int0- 15 , input interception inhibiting signal sot2-7,sin2-7 , sck2-7 sot0-1,sin0-1, sck0-1 i cu 0-5 o cu 0-3 t io a0-1, t io b0-1 trg0-5, pp g0-23 adt g, an0-31 pwm1m0-5, pwm1p0-5, pwm2m0-5 tin0-3,tot0-3 f rc k0-1 wild register 16 32 i/o port external flash memory (for video) ahb bus bridge asynchro nous type clock control (divide setting), reset control, low-power consumption control asynchronous bus bridge (pclk1 ? pclk2) asynchronous bus bridge (pclk1 ? pclk2) mb91590 series mn705-00009-3v0-e 19
chapter 1: overview 6 . cpu fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 20 6. cpu this section explains g eneral - purpose register s and dedicated register s of cpu . 6.1 . general - purpose r egister s 6.2 . dedicated r egister s mb91590 series mn705-00009-3v0-e 20
chapter 1: overview 6 . cpu fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 21 6.1. general- purpose registers register s r0 to r 15 are a general - purpose register s. they are u sed as the accumulator s for various operation s and a s pointer s for memory access. figure 6-1 general - purpose r egister s 32 - bit initial value r0 undefined r1 undefined r2 undefined r3 undefined r4 undefined r5 undefined r6 undefined r7 undefined r8 undefined r9 undefined r 10 undefined r11 undefined r12 undefined r13 accumulator( ac) undefined r14 frame pointer (fp) undefined r15 ssp or usp 00000000 h among these 16 registers, the following register s are assume d to be used for special applications. th erefore , some instruction functions have been enchanced. ? r13: ac (a ccumulator ) ? r14: fp (frame pointer ) ? r15: sp (stack pointer ) the initial value during reset is undefined for registers r0 to r14. register r15 has 00000000 h (ssp value). mb91590 series mn705-00009-3v0-e 21
chapter 1: overview 6 . cpu fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 22 6.2. dedicated re gister s there are nine dedicated registers for 32 - bit length exclusive for various usages, and there is one dedicated register for 64 - bit length of the multiplication and division calculation. figure 6-2 list of dedicated r egister s initial value pc reset entry address ps ssr= 3 h ,ilm=01111 b ,scr=xx0 b ,ccr=0000xxxx b tbr 000ffc00 h rp undefined ssp 00000000 h usp undefined bp undefined fcr undefined esr 00000000 h m d undefined dedicated register is used for a specific purpose. in the fr family, the following dedicated registers are prepared. ? p rogram counter (pc) ? p rogram status (ps) ? t able base register (tbr) ? r eturn pointer (rp) ? s ystem stack pointe r (ssp) ? u ser stack pointer (usp) ? b ase pointer (bp) ? fpu control register (fcr) ? e xception status register (esr) ? m ultiplication and division register (md) mb91590 series mn705-00009-3v0-e 22
chapter 1: overview 7 . pin assignment fujitsu semiconductor limited chapter: o verview fujitsu semiconductor confidential 23 7. pin assignment this section shows p in a ssignment of mb91590 series. figure 7-1 pin assignment ( single clock product ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg6_2 ppg5_2 ppg0_1 ppg9_1 ppg4_2 ppg3_2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg7_2 - - - - - icu5_1 icu4_1 icu1_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot2 tot1 tot0 tin3 tin2 tin1 tin0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot3 int7 int6 trg4 - - trg3 int8 int15 int11 - ppg0_2 - - - - - - - - cmdtrg - - - - - - - - - - - - - - - - vin7 vin6 vin5 vin4 vin3 vin2 vin1 vin0 - - - - - sck5 sot5 sin5 sck4 sot4 sin4 sck3 sot3 sin3 - - adtg - - - - - - - - dckin csout hsin vsin cclk bin7 bin6 bin5 bin4 bin3 bin2 - - gin7 gin6 gin5 gin4 gin3 gin2 rin7 rin6 rin5 rin4 rin3 rin2 - - - - - ocu0 frck0 frck1 sgo3 sga3 sgo2 sga2 wot sgo1 rx2 tx2 - vss avcc3 avss3 vin refout avr3 avss3 avcc3 pg0 pg3 pg2 pg1 ph3 pc7 pc6 pc5 pc4 pc3 pc2 vcc3 vss pb7 pb6 pb5 pb4 pb3 pb2 pa7 pa6 pa5 pa4 pa3 pa2 vcc3 vss vcc5 p136 p137 vss md2 p122 p121 p120 p117 p116 p115 p114 p097 p094 p113 p112 p090 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 - - - - - - vcc3 1 156 dvcc - - - - - - - - - - - rout2 pd2 2 155 dvss - - - - - - - - - - - rout3 pd3 3 154 p087 pwm2m5 an31 icu4_2 ppg23 - - - - - - - rout4 pd4 4 153 p086 pwm2p5 an30 icu3_2 ppg22 - - - - - - - rout5 pd5 5 152 p085 pwm1m5 an29 icu2_2 ppg21 - - - - - - - rout6 pd6 6 151 p084 pwm1p5 an28 icu1_2 ppg20 - - - - - - - rout7 pd7 7 150 p083 pwm2m4 an27 icu0_2 ppg19 - - - - - - - gout2 pe2 8 149 p082 pwm2p4 an26 sck6 ppg18 - - - - - - - gout3 pe3 9 148 p081 pwm1m4 an25 sot6 ppg17 - - - - - - - gout4 pe4 10 147 p080 pwm1p4 an24 sin6 ppg16 - - - - - - - gout5 pe5 11 146 dvcc - - - - - - - - - - - gout6 pe6 12 145 dvss - - - - - - - - - - - gout7 pe7 13 144 p077 pwm2m3 an23 sck7_1 ppg15_1 - - - - - - - bout2 pf2 14 143 p076 pwm2p3 an22 sot7_1 ppg14_1 - - - - - - - bout3 pf3 15 142 p075 pwm1m3 an21 sin7_1 ppg13_1 - - - - - - - bout4 pf4 16 141 p074 pwm1p3 an20 - ppg12_1 - - - - - - - bout5 pf5 17 140 p073 pwm2m2 an19 - - - - - - - - - - vcc3 18 139 p072 pwm2p2 an18 - - - - - - - - - - vss 19 138 p071 pwm1m2 an17 - - - - - - - - - - c_3 20 137 p070 pwm1p2 an16 - - - - - - - - - bout6 pf6 21 136 dvcc - - - - - - - - - - - bout7 pf7 22 135 dvss - - - - - - - - - - - dckout pg4 23 134 p067 pwm2m1 an15 - - - - - - - - - vsync pg5 24 133 p066 pwm2p1 an14 - - - - - - - - - hsync pg6 25 132 p065 pwm1m1 an13 - - - - - - - - - deout pg7 26 131 p064 pwm1p1 an12 - - - - - ppg0 tin0_2 sin2_1 d0 p000 27 130 p063 pwm2m0 an11 - - - - - ppg1 tin1_2 sot2_1 d1 p001 28 129 p062 pwm2p0 an10 - - - - - ppg2 tin2_2 sck2_1 d2 p002 29 128 p061 pwm1m0 an9 - - - - - ppg3 tin3_2 sin3_1 d3 p003 30 127 p060 pwm1p0 an8 - - - - - ppg4 tot0_2 sot3_1 d4 p004 31 126 dvcc - - - - - - - ppg5 tot1_2 sck3_1 d5 p005 32 125 dvss - - - - - - - ppg6 tot2_2 - d6 p006 33 124 c_1 - - - - - - - ppg7 tot3_2 - d7 p007 34 123 vss - - - - - - - - - - d8 p010 35 122 vcc5 - - - - - - - - - - - - vss 36 121 p107 sgo4_1 an7 - - - ppg5_1 - - - - - - vcc3 37 120 p106 sga4_1 an6 - - - ppg4_1 - - - rout0 d9 p011 38 119 p105 sck5_1 an5 tot1_1 - - ppg3_1 - - - rout1 d10 p012 39 118 p104 sot5_1 an4 tot0_1 - - ppg2_1 - - - gout0 d11 p013 40 117 p103 sin5_1 an3 tin3_1 - - ppg1_1 - - - gout1 d12 p014 41 116 p102 sck4_1 an2 tin2_1 - - ppg10 - - - bout0 d13 p015 42 115 p101 sot4_1 an1 tin1_1 - - ppg9 - - - bout1 d14 p016 43 114 p100 sin4_1 an0 tin0_1 - - ppg8 - - - - d15 p017 44 113 avss5/avrl5 - - - - - - - - - - wex p020 45 112 avrh5 - - - - - - - - - - cs0x p021 46 111 avcc5 - - - - - - - - - - cs1x p022 47 110 p125 ocu3 - - icu0 - ppg10_2 - - - - rex p023 48 109 p124 ocu2 - - icu5_2 - ppg9_2 - - - - - p024 49 108 p123 ocu1 - - - - ppg8_2 - - - - - p025 50 107 p096 rx0 - int9 - - - - - - - a00 p026 51 106 p095 tx0 - - - - ppg10_1 - - - - - - vss 52 105 vcc5 - - - - - - 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vcc3 p027 p030 p031 p032 p033 p034 p035 p036 p037 p040 p041 p042 p043 p044 p045 p046 p047 vcc3 vss c_2 p050 p051 p052 p053 p054 p055 p056 p057 vss x1 x0 md1 md0 rstx vss vcc5 p126 p127 p130 p131 p132 p133 p134 nmix p091 p092 p093 p110 p111 debug i/f vss - a01 a02 a03 a04 a05 a06 a07 a08 a09 a10 a11 a12 a13 a14 a15 a16 a17 - - - a18 a19 a20 a21 a22 a23 a24 rdy - - - - - - - - trg0 - - trg1 - trg5 trg2 - sga0 sgo0 sga1 tx1 rx1 - - - - - - - - - - - - - - - - - - - - - - - - - - spi_do spi_di spi_sck spi_xcs - - - - - - - - - sin0 sot0 sck0 - - ppg11_1 ppg1_3 - sin2 sck2 sot2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sin1 sot1 sck1 - - int12 int13 int14 - int10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - int1 - int0 int4 int2 int3 int5 - tot2_1 tot3_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - icu1 icu2 icu3 icu4 icu5 - icu2_1 icu0_1 icu3_1 - - - - - - - - - - - - - - - - - - tioa0 tioa1 tiob0 tiob1 - - ppg6_1 ppg7_1 ppg8_1 ppg1_2 ppg2_2 - - fr+gdc(g1) top view lqfp-208 / hqfp-208 (single clock product) (single clock product) debugif f r+gdc mb91590 series mn705-00009-3v0-e 23
chapter 1: overview 7 . pin assignment fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 24 figure 7-2 pin assignment ( dual clock product ) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg6_2 ppg5_2 ppg0_1 ppg9_1 ppg4_2 ppg3_2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - ppg7_2 - - - - - icu5_1 icu4_1 icu1_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot2 tot1 tot0 tin3 tin2 tin1 tin0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - tot3 int7 int6 trg4 - - trg3 int8 int15 int11 - ppg0_2 - - - - - - - - cmdtrg - - - - - - - - - - - - - - - - vin7 vin6 vin5 vin4 vin3 vin2 vin1 vin0 - - - - - sck5 sot5 sin5 sck4 sot4 sin4 sck3 sot3 sin3 - - adtg - - - - - - - - dckin csout hsin vsin cclk bin7 bin6 bin5 bin4 bin3 bin2 - - gin7 gin6 gin5 gin4 gin3 gin2 rin7 rin6 rin5 rin4 rin3 rin2 - - - (x1a) (x0a) - - ocu0 frck0 frck1 sgo3 sga3 sgo2 sga2 wot sgo1 rx2 tx2 - vss avcc3 avss3 vin refout avr3 avss3 avcc3 pg0 pg3 pg2 pg1 ph3 pc7 pc6 pc5 pc4 pc3 pc2 vcc3 vss pb7 pb6 pb5 pb4 pb3 pb2 pa7 pa6 pa5 pa4 pa3 pa2 vcc3 vss vcc5 vss md2 p122 p121 p120 p117 p116 p115 p114 p097 p094 p113 p112 p090 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 - - - - - - vcc3 1 156 dvcc - - - - - - - - - - - rout2 pd2 2 155 dvss - - - - - - - - - - - rout3 pd3 3 154 p087 pwm2m5 an31 icu4_2 ppg23 - - - - - - - rout4 pd4 4 153 p086 pwm2p5 an30 icu3_2 ppg22 - - - - - - - rout5 pd5 5 152 p085 pwm1m5 an29 icu2_2 ppg21 - - - - - - - rout6 pd6 6 151 p084 pwm1p5 an28 icu1_2 ppg20 - - - - - - - rout7 pd7 7 150 p083 pwm2m4 an27 icu0_2 ppg19 - - - - - - - gout2 pe2 8 149 p082 pwm2p4 an26 sck6 ppg18 - - - - - - - gout3 pe3 9 148 p081 pwm1m4 an25 sot6 ppg17 - - - - - - - gout4 pe4 10 147 p080 pwm1p4 an24 sin6 ppg16 - - - - - - - gout5 pe5 11 146 dvcc - - - - - - - - - - - gout6 pe6 12 145 dvss - - - - - - - - - - - gout7 pe7 13 144 p077 pwm2m3 an23 sck7_1 ppg15_1 - - - - - - - bout2 pf2 14 143 p076 pwm2p3 an22 sot7_1 ppg14_1 - - - - - - - bout3 pf3 15 142 p075 pwm1m3 an21 sin7_1 ppg13_1 - - - - - - - bout4 pf4 16 141 p074 pwm1p3 an20 - ppg12_1 - - - - - - - bout5 pf5 17 140 p073 pwm2m2 an19 - - - - - - - - - - vcc3 18 139 p072 pwm2p2 an18 - - - - - - - - - - vss 19 138 p071 pwm1m2 an17 - - - - - - - - - - c_3 20 137 p070 pwm1p2 an16 - - - - - - - - - bout6 pf6 21 136 dvcc - - - - - - - - - - - bout7 pf7 22 135 dvss - - - - - - - - - - - dckout pg4 23 134 p067 pwm2m1 an15 - - - - - - - - - vsync pg5 24 133 p066 pwm2p1 an14 - - - - - - - - - hsync pg6 25 132 p065 pwm1m1 an13 - - - - - - - - - deout pg7 26 131 p064 pwm1p1 an12 - - - - - ppg0 tin0_2 sin2_1 d0 p000 27 130 p063 pwm2m0 an11 - - - - - ppg1 tin1_2 sot2_1 d1 p001 28 129 p062 pwm2p0 an10 - - - - - ppg2 tin2_2 sck2_1 d2 p002 29 128 p061 pwm1m0 an9 - - - - - ppg3 tin3_2 sin3_1 d3 p003 30 127 p060 pwm1p0 an8 - - - - - ppg4 tot0_2 sot3_1 d4 p004 31 126 dvcc - - - - - - - ppg5 tot1_2 sck3_1 d5 p005 32 125 dvss - - - - - - - ppg6 tot2_2 - d6 p006 33 124 c_1 - - - - - - - ppg7 tot3_2 - d7 p007 34 123 vss - - - - - - - - - - d8 p010 35 122 vcc5 - - - - - - - - - - - - vss 36 121 p107 sgo4_1 an7 - - - ppg5_1 - - - - - - vcc3 37 120 p106 sga4_1 an6 - - - ppg4_1 - - - rout0 d9 p011 38 119 p105 sck5_1 an5 tot1_1 - - ppg3_1 - - - rout1 d10 p012 39 118 p104 sot5_1 an4 tot0_1 - - ppg2_1 - - - gout0 d11 p013 40 117 p103 sin5_1 an3 tin3_1 - - ppg1_1 - - - gout1 d12 p014 41 116 p102 sck4_1 an2 tin2_1 - - ppg10 - - - bout0 d13 p015 42 115 p101 sot4_1 an1 tin1_1 - - ppg9 - - - bout1 d14 p016 43 114 p100 sin4_1 an0 tin0_1 - - ppg8 - - - - d15 p017 44 113 avss5/avrl5 - - - - - - - - - - wex p020 45 112 avrh5 - - - - - - - - - - cs0x p021 46 111 avcc5 - - - - - - - - - - cs1x p022 47 110 p125 ocu3 - - icu0 - ppg10_2 - - - - rex p023 48 109 p124 ocu2 - - icu5_2 - ppg9_2 - - - - - p024 49 108 p123 ocu1 - - - - ppg8_2 - - - - - p025 50 107 p096 rx0 - int9 - - - - - - - a00 p026 51 106 p095 tx0 - - - - ppg10_1 - - - - - - vss 52 105 vcc5 - - - - - - 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 vcc3 p027 p030 p031 p032 p033 p034 p035 p036 p037 p040 p041 p042 p043 p044 p045 p046 p047 vcc3 vss c_2 p050 p051 p052 p053 p054 p055 p056 p057 vss x1 x0 md1 md0 rstx vss vcc5 p126 p127 p130 p131 p132 p133 p134 nmix p091 p092 p093 p110 p111 debug i/f vss - a01 a02 a03 a04 a05 a06 a07 a08 a09 a10 a11 a12 a13 a14 a15 a16 a17 - - - a18 a19 a20 a21 a22 a23 a24 rdy - - - - - - - - trg0 - - trg1 - trg5 trg2 - sga0 sgo0 sga1 tx1 rx1 - - - - - - - - - - - - - - - - - - - - - - - - - - spi_do spi_di spi_sck spi_xcs - - - - - - - - - sin0 sot0 sck0 - - ppg11_1 ppg1_3 - sin2 sck2 sot2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - sin1 sot1 sck1 - - int12 int13 int14 - int10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - int1 - int0 int4 int2 int3 int5 - tot2_1 tot3_1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - icu1 icu2 icu3 icu4 icu5 - icu2_1 icu0_1 icu3_1 - - - - - - - - - - - - - - - - - - tioa0 tioa1 tiob0 tiob1 - - ppg6_1 ppg7_1 ppg8_1 ppg1_2 ppg2_2 - - fr+gdc(g2) top view lqfp-208 / hqfp-208 (dual clock product) (dual clock product) debugif fr+gdc mb91590 series mn705-00009-3v0-e 24
chapter 1: overview 8 . package dimensions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 25 8. package dimensions th is section shows package dimensions of mb91590 series. figure 8-1 lqfp - 208( fpt - 208p - m06 ) package dimensions 208-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 28.0 28.0 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 2.55 g code (reference ) p-lfqfp208-28 28-0.5 0 208-pin plastic lqfp (fpt -208p-m06) (fpt-208p-m06) c 2003-2010 fujitsu semiconductor limited f208027s-c-3-5 details of "a" part 0.25(.010) (stand off) (.004.002) 0.100.05 (.024.006) 0.600.15 1.50 +0.20 ?0.10 +.008 ?.004 .059 0 ~8 "a" 0.08(.003) (.006.002) 0.1450.055 index 1 lead no. 52 53 104 105 156 157 208 0.50(.020) 0.08(.003) m (.009.002) 0.220.05 28.000.10(1.102.004)sq 30.000.20(1.181.008)sq (mounting height) * dimensions in mm (inches). note: the values in parentheses are reference values. note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. please confirm the latest package dimension by following ur l. http://edevice.fujitsu.com/package/ en - search/ mb91590 series mn705-00009-3v0-e 25
chapter 1: overview 8 . package dimensions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 26 figure 8-2 hqfp - 208(fpt - 208p - m04) package dimensions ( under planning ) 208-pin plastic qfp lead pitch 0.50 m m pa ck age width pa ck age lengt h 28.0 mm 28.0 mm lead shape gullwing sealing method plastic mold mounting height 3.95 mm ma x we ight 5.71 g remark 208-pin plastic qfp (fpt -208p-m04) (fpt-208p-m04) c 2003-2010 fujitsu semiconductor limited f208020s-c-3-6 .148 ?.012 +.008 ?0.30 +0.20 3.75 details of "a" part 0.500.20 (.020.008) 0.600.15 (.024.006) 0.25(.010) (stand off) 0.40 +0.10 ?0.15 +.004 ?.006 .016 0 ~8 1 lead no. 52 53 104 105 156 157 208 "a" 0.08(.003) 0.50(.020) 0.220.05 (.009.002) 0.08(.003) m 30.600.20(1.205.008)sq .007 ?.003 +.001 ?0.08 +0.03 0.17 index (mounting height) dimensions in mm (inches). note: the values in p arentheses a re reference values. note 1) * : these dimensions do not include resin protrusion . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. low heat resistance type please confirm the latest package dimension by following url. http://edevice.fujitsu .com/package/ en - search/ mb91590 series mn705-00009-3v0-e 26
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 27 9. explanation of pin functions the pin function list of the mb91590 series is shown. table 9-1 list of pin functions pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 84 x0 l main clock oscillation input pin 83 x1 l main clock oscillation output pin 1 71 ( dual clock product ) x0a n sub clock oscillation input pin 1 72 ( dual clock product ) x1a n sub clock oscillation output pin 171 ( s ingle clock product ) p137 a general - purpose i/o port 1 72 ( single clock product ) p136 a general - purpose i/o port 97 nmix n f 1 non - masking interrupt input pin 170 vss gnd pin 87 rstx n f 1 external reset input pin 86 md0 p mode pin 0 85 md1 p mode pin 1 169 md2 f 2 mode pin 2 27 p000 o general - purpose i/o port (3v pin) d0 external bus / data bit0 i/o pin sin2_1 lin - uart ch . 2 serial data input pin (1) tin0_2 reload timer ch . 0 event input pin (2) ppg0 ppg ch . 0 output p in 28 p001 o general - purpose i/o port (3v pin) d1 external bus / data bit1 i/o pin sot2_1 lin - uart ch . 2 serial data output pin (1) tin1_2 reload timer ch . 1 event input pin (2) ppg1 ppg ch . 1 output pin mb91590 series mn705-00009-3v0-e 27
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 28 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 29 p002 o general - purpose i/o port (3v pin) d2 external bus / data bit2 i/o pin sck2_1 lin - uart ch .2 clock i/o pin (1) tin2_2 reload timer ch . 2 event input pin (2) ppg2 ppg ch . 2 output pin 30 p003 o general - purpose i/o port (3v pin) d3 external bus / data b it3 i/o pin sin3_1 lin - uart ch . 3 serial data input pin (1) tin3_2 reload timer ch . 3 event input pin (2) ppg3 ppg ch . 3 output pin 31 p004 o general - purpose i/o port (3v pin) d4 external bus / data bit4 i/o pin sot3_1 lin - uart ch. 3 serial data output pin (1) tot0_2 reload timer ch.0 output pin (2) ppg4 ppg ch.4 output pin 32 p005 o general - purpose i/o port (3v pin) d5 external bus / data bit5 i/o pin sck3_1 lin - uart ch.3 clock i/o pin (1) tot1_2 reload t imer ch.1 output pin (2) ppg5 ppg ch.5 output pin 33 p006 o general - purpose i/o port (3v pin) d6 external bus / data bit6 i/o pin tot2_2 reload timer ch.2 output pin (2) ppg6 ppg ch.6 output pin 34 p007 o general - purpose i/o port (3v pin) d7 external bus / data bit7 i/o pin tot3_2 reload timer ch.3 output pin (2) ppg7 ppg ch.7 output pin 35 p010 o general - purpose i/o port (3v pin) d 8 external bus / data bit8 i/o pin 38 p011 o general - purpose i/o port (3v p in) d9 external bus / data bit9 i/o pin rout0 display digital r0 output pin mb91590 series mn705-00009-3v0-e 28
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overv iew fujitsu semiconductor confidential 29 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 39 p012 o general - purpose i/o port (3v pin) d 10 external bus / data bit10 i/o pin rout1 display digital r1 output pin 40 p013 o general - purpose i/o port (3v pin) d 11 external bus / data bit11 i/o pin gout0 display digital g0 output pin 41 p014 o general - purpose i/o port (3v pin) d 12 external bus / data bit12 i/o pin gout1 display digital g1 output pin 42 p015 o general - purpos e i/o port (3v pin) d 13 external bus / data bit13 i/o pin bout0 display digital b0 output pin 43 p016 o general - purpose i/o port (3v pin) d 14 external bus / data bit14 i/o pin bout1 display digital b1 output pin 44 p017 o general - purpose i/o port (3v pin) d 15 external bus / data bit15 i/o pin 45 p020 o general - purpose i/o port (3v pin) wex external bus / write enable output pin 46 p021 o general - purpose i/o port (3v pin) cs0 x external bus / chip select 0 output pin 47 p022 o general - purpose i/o port (3v pin) cs1 x external bus / chip select 1 output pin 48 p023 o general - purpose i/o port (3v pin) r ex external bus / read enable output pin 49 p024 o eneral - purpose i/o port (3v pin) 50 p025 o g eneral - purpose i/o port (3v pin) 51 p026 o general - purpose i/o port (3v pin) a00 external bus / address bit0 output pin 54 p027 o general - purpose i/o port (3v pin) a01 external bus /address bit1 output pin 55 p030 o general - purpose i/o p ort (3v pin) a02 external bus / address bit2 output pin mb91590 series mn705-00009-3v0-e 29
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 30 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 56 p031 o general - purpose i/o port (3v pin) a03 external bus /address bit3 output pin 57 p032 o general - purpose i/o port (3v pin) a04 external bus / address bit4 output pin 58 p0 33 o general - purpose i/o port (3v pin) a05 external bus / address bit5 output pin 59 p034 o general - purpose i/o port (3v pin) a06 external bus / address bit6 output pin 60 p035 o general - purpose i/o port (3v pin) a07 external bus / a ddress bit7 output pin 61 p036 o general - purpose i/o port (3v pin) a08 external bus/address bit8 output pin 62 p037 o general - purpose i/o port (3v pin) a09 external bus/address bit9 output pin 63 p040 o general - purpose i/o port (3v pin) a10 external bus / address bit10 output pin 64 p041 o general - purpose i/o port (3v pin) a11 external bus / address bit11 output pin 65 p042 o general - purpose i/o port (3v pin) a12 external bus / address bit12 output pin 66 p043 o ge neral - purpose i/o port (3v pin) a13 external bus / address bit13 output pin 67 p044 o general - purpose i/o port (3v pin) a14 external bus / address bit14 output pin 68 p045 o general - purpose i/o port (3v pin) a15 external bus / address bit15 output pin 69 p046 o general - purpose i/o port (3v pin) a16 external bus / address bit 1 6 output pin 70 p047 o general - purpose i/o port (3v pin) a17 external bus / address bit17 output pin 74 p050 o general - purpose i/o port (3v pin) a18 external bus / address bit18 output pin 75 p051 o general - purpose i/o port (3v pin) a19 external bus / address bit19 output pin mb91590 series mn705-00009-3v0-e 30
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 31 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 76 p052 o general - purpose i/o port (3v pin) a20 external bus / address bit20 output pin 77 p053 o gene ral - purpose i/o port (3v pin) a21 external bus / address bit21 output pin spi_do spi data output pin 78 p054 o general - purpose i/o port (3v pin) a22 external bus / address bit22 output pin spi_di spi data input pin 79 p055 o genera l- purpose i/o port (3v pin) a23 external bus / address bit23 output pin spi_sck spi clock output pin 80 p056 o general - purpose i/o port (3v pin) a24 external bus / address bit24 output pin spi_xcs spi chip select output pin 81 p057 o general - purpose i/o port (3v pin) rdy external bus / wait input pin 127 p060 e general - purpose i/o port pwm1p0 smc ch . 0 output pin an8 adc analog 8 input pin 128 p061 e general - purpose i/o port pwm1m0 smc ch .0 output pin an9 adc analog 9 input pin 129 p062 e general - purpose i/o port pwm2p0 smc ch . 0 output pin an10 adc analog 10 input pin 130 p063 e general - purpose i/o port pwm2m0 smc ch .0 output pin an11 adc analog 11 input pin 131 p064 e general - purpose i/o port pwm1p1 smc ch . 1 output pin an12 adc analog 12 input pin mb91590 series mn705-00009-3v0-e 31
chapter 1: overview 9 . explanatio n of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 32 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 132 p065 e general - purpose i/o port pwm1m1 smc ch . 1 output pin an13 adc analog 13 input pin 133 p066 e general - purpose i/o port pwm2p1 smc ch .1 output pin an14 adc analog 14 input pin 134 p067 e general - purpose i/o port pwm2m1 smc ch .1 output pin an15 adc analog 15 input pin 137 p070 e general - purpose i/o port pwm1p2 smc ch .2 output pin an16 adc analog 16 input pi n 138 p071 e general - purpose i/o port pwm1m2 smc ch .2 output pin an17 adc analog 17 input pin 139 p072 e general - purpose i/o port pwm2p2 smc ch . 2 output pin an18 adc analog 18 input pin 140 p073 e general - purpose i/o port pwm 2m2 smc ch . 2 output pin an19 adc analog 19 input pin 141 p074 e general - purpose i/o port pwm1p3 smc ch . 3 output pin an20 adc analog 20 input pin ppg12_1 ppg ch. 12 output pin (1) 142 p075 e general - purpose i/o port pwm1m3 s mc ch . 3 output pin an21 adc analog 21 input pin sin7 _1 lin - uart ch . 7 serial data input pin ppg13_1 ppg ch. 13 output pin (1) 143 p076 e general - purpose i/o port pwm2p3 smc ch . 3 output pin an22 adc analog 22 input pin sot7 _1 lin - uart ch . 7 serial data output pin ppg14_1 ppg ch. 14 output pin (1) mb91590 series mn705-00009-3v0-e 32
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 33 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 144 p077 e general - purpose i/o port pwm2m3 smc ch . 3 output pin an23 adc analog 23 input pin sck7 _1 lin - uart ch . 7 clock i/o pin ppg15_1 ppg ch. 15 output pin (1 ) 147 p080 e general - purpose i/o port pwm1p4 smc ch .4 output pin an24 adc analog 24 input pin sin6 lin - uart ch . 6 serial data input pin ppg16 ppg ch . 16 output pin 148 p081 e general - purpose i/o port pwm1m4 smc ch.4 output pi n an25 adc analog 25 input pin sot6 lin - uart ch.6 serial data output pin ppg17 ppg ch.17 output pin 149 p082 e general - purpose i/o port pwm2p4 smc ch.4 output pin an26 adc analog 26 inpu t pin sck6 lin - uart ch.6 clock i/ o pin ppg18 ppg ch.18 output pin 150 p083 e general - purpose i/o port pwm2m4 smc ch.4 output pin an27 adc analog 27 input pin icu0_2 input capture ch.0 input pin (2) ppg19 ppg ch.19 output pin 151 p084 e general - purpose i/o port pwm1p5 smc ch.5 output pin an28 adc analog 28 input pin icu1_2 input capture ch.1 input pin (2) ppg20 ppg ch.20 output pin 152 p085 e general - purpose i/o port pwm1m5 smc ch.5 output pin an29 adc analog 29 input pin icu2_2 input capture ch.2 input pin (2) ppg21 ppg ch.21 output pin mb91590 series mn705-00009-3v0-e 33
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 34 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 153 p086 e general - purpose i/o port pwm2p5 smc ch.5 output pin an30 adc analog 30 input pin icu3_2 input capture ch.3 input pin (2) ppg22 ppg ch.22 output pin 154 p087 e general - purpose i/o port pwm2m5 smc ch.5 output pin an31 adc analog 31 input pin icu4_2 input capture ch.4 input pin (2) ppg23 ppg ch.23 output pin 157 p090 a general - purpose i/o port adtg a/d converter ext ernal trigger input pin ppg0_2 ppg ch.0 output pin (2) 98 p091 c general - purpose i/o port sga0 sound generator ch.0 sga output pin sin2 lin - uart ch.2 serial data input pin int12 int12 external interrupt input pin tot2_1 reload timer ch.2 output pin (1) icu2_1 input capture ch.2 input pin (1) ppg6_1 ppg ch.6 output pin (1) 99 p092 c general - purpose i/o port sgo0 sound generator ch.0 sgo output pin sck2 lin - uart ch.2 clock i/o pin int13 int13 external interrupt input pin tot3_1 reload timer ch.3 output pin (1) icu0_1 input capture ch.0 input pin (1) ppg7_1 ppg ch.7 output pin (1) 100 p093 c general - purpose i/o port sga1 sound generator ch.1 sga output pin sot2 lin - uart ch.2 serial data output pin int14 int14 external interrupt input pin icu3_1 input capture ch.3 input pin (1) ppg8_1 ppg ch.8 output pin (1) mb91590 series mn705-00009-3v0-e 34
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 35 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 160 p094 c general - purpose i/o port sgo1 sound generator ch.1 sgo output pin sin3 lin - uart ch.3 serial data input pin int15 int15 external interrupt input pin icu1_1 input capture ch. 1 input pin (1) ppg9_1 ppg ch.9 output pin (1) 106 p095 a general - purpose i/o port tx0 can transmission data0 output pin ppg10_1 ppg ch.10 output pin (1) 107 p096 a general - purpose i/o port rx0 can reception data0 input pin int9 int9 external interrupt input pin 161 p097 c general - purpose i/o port wot rtc overflow output pin sot3 lin - uart ch.3 serial d ata output pin int8 int8 external interrupt input pin tin0 reload timer ch.0 event input pin icu4_1 input capture ch.4 input pin (1) ppg0_1 ppg ch.0 output pin (1) 114 p100 c general - purpose i/o port sin4_1 lin - uart ch.4 serial data input pin (1) an0 adc analog 0 input pin tin0_1 reload timer ch.0 event input pin (1) ppg8 ppg ch.8 output pin 115 p101 c general - purpose i/o port sot4_1 lin - uart ch.4 serial data output pin (1) an1 adc analog 1 input pin tin1_1 reload timer ch.1 event input pin (1) ppg9 ppg ch.9 output pin 116 p102 c general - purpose i/o port sck4_1 lin - uart ch.4 clock i/o pin (1) an2 adc analog 2 input pin tin2_1 reload timer ch.2 event input pin (1) ppg10 ppg ch.10 output pin mb91590 series mn705-00009-3v0-e 35
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 36 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 117 p103 c general - purpose i/o port sin5_1 lin - uart ch.5 serial data input pin (1) an3 adc analog 3 input pin tin3_1 reload timer ch.3 event input pin (1) ppg1_1 ppg ch.1 output pin (1) 118 p104 c gener al - purpose i/o port sot5_1 lin - uart ch.5 serial data output pin (1) an4 adc analog 4 input pin tot0_1 reload timer ch.0 output pin (1) ppg2_1 ppg ch.2 output pin (1) 119 p105 c general - purpose i/o port sck5_1 lin - uart ch.5 clock i/o pin (1) an5 adc analog 5 input pin tot1_1 reload timer ch.1 output pin (1) ppg3_1 ppg ch.3 output pin (1) 120 p106 c general - purpose i/o port sga4_1 sound generator ch.4 sga output pin an6 adc analog 6 input pin ppg4_1 ppg ch.4 output pin (1) 121 p107 c general - purpose i/o port sgo4_1 sound generator ch.4 sgo output pin an7 adc analog 7 input pin ppg5_1 ppg ch.5 output pin (1) 101 p110 c general - purpose i/o port tx1 can transmission data1 out put pin ppg1_2 ppg ch.1 output pin (2) 102 p111 c general - purpose i/o port rx1 can reception data 1 input pin int10 int10 external interrupt input pin ppg2_2 ppg ch.2 output pin (2) 158 p112 c general - purpose i/o port tx2 ca n transmission data 2 output pin ppg3_2 ppg ch.3 output pin (2) mb91590 series mn705-00009-3v0-e 36
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overv iew fujitsu semiconductor confidential 37 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 159 p113 c general - purpose i/o port rx2 can reception data 2 input pin int11 int11 external interrupt input pin ppg4_2 ppg ch.4 output pin (2) 162 p114 c gene ral - purpose i/o port sga2 sound generator ch.2 sga output pin sck3 lin - uart ch.3 clock i/o pin trg3 ppg trigger 3 input pin ( ch.12 to ch.15) tin1 reload timer ch.1 event input pin icu5_1 input capture ch.5 input pin (1) 163 p115 c general - purpose i/o port sgo2 sound generator ch.2 sgo output pin sin4 lin - uart ch.4 serial data input pin tin2 reload timer ch.2 event input pin 164 p116 c general - purpose i/o port sga3 sound generator ch.3 sga output pin s ot4 lin - uart ch.4 serial data output pin tin3 reload timer ch.3 event input pin 165 p117 c general - purpose i/o port sgo3 sound generator ch.3 sgo output pin sck4 lin - uart ch.4 clock i/o pin trg4 ppg trigger 4 input pin ( ch.16 to ch.19) tot0 reload timer ch.0 output pin 166 p120 c general - purpose i/o port frck1 free - run timer 1 clock input pin sin5 lin - uart ch.5 serial data input pin int6 int6 external interrupt input pin tot1 reload timer ch.1 output pin ppg5_2 ppg ch.5 output pin (2) mb91590 series mn705-00009-3v0-e 37
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 38 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 167 p121 c general - purpose i/o port frck0 free - run timer 0 clock input pin sot5 lin - uart ch.5 serial data output pin int7 int7 external interrupt input pin tot2 reload timer ch.2 out put pin ppg6_2 ppg ch.6 output pin (2) 168 p122 c general - purpose i/o port ocu0 output compare ch.0 output pin sck5 lin - uart ch.5 clock i/o pin tot3 reload timer ch.3 output pin ppg7_2 ppg ch.7 output pin (2) 108 p123 a ge neral - purpose i/o port ocu1 output compare ch.1 output pin ppg8_2 ppg ch.8 output pin (2) 109 p124 a general - purpose i/o port ocu2 output compare ch.2 output pin icu5_2 input capture ch.5 input pin (2) ppg9_2 ppg ch.9 output p in (2) 110 p125 a general - purpose i/o port ocu3 output compare ch.3 output pin icu0 input capture ch.0 input pin ppg10_2 ppg ch.10 output pin (2) 90 p126 a general - purpose i/o port trg0 ppg trigger 0 input pin ( ch.0 to ch.3) si n0 multi - uart ch.0 serial data input pin int1 int1 external interrupt input pin 91 p127 k general - purpose i/o port sot0 multi - uart ch.0 serial data output pin / i 2 c ch.0 serial data i/o pin mb91590 series mn705-00009-3v0-e 38
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 39 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 92 p130 k general - purpose i/o port sck0 multi - uart ch.0 clock i/o pin / i 2 c ch.0 clock i/o pin int0 int0 external interrupt input pin icu1 input capture ch.1 input pin tioa0 base timer tioa0 output pin 93 p131 a general - purpose i/o port trg1 ppg trigger 1 input pin ( ch.4 to ch.7) sin1 multi - uart ch.1 serial data input pin int4 int4 external interrupt input pin icu2 input capture ch.2 input pin tioa1 base timer tioa1 output / input pin 94 p132 k general - purpose i/o port sot1 multi - uart ch.1 seri al data output pin / i 2 c ch.1 serial data i/o pin int2 int2 external interrupt input pin icu3 input capture ch.3 input pin tiob0 base timer tiob0 input pin 95 p133 k general - purpose i/o port trg 5 ppg trigger 5 input pin ( ch.20 to ch. 23) ppg11_1 ppg ch.11 output pin (1) sck1 multi - uart ch.1 clock i/o pin / i 2 c ch . 1 clock i/o pin int3 int3 external interrupt input pin icu4 input capture ch.4 input pin tiob1 base timer tiob1 input pin 96 p134 a general - purpose i/o port trg2 ppg trigger 2 input pin ( ch.8 to ch.11 ) ppg1_3 ppg ch.1 output pin (3) int5 int5 external interrupt input pin icu5 input capture ch.5 input pin 103 debug if g debug if pin 176 pa2 o general - purpose i/o port (3v pin) rin2 capture r2 input pin (rgb mode) vin0 capture vin0 input pin (656 mode) mb91590 series mn705-00009-3v0-e 39
chapter 1: overview 9 . explanatio n of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 40 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 177 pa3 o general - purpose i/o port (3v pin) rin3 capture r3 input pin (rgb mode) vin1 capture vin1 input pin (656 mode) 178 pa4 o general - purpose i/o port (3v pin) rin4 capture r4 input pin (rgb mode) vin2 capture vin2 input pin (656 mode) 179 pa5 o general - purpose i/o port (3v pin) rin5 capture r5 input pin (rgb mode) vin3 capture vin3 input pin (656 mode) 180 pa6 o general - purpose i/o port (3v pin) rin6 capture r6 input pin (rgb mode) vin4 capture vin4 input pin (656 mode) 181 pa7 o general - purpose i/o port (3v pin) rin7 capture r7 input pin (rgb mode) vin5 capture vin5 input pin (656 mode) 182 pb2 o general - purpose i/o port (3v pin) gin2 capture g2 input pin (rgb mode) vin6 capture vin6 input pin (656 mode) 183 pb3 o general - purpose i/o port (3v pin) gin3 capture g3 input pin (rgb mode) vin7 capture vin7 input pin (656 mode) 184 pb4 o general - purpose i/o port (3v pin) gin4 capture g4 input pin (rgb mode) 185 pb5 o general - purpose i/o port (3v pin) gin5 capture g5 input pin (rgb mode) 186 pb6 o general - purpose i/o port (3v pin) gin6 capture g6 input pin (rgb mode) 187 pb7 o general - purpose i/o port (3v pin) gin7 capture g7 input pin (rgb mode) 190 pc2 o general - purpose i/o port (3v pin) bin2 capture b2 input pin (rgb mode) 191 pc3 o general - purpose i/o port (3v pin) bin3 capture b3 input pin (rgb mode) 192 pc4 o general - purpose i/o port (3v pin) bin4 capture b4 input pin (rgb mode) mb91590 series mn705-00009-3v0-e 40
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 41 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 193 pc5 o general - purpose i/o port (3v pin) bin5 capture b5 input pin (rgb mode) 194 pc6 o general - purpose i/o port (3v pin) bin6 capture b6 input pin (rgb mode) 195 pc7 o general - purpose i/o port (3v pin) bin7 capture b7 input pin (rgb mode) 2 pd2 o general - purpose i/o port (3v pin) rout2 display digital r2 output pin 3 pd3 o general - purpose i/o port (3v pin) rout3 display digital r3 output pin 4 pd4 o general - purpose i/o port (3v pin) rout4 display digital r4 output pin 5 pd5 o general - purpose i/o port (3v pin) rout5 display digital r5 output pin 6 pd6 o general - purpose i/o port (3v pi n) rout6 display digital r6 output pin 7 pd7 o general - purpose i/o port (3v pin) rout7 display digital r7 output pin 8 pe2 o general - purpose i/o port (3v pin) gout2 display digital g2 output pin 9 pe3 o general - purpose i/o port ( 3v pin) gout3 display digital g3 output pin 10 pe4 o general - purpose i/o port (3v pin) gout4 display digital g4 output pin 11 pe5 o general - purpose i/o port (3v pin) gout5 display digital g5 output pin 12 pe6 o general - purpose i/ o port (3v pin) gout6 display digital g6 output pin 13 pe7 o general - purpose i/o port (3v pin) gout7 display digital g7 output pin 14 pf2 o general - purpose i/o port (3v pin) bout2 display digital b2 output pin 15 pf3 o general - pu rpose i/o port (3v pin) bout3 display digital b3 output pin mb91590 series mn705-00009-3v0-e 41
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 42 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 16 pf4 o general - purpose i/o port (3v pin) bout4 display digital b4 output pin 17 pf5 o general - purpose i/o port (3v pin) bout5 display digital b5 output pin 21 pf6 o general - purpose i/o port (3v pin) bout6 display digital b6 output pin 22 pf7 o general - purpose i/o port(3v pin) bout7 display digital b7 output pin 200 pg0 o general - purpose i/o port (3v pin) dckin display reference clock input p in (for external sync) cmdtrg gdc command trigger input pin 197 pg1 o general - purpose i/o port (3v pin) vsin p capture vertical sync signal input pin 198 pg2 o general - purpose i/o port (3v pin) hsin p capture horizontal sync signal input pin 199 pg3 o general - purpose i/o port (3v pin) csout display composite sync signal output pin, graphics/video switch (for external sync) output pin 23 pg4 o general - purpose i/o port (3v pin) dckout display reference clock output pin (for internal sync) 24 pg5 o general - purpose i/o port (3v pin) vsync display vertical sync signal output pin (for internal sync) , / display vertical sync signal input pin (for external sync) 25 pg6 o general - purpose i/o port (3v pin) hsync disp lay horizontal sync signal output pin (for internal sync) / display horizontal sync signal input pin (for external sync) 26 pg7 o general - purpose i/o port (3v pin) deout p display enable display period output pin 196 ph3 o general - purpose i/o por t (3v pin) cclk f or capture, capture clock input pin 204 refout t clamp level output pin 203 av r 3 s ? l ? level reference voltage for ntsc - ad 205 vin s ntsc signal input pin 111 av c c 5 ad convert e r analog power supply pin 201, 207 av c c 3 for ntsc, ad convert e r analog power supply pin 112 av r h 5 ad converter upper limit reference voltage mb91590 series mn705-00009-3v0-e 42
chapter 1: overview 9 . explanation of pin functions fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 43 pin no. pin name polarity i/o circuit types function (for switching, see ? chapter : i/o port ?) 113 av s s 5/ av r l 5 ad converter gnd/ ad converter lower limit reference voltage 202, 206 avss3 ntsc ad converter gnd pin 124 c_1 built - in regulator capacitor connected pin 1 73 c_2 built - in regulator capacitor connected pin 2 20 c _3 built - in regulator capacitor connected pin 3 126, 136,146, 156 dvcc smc high current port power supply pin 125, 135, 145, 155 dvss smc hig h current port gnd pin 89, 105, 122, 173 vcc5 +5.0v power supply pin 1, 18, 37,53, 71,175, 189 vcc3 +3.3v power supply pin 19, 36, 52, 72, 82, 88, 104, 123, 174, 188, 208 vss gnd pin mb91590 series mn705-00009-3v0-e 43
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 44 10. pins of each function this section shows the pins of eac h function. 10.1 . pins of ad c onverter 10.2 . pins of can (ch.0 to ch.2) 10.3 . pins of e xt ernal i nterrupt i nput ( ch. 0 to ch. 15) 10.4 . pins of l in - uart (ch.2 to ch.7) 10.5 . pins of mul ti - function serial interface (ch .0 , ch . 1) 10.6 . pins of ppg (ch.0 to ch.23 ) 10.7 . pin of real time clock 10.8 . pins of s tepping m otor c ontr oller ( ch. 0 to ch. 5) 10.9 . pins of output c ompare ( ch. 0 to ch. 3) 10.10 . pins of input c apture ( ch. 0 to ch. 5) 10.11 . pins of s ound g enerator ( ch. 0 to ch. 4) 10.12 . pins of free - run t imer (ch.0, ch.1) 10.13 . pins of base t imer ( ch. 0 , ch. 1) 10.14 . pins of reload t imer ( ch. 0 to ch. 3) 10.15 . pins of external bus interface (gdc e xternal m emory i/f ) 10.16 . pins of spi interface (gdc e xternal m emory i/f ) 10.17 . pins of p ort f unction (g eneral - purpose i/o) 10.18 . pins of gdc (capture rgb m ode) 10.19 . pins of gdc (captur e 656 m ode) 10.20 . pins of gdc (capture o ther) 10.21 . pins of gdc (display) 10.22 . pins of gdc ( n tsc) 10.23 . pin of gdc (other) 10.24 . pins of other mb91590 series mn705-00009-3v0-e 44
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 45 10.1. pins of ad c onverter pins of ad converter are shown. ? a/d converter external trigger input (pin name) adtg (pin no.) 157 ? adc analog 0 input (pin name) an0 (pin no.) 114 ? adc analog 1 input (pin name) an1 (pin no.) 115 ? adc an alog 2 input (pin name) an2 (pin no.) 116 ? adc analog 3 input (pin name) an3 (pin no.) 117 ? adc analog 4 input (pin name) an4 (pin no.) 118 ? adc analog 5 input (pin name) an5 (pin no.) 119 ? adc analog 6 input (pin name) an6 (pin no.) 120 ? adc analog 7 input (pin name) an7 (pin no.) 121 ? adc analog 8 input (pin name) an8 (pin no.) 127 ? adc analog 9 input (pin name) an9 (pin no.) 128 ? adc analog 10 input (pin name) an10 (pin no.) 129 ? adc analog 11 input (pin name) an11 (pin no.) 130 ? adc analog 12 input (pin name) an12 (pin no.) 131 ? adc analog 13 input (pin name) an13 (pin no.) 132 ? adc analog 14 input (pin name) an14 (pin no.) 133 ? adc analog 15 input (pin name) an15 (pin no.) 134 ? adc analog 16 input (pin name) an16 (pin no.) 137 ? adc analog 17 input (pin name) an17 (pin no.) 138 ? adc analog 18 input (pin name) an18 (pin no.) 139 ? adc analog 19 input (pin name) an19 (pin no.) 140 ? adc analog 20 input (pin name) a n20 (pin no.) 141 ? adc analog 21 input (pin name) an21 (pin no.) 142 ? adc analog 22 input (pin name) an22 (pin no.) 143 ? adc analog 23 input (pin name) an23 (pin no.) 144 ? adc analog 24 input (pin name) an24 (pin no.) 147 ? adc analog 25 input (pi n name) an25 (pin no.) 148 ? adc analog 26 input (pin name) an26 (pin no.) 149 ? adc analog 27 input (pin name) an27 (pin no.) 150 ? adc analog 28 input (pin name) an28 (pin no.) 151 ? adc analog 29 input (pin name) an29 (pin no.) 152 ? adc analog 30 inp ut (pin name) an30 (pin no.) 153 ? adc analog 31 input (pin name) an31 (pin no.) 154 ? ad converter analog power supply (pin name) avcc5 (pin no.) 111 ? ad converter upper limit reference voltage (pin name) avrh5 (pin no.) 112 ? ad converter gnd/ ad conver ter lower limit reference voltage (pin name) av s s 5 / av r l 5 (pin no.) 113 mb91590 series mn705-00009-3v0-e 45
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 46 10.2. pins of can (ch.0 to ch.2) pins of can are shown. ? can reception data 0 input (pin name) rx0 (pin no.) 107 ? can reception data 1 input (pin name) rx1 (pin no.) 102 ? can recep tion data 2 input (pin name) rx2 (pin no.) 159 ? can transmission data 0 output (pin name) tx0 (pin no.) 106 ? can transmission data 1 output (pin name) tx1 (pin no.) 101 ? can transmission data 2 output (pin name) tx2 (pin no.) 158 mb91590 series mn705-00009-3v0-e 46
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 47 10.3. pins of external i nterrupt i nput ( ch. 0 to ch. 15) pins of external interrupt input are shown. ? int0 external interrupt input (pin name) int0 (pin no .) 92 ? int1 external interrupt input (pin name) int1 (pin no .) 90 ? int2 external interrupt input (pin name) int2 (pin no .) 94 ? int3 external interrupt input (pin name) int3 (pin no .) 95 ? int4 external interrupt input (pin name) int4 (pin no .) 93 ? int5 external interrupt input (pin name) int5 (pin no .) 96 ? int6 external interrupt input (pin name) int6 (pin no .) 166 ? int7 exter nal interrupt input (pin name) int7 (pin no .) 167 ? int8 external interrupt input (pin name) int8 (pin no .) 161 ? int9 external interrupt input (pin name) int9 (pin no .) 107 ? int10 external interrupt input (pin name) int10 (pin no .) 102 ? int11 external inter rupt input (pin name) int11 (pin no .) 159 ? int12 external interrupt input (pin name) int12 (pin no . ) 98 ? int13 external interrupt input (pin name) int13 (pin no .) 99 ? int14 external interrupt input (pin name) int14 (pin no .) 100 ? int15 external interrupt input (pin name) int15 (pin no .) 160 mb91590 series mn705-00009-3v0-e 47
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 48 10.4. pins of l in- uart (ch.2 to ch.7) pins of l in - uart are shown. ? lin - uart ch . 2 clock i/o (pin name) sck2 (pin no.) 99 ? lin - uart ch . 2 clock i/o (1) (pin name) sck2_1 (pin no.) 29 ? lin - uart ch . 2 serial data output (pin na me) sot2 (pin no.) 100 ? lin - uart ch . 2 serial data output (1) (pin name) sot2_1 (pin no.) 28 ? lin - uart ch . 2 serial data input (pin name) sin2 (pin no.) 98 ? lin - uart ch . 2 serial data input (1) (pin name) sin2_1 (pin no.) 27 ? lin - uart ch . 3 clock i/o (pin nam e) sck3 (pin no.) 162 ? lin - uart ch . 3 clock i/o (1) (pin name) sck3_1 (pin no.) 32 ? lin - uart ch . 3 serial data output (pin name) sot3 (pin no.) 161 ? lin - uart ch . 3 serial data output (1) (pin name) sot3_1 (pin no.) 31 ? lin - uart ch . 3 serial data input (pin nam e) sin3 (pin no.) 160 ? lin - uart ch . 3 serial data input (1) (pin name) sin3_1 (pin no.) 30 ? lin - uart ch . 4 clock i/o (pin name) sck4 (pin no.) 165 ? lin - uart ch . 4 clock i/o (1) (pin name) sck4_1 (pin no.) 116 ? lin - uart ch . 4 serial data output (pin name) sot4 ( pin no.) 164 ? lin - uart ch . 4 serial data output (1) (pin name) sot4_1 (pin no.) 115 ? lin - uart ch . 4 serial data input (pin name) sin4 (pin no.) 163 ? lin - uart ch . 4 serial data input (1) (pin name) sin4_1 (pin no.) 114 ? lin - uart ch . 5 clock i/o (pin name) sck5 (p in no.) 168 ? lin - uart ch . 5 clock i/o (1) (pin name) sck5_1 (pin no.) 119 ? lin - uart ch . 5 serial data output (pin name) sot5 (pin no.) 167 ? lin - uart ch . 5 serial data output (1) (pin name) sot5_1 (pin no.) 118 ? lin - uart ch . 5 serial data input (pin name) sin5 (p in no.) 166 ? lin - u art ch . 5 serial data input (1) (pin name) sin5_1 (pin no.) 117 ? lin - uart ch . 6 clock i/o (pin name) sck6 (pin no.) 149 ? lin - uart ch . 6 serial data output (pin name) sot6 (pin no.) 148 ? lin - uart ch . 6 serial data input (pin name) sin6 (pin no.) 147 ? lin - uart ch . 7 clock i/o (pin name) sck7_1 (pin no.) 144 ? lin - uart ch . 7 serial data output (pin name) sot7_1 (pin no.) 143 ? lin - uart ch . 7 serial data input (pin name) sin7_1 (pin no.) 142 mb91590 series mn705-00009-3v0-e 48
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 49 10.5. pins of mul ti -function serial interface (ch.0, ch .1) pin s of mu l ti - function s erial i nterface are shown. ? mfs ch . 0 clock i/o / i 2 c ch . 0 clock i/o (pin name) sck0 (pin no.) 92 ? mfs ch . 0 serial data output / i 2 c ch . 0 serial data i/o ( pin name ) sot0 (pin no.) 91 ? mfs ch . 0 serial data input (pin name) sin0 (pin no.) 90 ? mfs ch . 1 clock i/o / i 2 c ch . 1 clock i/o (pin name) sck1 (pin no.) 95 ? mfs ch . 1 serial data output / i 2 c ch . 1 serial data i/o (pin name) sot1 (pin no.) 94 ? mfs ch . 1 serial data input (pin name) sin1 (pin no.) 93 mb91590 series mn705-00009-3v0-e 49
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 50 10.6. pins of ppg (ch.0 to ch.23) pins of ppg are shown. ? ppg ch.0 output (pin name) ppg0 (pin no.) 27 ? ppg ch.0 output (1) (pin name) ppg0_1 (pin no.) 161 ? ppg ch.0 output (2) (pin name) ppg0_2 (pin no.) 157 ? ppg ch.1 output (pin name) ppg1 (pin no.) 28 ? ppg ch.1 output (1) (pin name) ppg1_1 (pin no.) 117 ? ppg ch.1 output (2) (pin name) ppg1_2 (pin no.) 101 ? ppg ch.1 output (3) (pin name) ppg1_3 (pin no.) 96 ? ppg ch.2 output (pin name) ppg2 (pin no.) 29 ? ppg ch.2 output (1) (pin name) ppg2_1 (pin no.) 118 ? ppg ch.2 output (2) ( pin name) ppg2_2 (pin no.) 102 ? ppg ch.3 output (pin name) ppg3 (pin no.) 30 ? ppg ch.3 output (1) (pin name) ppg3_1 (pin no.) 119 ? ppg ch.3 output (2) (pin name) ppg3_2 (pin no.) 158 ? ppg ch.4 output (pin name) ppg4 (pin no.) 31 ? ppg ch.4 output (1) (pin name) ppg4_1 (pin no.) 120 ? ppg ch.4 output (2) (pin name) ppg4_2 (pin no.) 159 ? ppg ch.5 output (pin name) ppg5 (pin no.) 32 ? ppg ch.5 output (1) (pin name) ppg5_1 (pin no.) 121 ? ppg ch.5 output (2) (pin name) ppg5_2 (pin no.) 166 ? ppg ch.6 o utput (pin name) ppg6 (pin no.) 33 ? ppg ch.6 output (1) (pin name) ppg6_1 (pin no.) 98 ? ppg ch.6 output (2) (pin name) ppg6_2 (pin no.) 167 ? ppg ch.7 output (pin name) ppg7 (pin no.) 34 ? ppg ch.7 output (1) (pin name) ppg7_1 (pin no.) 99 ? ppg ch .7 output (2) (pin name) ppg7_2 (pin no.) 168 ? ppg ch.8 output (pin name) ppg8 (pin no.) 114 ? ppg ch.8 output (1) (pin name) ppg8_1 (pin no.) 100 ? ppg ch.8 output (2) (pin name) ppg8_2 (pin no.) 108 ? ppg ch.9 output (pin name) ppg9 (pin no.) 115 ? ppg ch.9 output (1) (pin name) ppg9_1 (pin no.) 160 ? ppg ch.9 output (2) (pin name) ppg9_2 (pin no.) 109 ? ppg ch.10 output (pin name) ppg10 (pin no.) 116 ? ppg ch.10 output (1) (pin name) ppg10_1 (pin no.) 106 ? ppg ch.10 output (2) (pin name) ppg10_2 ( pin no.) 110 ? ppg ch.11 output (1) (pin name) ppg11_1 (pin no.) 95 ? ppg ch.12 output (1) (pin name) ppg12_1 (pin no.)141 ? ppg ch.13 output (1) (pin name) ppg13_1 (pin no.)142 ? ppg ch.14 output (1) (pin name) ppg14_1 (pin no.)143 ? ppg ch.15 output (1) ( pin name) ppg15_1 (pin no.)144 ? ppg ch.16 output (pin name) ppg16 (pin no.)147 ? ppg ch.17 output (pin name) ppg17 (pin no.)148 ? ppg ch.18 output (pin name) ppg18 (pin no.)149 ? ppg ch.19 output (pin name) ppg19 (pin no.)150 ? ppg ch.20 output ( pin name) ppg20 (pin no.)151 ? ppg ch.21 output (pin name) ppg21 (pin no.)152 ? ppg ch.22 output (pin name) ppg22 (pin no.)153 ? ppg ch.23 output (pin name) ppg23 (pin no.)154 ? ppg trigger 0 input ( ch.0 to ch.3) (pin name) trg0 (pin no.) 90 ? ppg tr igger 1 input ( ch.4 to ch.7) (pin name) trg1 (pin no.) 93 ? ppg trigger 2 input ( ch.8 to ch.11 ) (pin name) trg2 (pin no.) 96 ? ppg trigger 3 input ( ch.12 to ch.15) (pin name) trg3 (pin no.)162 mb91590 series mn705-00009-3v0-e 50
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 51 ? ppg trigger 4 input ( ch . 16 to ch . 19) (pin name) trg4 (pin no.)165 ? ppg trigger 5 input ( ch . 20 to ch . 23) (pin name) trg5 (pin no.) 95 mb91590 series mn705-00009-3v0-e 51
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 52 10.7. pin of real time clock pin of real time clock is shown. ? rtc overflow output ( pin name ) wot ( pin n o. ) 16 1 mb91590 series mn705-00009-3v0-e 52
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 53 10.8. pins of s tepping m otor c ontroller ( ch. 0 to ch. 5) pins of stepping motor con troller are shown. ? smc ch .0 output (pin name) pwm1m0 (pin no.) 128 ? smc ch .0 output (pin name) pwm1p0 (pin no.) 127 ? smc ch .0 output (pin name) pwm2m0 (pin no.) 130 ? smc ch .0 output (pin name) pwm2p0 (pin no.) 129 ? smc ch .1 output (pin name) pwm 1m1 (pin no.) 132 ? smc ch .1 output (pin name) pwm1p1 (pin no.) 131 ? smc ch .1 output (pin name) pwm2m1 (pin no.) 134 ? smc ch .1 output (pin name) pwm2p1 (pin no.) 133 ? smc ch .2 output (pin name) pwm1m2 (pin no.) 138 ? smc ch .2 output (pin name) pwm1 p2 (pin no.) 137 ? smc ch .2 output (pin name) pwm2m2 (pin no.) 140 ? smc ch .2 output (pin name) pwm2p2 (pin no.) 139 ? smc ch .3 output (pin name) pwm1m3 (pin no.) 142 ? smc ch .3 output (pin name) pwm1p3 (pin no.) 141 ? smc ch .3 output (pin name) pwm2m 3 (pin no.) 144 ? smc ch .3 output (pin name) pwm2p3 (pin no.) 143 ? smc ch .4 output (pin name) pwm1m4 (pin no.) 148 ? smc ch .4 output (pin name) pwm1p4 (pin no.) 147 ? smc ch . 4 output (pin name) pwm2m4 (pin no.) 150 ? smc ch . 4 output (pin name) pwm2p4 (pin no.) 149 ? smc ch . 5 output (pin name) pwm1m5 (pin no.) 152 ? smc ch . 5 output (pin name) pwm1p5 (pin no.) 151 ? smc ch . 5 output (pin name) pwm2m5 (pin no.) 154 ? smc ch . 5 output (pin name) pwm2p5 (pin no.) 153 ? smc high current port gnd (pin name) dvss (pin no.) 125,135,145,155 ? smc hi gh c urrent port power supply (pin name) dvcc (pin no.) 126,136,146,156 mb91590 series mn705-00009-3v0-e 53
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 54 10.9. pins of output c ompare ( ch. 0 to ch. 3) pins of o utput compare are shown. ? output compare ch . 0 output (pin name) ocu0 (pin no.) 168 ? output compare ch . 1 output (pin name) ocu1 (pin no.) 108 ? output compare ch . 2 output (pin name) ocu2 (pin no.) 109 ? output compare ch . 3 output (pin name) ocu3 (pin no.) 110 mb91590 series mn705-00009-3v0-e 54
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 55 10.10. pins of input c apture ( ch. 0 to ch. 5) pins of i nput capture are shown. ? input capture ch . 0 input (pin name) icu0 (pin no.) 110 ? input capture ch . 0 input (1) (pin name) icu0_1 (pin no.) 99 ? input capture ch . 0 input (2) (pin name) icu0_2 (pin no.) 150 ? input capture ch . 1 input (pin name) icu1 (pin no.) 92 ? input capture ch . 1 input (1) (pin name) icu1_1 (pin no.) 160 ? input capture ch . 1 input (2) (pin name) icu1_2 (pin no.) 151 ? input capture ch . 2 input (pin name) icu2 (pin no.) 93 ? input capture ch . 2 input (1) (pin name) icu2_1 (pin no.) 98 ? input capture ch . 2 input (2) (pin name) icu2_2 (pin no.) 152 ? input capture ch . 3 input (pin name) icu3 (pin no.) 94 ? input capture ch . 3 input (1) (pin name) icu3_1 (pin no.) 100 ? input capture ch . 3 input (2) (pin name) icu3_2 (pin no.) 153 ? input capture ch . 4 input (pin name) icu4 (pin no.) 95 ? input capture ch . 4 input (1) (pin name) icu4_1 (pin no.) 161 ? input capture ch . 4 input (2) (pin name) icu4_2 (pin no.) 154 ? input capture ch . 5 input (pin name) icu5 (pin no.) 96 ? input capture ch . 5 input (1) (pin name) icu5_1 (pin no.) 162 ? in put capture ch . 5 input (2) (pin name) icu5_2 (pin no.) 109 mb91590 series mn705-00009-3v0-e 55
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 56 10.11. pins of s ound g enerator ( ch. 0 to ch. 4) pins of sound generator are shown. ? sound generator ch . 0 sga output (pin name) sga0 (pin no.) 98 ? sound generator ch . 0 sgo output (pin name) sgo0 (pin no. ) 99 ? sound generator ch . 1 sga output (pin name) sga1 (pin no.) 100 ? sound generator ch . 1 sgo output (pin name) sgo1 (pin no.) 160 ? sound generator ch . 2 sga output (pin name) sga2 (pin no.) 162 ? sound generator ch . 2 sgo output (pin name) sgo2 (pin no.) 163 ? sound generator ch . 3 sga output (pin name) sga3 (pin no.) 164 ? sound generator ch . 3 sgo output (pin name) sgo3 (pin no.) 165 ? sound generator ch . 4 sga output (pin name) sga4_1 (pin no.) 120 ? sound generator ch . 4 sgo output (pin name) sgo4_1 (pin no.) 121 mb91590 series mn705-00009-3v0-e 56
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 57 10.12. pins of free - run timer (ch.0, ch.1) pins of f ree - run timer are shown. ? free - run timer 0 clock input (pin name) frck0 (pin no.) 167 ? free - run timer 1 clock input (pin name) frck1 (pin no.) 166 mb91590 series mn705-00009-3v0-e 57
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 58 10.13. pins of base t imer ( ch. 0, ch. 1) pins of b ase timer are shown. ? base timer tioa0 output (pin name) tioa0 (pin no.) 92 ? base timer tiob0 input (pin name) tiob0 (pin no.) 94 ? base timer tioa1 output / input (pin name) tioa1 (pin no.) 93 ? base timer tiob1 input (pin name) tiob1 (pin no.) 95 mb91590 series mn705-00009-3v0-e 58
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 59 10.14. pins of reload timer ( ch. 0 to ch. 3) pins of r eload timer are shown. ? reload timer ch . 0 event input (pin name) tin0 (pin no.) 161 ? reload timer ch . 0 event input (1) (pin name) tin0_1 (pin no.) 114 ? reload timer ch . 0 event input (2) (pin name) tin0_2 (pin no.) 27 ? reload timer ch . 0 output (pin name) tot0 (pin no.) 165 ? reload timer ch . 0 output (1) (pin name) tot0_1 (pin no.) 118 ? reload timer ch . 0 output (2) (pin name) tot0_2 (pin no.) 31 ? reload timer ch . 1 event input (pin name) tin1 (pin no.) 162 ? reload timer ch . 1 event input (1) (pin name) tin1_1 (pin no.) 115 ? reload timer ch . 1 event input (2) (pin name) tin1_2 (pin no.) 28 ? reload timer ch . 1 output (pin name) tot1 (pin no.) 166 ? reload timer ch . 1 output (1) (pin name) tot1_1 (pin no.) 119 ? reload timer ch . 1 output (2) (pin name) tot1_2 (pin no.) 32 ? reload timer ch . 2 event input (pin name) tin2 (pin no.) 163 ? reload timer ch . 2 event input (1) (pin name) tin2_1 (pin no.) 116 ? reload timer ch . 2 event input (2) (pin name) tin2_2 (pin no.) 29 ? reload timer ch . 2 output (pin name) tot2 (pin no.) 167 ? reload timer ch . 2 output (1) (pin name) tot2_1 (pin no.) 98 ? reload timer ch . 2 output (2) (pin name) tot2_2 (pin no.) 33 ? reload timer ch . 3 event input (pin name) tin3 (pin no.) 164 ? reload timer ch . 3 event inp ut (1) (pin name) tin3_1 (pin no.) 117 ? reload timer ch . 3 event input (2) (pin name) tin3_2 (pin no.) 30 ? reload timer ch . 3 output (pin name) tot3 (pin no.) 168 ? reload timer ch . 3 output (1) (pin name) tot3_1 (pin no.) 99 ? reload timer ch . 3 output (2) (pin name) tot3_2 (pin no.) 34 mb91590 series mn705-00009-3v0-e 59
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 60 10.15. pins of external bus interface (gdc external m emory i/f) pins of external bus interface (gdc external memory i/f ) are shown. ? external bus/wait input (pin name) rdy (pin no.) 81 ? external bus/address bit0 output (pi n name) a00 (pin no.) 51 ? external bus/address bit1 output (pin name) a01 (pin no.) 54 ? external bus/address bit2 output (pin name) a02 (pin no.) 55 ? external bus/address bit3 output (pin name) a03 (pin no.) 56 ? external bus/address bit4 output (pin name) a04 (pin no.) 57 ? external bus/address bit5 output (pin name) a05 (pin no.) 58 ? external bus/address bit6 output (pin name) a06 (pin no.) 59 ? external bus/address bit7 output (pin name) a07 (pin no.) 60 ? external bus/address bit8 output (pin name) a08 (pin no.) 61 ? external bus/address bit9 output (pin name) a09 (pin no.) 62 ? external bus/address bit10 output (pin name) a10 (pin no.) 63 ? external bus/address bit11 output (pin name) a11 (pin no.) 64 ? external bus/address bit12 o utput (pin name) a12 (pin no.) 65 ? external bus/address bit13 output (pin name) a13 (pin no.) 66 ? external bus/address bit14 output (pin name) a14 (pin no.) 67 ? external bus/address bit15 output (pin name) a15 (pin no.) 68 ? external bus/address bit16 output (pin name) a16 (pin no.) 69 ? external bus/address bit17 output (pin name) a17 (pin no.) 70 ? external bus/address bit18 output (pin name) a18 (pin no.) 74 ? external bus/address bit19 output (pin name) a19 (pin no.) 75 ? external bus/address bit20 output (pin name) a20 (pin no.) 76 ? external bus/address bit21 output (pin name) a21 (pin no.) 77 ? external bus/address bit22 output (pin name) a22 (pin no.) 78 ? external bus/address bit23 output (pin name) a23 (pin no.) 79 ? external bus/address bit24 output (pin name) a24 (pin no.) 80 ? external bus / write enable output (pin name) wex (pin no.) 45 ? external bus / r ead enable output (pin name) rex (pin no.) 48 ? external bus / chip select 0 output (pin name) cs0x (pin no.) 46 ? external bus / chip select 1 output (pin name) cs1x (pin no.) 47 ? external bus / data bit 0 i/o (pin name) d0 (pin no.) 27 ? external bus / data bit 1 i/o (pin name) d1 (pin no.) 28 ? external bus / data bit 2 i/o (pin name) d2 (pin no.) 29 ? external bus / data bit 3 i/o (pin name) d3 (pin no.) 30 ? external bus / data bit 4 i/o (pin name) d4 (pin no.) 31 ? external bus / data bit 5 i/o (pin name) d5 (pin no.) 32 ? external bus / data bit 6 i/o (pin name) d6 (pin no.) 33 ? external bus / data bit 7 i/o (pin name) d7 (pin no. ) 34 ? external bus / data bit 8 i/o (pin name) d8 (pin no.) 35 ? external bus / data bit 9 i/o (pin name) d9 (pin no.) 38 ? external bus / data bit10 i/o (pin name) d10 (pin no.) 39 ? external bus / data bit11 i/o (pin name) d11 (pin no.) 40 ? external bus / data bit12 i/o (pin name) d12 (pin no.) 41 ? external bus / data bit13 i/o (pin name) d13 (pin no.) 42 ? external bus / data bit14 i/o (pin name) d14 (pin no.) 43 ? external bus / data bit15 i/o (pin name) d15 (pin no.) 44 mb91590 series mn705-00009-3v0-e 60
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 61 10.16. pins of spi interface (gdc external m emory i/f) pins of spi i nterface (gdc external memory i/f ) are shown. ? spi data output (pin name) spi_do (pin no.) 77 ? spi data input (pin name) spi_di (pin no.) 78 ? spi clock output (pin name) spi_sck (pin no.) 79 ? spi chip select output (pin name) spi_xcs (pin no.) 80 mb91590 series mn705-00009-3v0-e 61
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 62 10.17. pins of p ort f unction (general- purpose i/o) pins of port function (general - purpose i/o) are shown. ? general - purpose i/o port (3v pin) (pin name) p000 (pin no.) 27 ? general - purpose i/o port (3v pin) (pin name) p001 (pin no.) 28 ? general - purpose i/o port (3v pin) (pin name) p002 (pin no.) 29 ? general - purpose i/o port (3v pin) (pin name) p003 (pin no.) 30 ? general - purpose i/o port (3v pin) (pin name) p004 (pin no.) 31 ? general - purpose i/o port (3v pin) (pin name) p005 (pin no.) 32 ? general - purpose i/o port (3v pin) (pin name) p006 (pin no.) 33 ? general - purpose i/o port (3v pin) (pin name) p007 (pin no.) 34 ? general - purpose i/o port (3v pin) (pin name) p010 (pin no.) 35 ? general - purpose i/o port (3v pin) (pin na me) p011 (pin no.) 38 ? general - purpose i/o port (3v pin) (pin name) p012 (pin no.) 39 ? general - purpose i/o port (3v pin) (pin name) p013 (pin no.) 40 ? general - purpose i/o port (3v pin) (pin name) p014 (pin no.) 41 ? general - purpose i/o port (3v pin) (pin name) p015 (pin no.) 42 ? general - purpose i/o port (3v pin) (pin name) p016 (pin no.) 43 ? general - purpose i/o port (3v pin) (pin name) p017 (pin no.) 44 ? general - purpose i/o port (3v pin) (pin name) p020 (pin no.) 45 ? general - purpose i/o port (3v pin) (pin name) p021 (pin no.) 46 ? general - purpose i/o port (3v pin) (pin name) p022 (pin no.) 47 ? general - purpose i/o port (3v pin) (pin name) p023 (pin no.) 48 ? general - purpose i/o port (3v pin) (pin name) p024 (pin no.) 49 ? general - purpose i/o port (3v pin) (pin name) p025 (pin no.) 50 ? general - purpose i/o port (3v pin) (pin name) p026 (pin no.) 51 ? general - purpose i/o port (3v pin) (pin name) p027 (pin no.) 54 ? general - pu rpose i/o port (3v pin) (pin name) p030 (pin no.) 55 ? general -p urpose i/o port (3v pin) (pin name) p031 (pin no.) 56 ? general - purpose i/o port (3v pin) (pin name) p032 (pin no.) 57 ? general - purpose i/o port (3v pin) (pin name) p033 (pin no.) 58 ? general - purpose i/o port (3v pin) (pin name) p034 (pin no.) 59 ? g eneral - purpose i/o port (3v pin) (pin name) p035 (pin no.) 60 ? general - purpose i/o port (3v pin) (pin name) p036 (pin no.) 61 ? general - purpose i/o port (3v pin) (pin name) p037 (pin no.) 62 ? general - purpose i/o port (3v pin) (pin name) p040 (pin n o.) 63 ? general - purpose i/o port (3v pin) (pin name) p041 (pin no.) 64 ? general - purpose i/o port (3v pin) (pin name) p042 (pin no.) 65 ? general - purpose i/o port (3v pin) (pin name) p043 (pin no.) 66 ? general - purpose i/o port (3v pin) (pin name) p044 (pin no.) 67 ? general - purpose i/o port (3v pin) (pin name) p045 (pin no.) 68 ? general - purpose i/o port (3v pin) (pin name) p046 (pin no.) 69 ? general - purpose i/o port (3v pin) (pin name) p047 (pin no.) 70 ? general - purpose i/o port (3v pin) (pin nam e) p050 (pin no.) 74 ? general - purpose i/o port (3v pin) (pin name) p051 (pin no.) 75 ? general - purpose i/o port (3v pin) (pin name) p052 (pin no.) 76 ? general - purpose i/o port (3v pin) (pin name) p053 (pin no.) 77 ? general - purpose i/o port (3v pin) (pin name) p054 (pin no.) 78 ? general - purpose i/o port (3v pin) (pin name) p055 (pin no.) 79 ? general - purpose i/o port (3v pin) (pin name) p056 (pin no.) 80 ? general - purpose i/o port (3v pin) (pin name) p057 (pin no.) 81 ? general - pu rpose i/o port (pin name) p060 (pin no.) 127 ? general - purpose i/o port (pin name) p061 (pin no.) 128 ? general - purpose i/o port (pin name) p062 (pin no.) 129 mb91590 series mn705-00009-3v0-e 62
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 63 ? general - purpose i/o port (pin name) p063 (pin no.) 130 ? general - purpose i/o port (pin name) p064 (p in no.) 131 ? general - purpose i/o port (pin name) p065 (pin no.) 132 ? general - purpose i/o port (pin name) p066 (pin no.) 133 ? general - purpose i/o port (pin name) p067 (pin no.) 134 ? general - purpose i/o port (pin name) p070 (pin no.) 137 ? general - purpose i/o port (pin name) p071 (pin no.) 138 ? general - purpose i/o port (pin name) p072 (pin no.) 139 ? general - purpose i/o port (pin name) p073 (pin no.) 140 ? general - purpose i/o port (pin name) p074 (pin no.) 141 ? general - purpose i/o port ( pin name) p075 (pin no.) 142 ? general - purpose i/o port (pin name) p076 (pin no.) 143 ? general - purpose i/o port (pin name) p077 (pin no.) 144 ? general - purpose i/o port (pin name) p080 (pin no.) 147 ? general - purpose i/o port (pin name) p081 (pi n no.) 148 ? general - purpose i/o port (pin name) p082 (pin no.) 149 ? general - purpose i/o port (pin name) p083 (pin no.) 150 ? general - purpose i/o port (pin name) p084 (pin no.) 151 ? general - purpose i/o port (pin name) p085 (pin no.) 152 ? general -p urpose i/o port (pin name) p086 (pin no.) 153 ? general - purpose i/o port (pin name) p087 (pin no.) 154 ? general - purpose i/o port (pin name) p090 (pin no.) 157 ? general - purpose i/o port (pin name) p091 (pin no.) 98 ? general - purpose i/o port (pi n name) p092 (pin no.) 99 ? general - purpose i/o port (pin name) p093 (pin no.) 100 ? general - p u rpose i/o port (pin name) p094 (pin no.) 160 ? general - purpose i/o port (pin name) p095 (pin no.) 106 ? general - purpose i/o port (pin name) p096 (pin n o.) 107 ? general - purpose i/o port (pin name) p097 (pin no.) 161 ? general - purpose i/o port (pin name) p100 (pin no.) 114 ? general - purpose i/o port (pin name) p101 (pin no.) 115 ? general - purpose i/o port (pin name) p102 (pin no.) 116 ? general - purp ose i/o port (pin name) p103 (pin no.) 117 ? general - purpose i/o port (pin name) p104 (pin no.) 118 ? general - purpose i/o port (pin name) p105 (pin no.) 119 ? general - purpose i/o port (pin name) p106 (pin no.) 120 ? general - purpose i/o port (pin name) p107 (pin no.) 121 ? general - purpose i/o port (pin name) p110 (pin no.) 101 ? general - purpose i/o port (pin name) p111 (pin no.) 102 ? general - purpose i/o port (pin name) p112 (pin no.) 158 ? general - purpose i/o port (pin name) p113 (pin no .) 159 ? general - purpose i/o port (pin name) p114 (pin no.) 162 ? general - purpose i/o port (pin name) p115 (pin no.) 163 ? general - purpose i/o port (pin name) p116 (pin no.) 164 ? general - purpose i/o port (pin name) p117 (pin no.) 165 ? general - purpo se i/o port (pin name) p120 (pin no.) 166 ? general - purpose i/o port (pin name) p121 (pin no.) 167 ? general - purpose i/o port (pin name) p122 (pin no.) 168 ? general - purpose i/o port (pin name) p123 (pin no.) 108 ? general - purpose i/o port (pin n ame) p124 (pin no.) 109 ? general - p u rpose i/o port (pin name) p125 (pin no.) 110 ? general - purpose i/o port (pin name) p126 (pin no.) 90 ? general - purpose i/o port (pin name) p127 (pin no.) 91 ? general - purpose i/o port (pin name) p130 (pin no.) 92 ? general - purpose i/o port (pin name) p131 (pin no.) 93 ? general - purpose i/o port (pin name) p132 (pin no.) 94 ? general - purpose i/o port (pin name) p133 (pin no.) 95 ? general - purpose i/o port (pin name) p134 (pin no.) 96 mb91590 series mn705-00009-3v0-e 63
chapter 1: overview 1 0 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 64 ? general - purpose i/o p ort (single clock product) (pin name) p136 (pin no.) 172 ? general - purpose i/o port(single clock product) (pin name) p137 (pin no.) 171 ? general - purpose i/o port (3v pin) (pin name) pa2 (pin no.) 176 ? general - purpose i/o port (3v pin) (pin name) pa3 ( pin no.) 177 ? general - purpose i/o port (3v pin) (pin name) pa4 (pin no.) 178 ? general - purpose i/o port (3v pin) (pin name) pa5 (pin no.) 179 ? general - purpose i/o port (3v pin) (pin name) pa6 (pin no.) 180 ? general - purpose i/o port (3v pin) (pin name) pa7 (pin no.) 181 ? general - purpose i/o port (3v pin) (pin name) pb2 (pin no.) 182 ? general - purpose i/o port (3v pin) (pin name) pb3 (pin no.) 183 ? general - purpose i/o port (3v pin) (pin name) pb4 (pin no.) 184 ? general - purpose i/o port (3v pin) (p in name) pb5 (pin no.) 185 ? general - purpose i/o port (3v pin) (pin name) pb6 (pin no.) 186 ? general - purpose i/o port (3v pin) (pin name) pb7 (pin no.) 187 ? general - purpose i/o port (3v pin) (pin name) pc2 (pin no.) 190 ? general - purpose i/o port (3v pin) (pin name) pc3 (pin no.) 191 ? general - purpose i/o port (3v pin) (pin name) pc4 (pin no.) 192 ? general - purpose i/o port (3v pin) (pin name) pc5 (pin no.) 193 ? general - purpose i/o port (3v pin) (pin name) pc6 (pin no.) 194 ? general - purpose i/o p ort (3v pin) (pin name) pc7 (pin no.) 195 ? general - purpose i/o port (3v pin) (pin name) pd2 (pin no.) 2 ? general - purpose i/o port (3v pin) (pin name) pd3 (pin no.) 3 ? general - purpose i/o port (3v pin) (pin name) pd4 (pin no.) 4 ? general - purpose i/o port (3v pin) (pin name) pd5 (pin no.) 5 ? general - purpose i/o port (3v pin) (pin name) pd6 (pin no.) 6 ? general - p u rpose i/o port (3v pin) (pin name) pd7 (pin no.) 7 ? general - purpose i/o port (3v pin) (pin name) pe2 (pin no.) 8 ? general - purpose i/o port (3v pin) (pin name) pe3 (pin no.) 9 ? general - purpose i/o port (3v pin) (pin name) pe4 (pin no.) 10 ? general - purpose i/o port (3v pin) (pin name) pe5 (pin no.) 11 ? general - purpose i/o port (3v pin) (pin name) pe6 (pin no.) 12 ? general - purpose i/o port (3v pin) (pin name) pe7 (pin no.) 13 ? general - purpose i/o port (3v pin) (pin name) pf2 (pin no.) 14 ? general - purpose i/o port (3v pin) (pin name) pf3 (pin no.) 15 ? general - purpose i/o port (3v pin) (pin name) pf4 (pin no.) 16 ? general - purp ose i/o port (3v pin) (pin name) pf5 (pin no.) 17 ? general - purpose i/o port (3v pin) (pin name) pf6 (pin no.) 21 ? general - purpose i/o port (3v pin) (pin name) pf7 (pin no.) 22 ? general - purpose i/o port (3v pin) (pin name) pg0 (pin no.) 200 ? general - purpose i/o port (3v pin) (pin name) pg1 (pin no.) 197 ? general - purpose i/o port (3v pin) (pin name) pg2 (pin no.) 198 ? general - purpose i/o port (3v pin) (pin name) pg3 (pin no.) 199 ? general - purpose i/o port (3v pin) (pin name) pg4 (pin no.) 23 ? general - purpose i/o port (3v pin) (pin name) pg5 (pin no.) 24 ? general - purpose i/o port (3v pin) (pin name) pg6 (pin no.) 25 ? general - purpose i/o port (3v pin) (pin name) pg7 (pin no.) 26 ? general - purpose i/o port (3v pin) (pin name) ph3 (pin no.) 196 note : p135 is a missing number. mb91590 series mn705-00009-3v0-e 64
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 65 10.18. pins of gdc (capture rgb m ode) pins of gdc (capture rgb mode) are shown. ? capture r2 input (rgb mode) (pin name) rin2 (pin no.) 176 ? capture r3 input (rgb mode) (pin name) rin3 (pin no.) 177 ? capture r4 input (rg b mode) (pin name) rin4 (pin no.) 178 ? capture r5 input (rgb mode) (pin name) rin5 (pin no.) 179 ? capture r6 input (rgb mode) (pin name) rin6 (pin no.) 180 ? capture r7 input (rgb mode) (pin name) rin7 (pin no.) 181 ? capture g2 input (rgb mode) (pin name) gin2 (pin no.) 182 ? capture g3 input (rgb mode) (pin name) gin3 (pin no.) 183 ? capture g4 input (rgb mode) (pin name) gin4 (pin no.) 184 ? capture g5 input (rgb mode) (pin name) gin5 (pin no.) 185 ? capture g6 input (rgb mode) (pin n ame) gin6 (pin no.) 186 ? capture g7 input (rgb mode) (pin name) gin7 (pin no.) 187 ? capture b2 input (rgb mode) (pin name) bin2 (pin no.) 190 ? capture b3 input (rgb mode) (pin name) bin3 (pin no.) 191 ? capture b4 input (rgb mode) (pin name) bin 4 (pin no.) 192 ? capture b5 input (rgb mode) (pin name) bin5 (pin no.) 193 ? capture b6 input (rgb mode) (pin name) bin6 (pin no.) 194 ? capture b7 input (rgb mode) (pin name) bin7 (pin no.) 195 mb91590 series mn705-00009-3v0-e 65
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 66 10.19. pins of gdc (capture 656 m ode) pins of gdc (capture 656 mode) are shown. ? capture vin0 input (656 mode) (pin name) vin0 (pin no.) 176 ? capture vin1 input (656 mode) (pin name) vin1 (pin no.) 177 ? capture vin2 input (656 mode) (pin name) vin2 (pin no.) 178 ? capture vin3 input (656 mode) (pin name) vin3 (pin no.) 179 ? capture vin4 input (656 mode) (pin name) vin4 (pin no.) 180 ? capture vin5 input (656 mode) (pin name) vin5 (pin no.) 181 ? capture vin6 input (656 mode) (pin name) vin6 (pin no.) 182 ? capture vin7 input (656 mode) (pin name) vin7 (pin no.) 183 mb91590 series mn705-00009-3v0-e 66
chapter 1: overview 10 . pin s of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 67 10.20. pins of gdc (capture o ther) pins of gdc (capture other) are shown. ? capture vertical sync signal input (pin name) vsin (pin no.) 197 ? capture horizontal sync signal input (pin name) hsin (pin no.) 198 ? capture capture clock inp ut (pin name) cclk (pin no.) 196 mb91590 series mn705-00009-3v0-e 67
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 68 10.21. pins of gdc (display) pins of gdc (display) are shown. ? display digital r0 output (pin name) rout0 (pin no.) 38 ? display digital r1 output (pin name) rout1 (pin no.) 39 ? display digital r2 output (pin name) r out2 (pin no.) 2 ? display digital r3 output (pin name) rout3 (pin no.) 3 ? display digital r4 output (pin name) rout4 (pin no.) 4 ? display digital r5 output (pin name) rout5 (pin no.) 5 ? display digital r6 output (pin name) rout6 (pin no.) 6 ? display digital r7 output (pin name) rout7 (pin no.) 7 ? display digital g0 output (pin name) gout0 (pin no.) 40 ? display digital g1 output (pin name) gout1 (pin no.) 41 ? display digital g2 output (pin name) gout2 (pin no.) 8 ? display digital g3 output (pin name) gout3 (pin no.) 9 ? display digital g4 output (pin name) gout4 (pin no.) 10 ? display digital g5 output (pin name) gout5 (pin no.) 11 ? display digital g6 output (pin name) gout6 (pin no.) 12 ? display digital g7 output (pin name) gout7 (pin no.) 13 ? display digital b0 output (pin name) bout0 (pin no.) 42 ? display digital b1 output (pin name) bout1 (pin no.) 43 ? display digital b2 output (pin name) bout2 (pin no.) 14 ? display digital b3 output (pin name) bout3 (pin no.) 15 ? display digital b4 output (pin name) bout4 (pin no.) 16 ? display digital b5 output (pin name) bout5 (pin no.) 17 ? display digital b6 output (pin name) bout6 (pin no.) 21 ? display digital b7 output (pin name) bout7 (pi n no.) 22 ? display enable display period output (pin name) deout (pin no.) 26 ? display composite sync signal output , / graphics/video switch (external sync) output (pin name) csout (pin no.)199 ? display reference clock output (internal sync) (pin name) d ckout (pin no.) 23 ? display vertical sync signal output (internal sync) / display vertical sync signal input (external sync) (pin name) vsync (pin no.) 24 ? display horizontal sync signal output (internal sync) / display horizontal sync signal input (external sync) (pin name) hsync (pin no.) 25 ? display reference clock input (external sync) (pin name) dckin (pin no.)200 mb91590 series mn705-00009-3v0-e 68
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 69 10.22. pins of gdc (ntsc) pins of gdc (ntsc) are shown. ? clamp level output (pin name) refout (pin no.) 204 ? ?l? level reference voltage f or ntsc - ad (pin name) avr3 (pin no.) 203 ? ntsc signal input (pin name) vin (pin no.) 205 ? f or ntsc, ad converter analog power supply (pin name) avcc3 (pin no.) 201, 207 ? ntsc ad converter gnd (pin name) avss3 (pin no.) 20 2, 206 mb91590 series mn705-00009-3v0-e 69
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 70 10.23. pin of gdc (o ther) pin of gdc ( other ) is shown. ? gdc command trigger input (pin name) cmdtrg (pin no.) 20 0 mb91590 series mn705-00009-3v0-e 70
chapter 1: overview 10 . pins of each function fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 71 10.24. pins of other pins of o ther such as power supply and gnd are shown. ? +5.0v power supply (pin name) vcc5 (pin no.) 89,105,122,173 ? +3.3v power supply (pin name) vcc3 (pin no.) 1,18,37,53,71, 175,189 ? gnd (pin name) vss (pin no.) 19,36,52,72,82,88, 104,123,174,188,208,170 ? built - in regulator capacitor connected pin 1 (pin name) c_1 (pin no.) 124 ? built - in regulator capacitor connec ted pin 2 (pin name) c_2 (pin no.) 73 ? built - in regulator capacitor connected pin 3 (pin name) c_3 (pin no.) 20 ? main clock oscillator output (pin name) x1 (pin no.) 83 ? main clock oscillator input (pin name) x0 (pin no.) 84 ? sub - clock oscil lator output (dual clock product) (pin name) x1a (pin no.) 172 ? sub - clock oscillator input (dual clock product) (pin name) x0a (pin no.) 1 71 ? mode pin 0 (pin name) md0 (pin no.) 86 ? mode pin 1 (pin name) md1 (pin no.) 85 ? mode pin 2 (pi n name) md2 (pin no.) 169 ? nmi interrupt input (pin name) nmix (pin no.) 97 ? debug i/f (pin name) debug if (pin no.) 103 ? external reset input (pin name) rstx (pin no.) 87 mb91590 series mn705-00009-3v0-e 71
chapter 1: overview 11 . i/o circuit types fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 72 11. i/o circuit types this section shows i/o c ircuit t ypes of mb91590 se ries . type circuit remarks a ? general - purpose i/o port ? output 1 ma, 2ma ? pull - up resistor control 50 k ? pull - down resistor control 50 k ? cmos input ? schmitt input ? ttl input ? automotive input c ? analog i/o , general - purpose i/o port ? output 1 ma, 2ma ? pull - up resistor control 50 k ? pull - down resistor control 50 k ? cmo s input ? schmitt input ? ttl input ? automotive input pull - up control degital output degital output pull - down control standby control standby control standby control ttl input standby control automotive input cmos input cmos - hys input pull - up control degital output degital output pull - down control standby control standby control standby control ttl input standby control automotive input cmos input analog input cmos - hys input mb91590 series mn705-00009-3v0-e 72
chapter 1: overview 11 . i/o circuit types fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 73 type circuit remarks e ? analog input , general - purpose i/o port ? output 1ma, 2ma, 30ma ( high current for smc) ? pull - up resistor control 50 k ? pull - down resistor control 50 k ? cmos input ? schmitt input ? ttl input ? automotive input f 1 ? schmitt input ? pull - up resistor control 50 k (5v cont) f 2 ? schmitt input ? pull - down resistor control 50 k (5v cont) g ? open - drain i/o ? output 25ma (nod) ? ttl input pull - up control degital output degital output pull - down control stnadby control stnadby control stnadby control ttl input stnadby control automotive input cmos input analog input cmos - hys input cmos - hys input cmos - hys input ttl input mb91590 series mn705-00009-3v0-e 73
chapter 1: overview 11 . i/o circuit types fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 74 type circuit remarks j ? automotive input k ? analog input, general - purpose i/o port ? output 1 ma, 2ma, 3ma(i 2 c) ? pull - up resistor control 50 k ? pull - down resistor control 50 k ? cmos input ? schmitt input ? ttl input ? automotive input l input standby control ? main oscillation i/o n input standby control ? sub oscillation i/o automotive input standby control standby control standby control standby control cmos - hys input digital output digital output pull - up control pull - down control cmos input automotive input ttl input analog input mb91590 series mn705-00009-3v0-e 74
chapter 1: overview 11 . i/o circuit types fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 75 type circuit remarks o ? analog input, 3.3v general - purpose i/o port ? output 2ma, 5ma, 10ma and 20ma ? pull - up resistor control 33 k ? pull - down resistor control 33 k ? s chmitt input ? ttl input p mode input control ? mode i/o ? schmitt input s analog input ? analog input(3v) t analog output ? analog output(3v) pull - up control digital output digital output pull - down control standby control ttl input standby control cmos - hys input mb91590 series mn705-00009-3v0-e 75
chapter 1: overview 11 . i/o circuit types fujitsu semiconductor limited chapter: overview fujitsu semiconductor confidential 76 mb91590 series mn705-00009-3v0-e 76
chapt er 2: handling the device 1 . handling precautions fujitsu semiconductor limited chapter: han dling the device fujitsu semiconductor confidential 1 chapter : h andling the device this chapter explains the notes on using this series . 1. handling precautions 2. handling device 3. application notes c ode : 02_mb91590_hm_e_introdution_00 4 _2011112 7 mb91590 series mn705-00009-3v0-e 77
chapt er 2: handling the device 1 . handling precautions fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 2 1. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is greatly affected by the conditi ons in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observed to minimize the chance of failure and to obtain higher reliability from your fujitsu semiconductor devices. ? precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc. ) in excess of certain e stablished limits , called absolute maximum rating. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. all the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on th e d ata sheet . users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? processing and protection of p ins these precautions must be followed when handling th e pins which connect s emiconductor devices to power supply and input/output functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output pins shorting of output p ins to supply pins or other output pins, or connection to large capacitance can cause large current flows. such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. handling of unused input pin s unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor devices are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundred ma to flow continuous ly at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to prevent this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the power - on sequence. mb91590 series mn705-00009-3v0-e 78
chapt er 2: handling the device 1 . handling precautions fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 3 ? observ ance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regulations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such a s redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions. ? precautions related t o usage devices fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect hu man lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) a re re quested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. ? precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under fujitsu semiconductor 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertion type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the board, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - holes on the boa rd and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes shou ld conform to fujitsu semiconductor recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recomm ended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the u se of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. fujitsu semiconductor recommends the solder reflow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with fujitsu semiconductor ranking of recommended conditions. ? lead - free packaging caution: w hen ball grid ar ray (bga) packages with sn - ag - cu balls are mounted using sn - pb eutectic soldering , junction strength may be reduced under some conditions of use . mb91590 series mn705-00009-3v0-e 79
chapt er 2: handling the device 1 . handling precautions fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 4 ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. to prevent, do the following: (1) avoid exposure to rapid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. (2) use dry boxes for product storage. products should be stored below 70% re lative humidity, and at temperatures between 5 and 30 . when you open dry package that recommends humidity 40% to 70% rh. (3) when necessary, fujitsu semiconductor packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be seale d in their aluminum laminate bags for storage. (4) avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the fujitsu recomm ended conditions for baking. condition: 125 /24 h ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following precautions: (1) maintain relative humidity in the working environment between 40% and 70%.use of an apparatu s for ion generation may be needed to remove electricity. (2)electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. (3)eliminate static body electricity by the use of rings or bracelets connected to ground through hig h resistance (on the level of 1m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. (4)ground all fixtures and instruments, or protect with anti - static measures. (5)avoid the use of styrofoam or other highl y static - prone materials for storage of completed board assemblies. ? precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions as described above. for reliable performance, do the following: (1) humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing (2)discharge of static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. (3)corrosive gases, dust, or oil exposure to corrosive gases or contact with dust or oil may lead to chemical reac tions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. (4)radiation, including cosmic radiation most devices are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. (5)smoke, flame caution: plastic molded devices ar e flammable , and t herefore should not be use near combustible substances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of fujitsu semiconductor products in other special environmental conditions should consul t with sales representatives. mb91590 series mn705-00009-3v0-e 80
chapt er 2: handling the device 1 . handling precautions fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 5 please check the latest handling precautions at the following url. http://edevice.fujitsu.com/fj/handling - e.pdf mb91590 series mn705-00009-3v0-e 81
chapt er 2: handling the device 2 . handling device fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 6 2. handling device this section explains the handling device. ? notes on handling device this section explains the la t ch - up prevention and pin processing . ? for la t ch - up prevention if a voltage higher than vcc or a vol tage lower than vss is applied to an i/o pin, or if a voltage exceeding the ratings is applied between v cc and v ss pins, a latch - up may occur in cmos ic. if the latch - up occurs, the power supply current increases excessively and device elements may be damaged by heat. take care to prevent any voltage from exceeding the maximum ratings in device application. also, the an a log power supply (av cc 5 , av r h 5) , the ntsc power supply (av cc 3, avr3), analog input and power supply to high - current output buffer pins mus t not be exceed the digital power supply (v cc 5 or v cc 3) when the power supply to the analog system and high- current output buffer pins is turned on or off. in the correct power - on sequence of the microcontroller unit , turn on the digital power supply (v cc5 ), analog power supplies (av cc 5, avrh5), and the power supply of high- current output buffer pins (dv cc ) simultaneously. or, turn on the digital power supply (v cc 5 ), and then turn on analog power supplies ( av cc 5, avrh5) and the power supply of high - current output buffer pins (dv cc). in the correct power - on sequence of gdc unit , similarly turn on the digital power supply (v cc 3) and the ntsc analog power supply (av cc 3) simultaneously. or, turn on the digital power supply (v cc 3 ), and then turn on the ntsc analo g power supply (av cc 3). ? treatment of unused pins if unused input pins are left open, they may cause a permanent damage to the device due to malfunction or latch - up. connect a 2k resistor or more to each of unused pins for pull - up or pill - down processing. also, if i/o pins are not used, they must be set to the output state for releasing or they must be set to the input state and treated in the same way as for the input pins. mb91590 series mn705-00009-3v0-e 82
chapt er 2: handling the device 2 . handling device fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 7 ? power supply pins the device is designed to ensure that if the device contains m ultiple v cc or v ss pins, the pins that should be at the same potential are interconnected to prevent latch - up or other malfunctions. further, connect these pins to an external power s upply or ground to reduce unwanted radiation, prevent strobe signals from malfunctioning due to a raised ground level, and fulfill the total output current standard, etc. as shown in figure 2-1 , all vss power supply pins must be treated in the similar way. if multiple vcc or vss systems are connected, the device cannot operate correctly even within the guaranteed operating range. figure 2-1 power supply input pins the power supply pins should be connected to vcc and vss of this device at the low impedance from the power supply source. in the area close to this device, a ceramic capacitor having the capacitance larger than the capacitor of the c pin is recommended to use as a bypass capacitor between vcc and vss pins . ? crystal oscillation circuit an external noise to the x0 or x1 pin may cause a device malfunction. the printed circuit boa rd must be designed to lay out x0 and x1 pins, crystal oscillator (or ceramic resonator), and the bypass capacitor to be grounded to the close position to the device. the printed circuit board artwork is recommended to surround the x0 and x1 pins by ground circuits. ? mode pins (md 2 , md1, md0 ) connec t the md2, md1 and md0 m ode pin s to the v cc or v ss pin directly. to prevent an erroneous selection of test mode caused by the noise, reduce the pattern length between each mode pin and v cc or v ss pin on the printed circuit board. also, use the low - impedance pin connection. ? during power - on to prevent a malfunction of the voltage step - down circuit built in the device, set the voltage rising time to have 50 s or longer (between 0.2v and 2.7v) during power - on. ? notes during pll clock operation when the pll clock is selected and if the oscillator is disconnected or if the input is stopped, this clock may continue to operate at the free running frequency of the self oscillator circuit built in the pll clock. this operation is not guaranteed. vss vss vcc vcc vss vcc mb91590 series mn705-00009-3v0-e 83
chapt er 2: handling the device 2 . handling device fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 8 ? treatment of a/d converter power supply pins connect the pins to have av cc 5=avrh5=v cc 5 and av ss 5/avrl5=v ss even if the a/d converter is not used. also, similarly connect the pins of ntsc a/d convert e r power supply to have av cc3 =v cc3 and av ss3 =v ss . at this time, open vin/refout. ? no tes on using external clock an external clock is not supported. none of the external d irect clock input can be used for both main clock and sub clo ck . ? power - on sequence of a/d converter power supplies and analog inputs be sure to turn on the digital power supply (v cc5 ) first, and then turn on the a/d converter power supplies (avcc 5 , avrh 5 , avrl 5 ) and analog inputs (an0 to an31). also, turn off the a/ d converter power supplies and analog inputs first, and then turn off the digital power supply (v cc5 ). when the avrh 5 is turned on or off, it must not exceed av cc5 . even if a common analog input pin is used as an input port, its input voltage must not exce ed av cc5 . (however, the analog power supply and digital power supply can be turned on or off simultaneously.) be sure to similarly turn on the digital power supply ( v cc 3 ) first, and then turn on the a/d converter power supply ( av cc 3 ) for ntsc and ntsc inpu ts (vin, avr). also, turn off the a/d converter power supplies and analog inputs first, and then turn off the digital power supply ( v cc3 ). ? treatment of power supplies for high current output buffer pins (dvcc, dvss) be sure to turn on the digital power supply (vcc) first, and then turn on the power supplies for high current output buffer pins (dvcc, dvss). also, turn off the power supplies for high current output buffer pins first, and then turn off the digital power supply (vcc). even if the high current o utput buffer pins are used as general - purpose ports, the power supplies of high current output buffer pins (dvcc, dvss) must be powered. ( t he power supplies of high current output buffer pins and the digital power supplies can be turned on or off simultane ously. ) ? treatment of c pin this device contains a voltage step - down circuit. a capacitor must always be connected to the c pin to assure the internal stabilization of the device. for the standard values, see the "recommended operating conditions" of the l atest data sheet. note: for the detailed specifications of operating voltages, see the latest data sheet . mb91590 series mn705-00009-3v0-e 84
chapt er 2: handling the device 3 . application notes fujitsu semiconductor limited chapter: handlin g the device fujitsu semiconductor confidential 9 3. application notes this section explains a pplication n otes . 3.1 function switching of a multiplexed port 3.2 low - power consumption mode 3.3 notes when writing data in a register having the status flag mb91590 series mn705-00009-3v0-e 85
chapt er 2: handling the device 3 . application notes fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 10 3.1. function switching of a multiplexed port function s witching of a m ultiplexed p ort is shown. to switch between the port function and the multiplexed pin function, use the pfr (port function register). for details, see "chapter : i/o ports". mb91590 series mn705-00009-3v0-e 86
chapt er 2: handling the device 3 . application notes fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 11 3.2. low - power consumption mode this section explains l ow - power c onsumption m ode . to transit t o the sleep mode, watch mode, stop mode, watch mode(power shutdown ) or stop mode(power shutdown ), follow the procedure explained in the "activating the sleep mode, watch mode, or stop mode" o r the "activating the watch mode (power shutdown ) or stop mode (power shutdown )" of "chapter : power c onsumption control". and gdc part and micom part should be power - controlled separately. take the following notes when using a monitor debugger. ? do not set a break point for the low - power consumption transition program. ? do not execute an operation step for the low - power consumption transition program. mb91590 series mn705-00009-3v0-e 87
chapt er 2: handling the device 3 . ap plication notes fujitsu semiconductor limited chapter: handling the device fujitsu semiconductor confidential 12 3.3. notes when writing data in a register having the status flag this section explains n otes w hen w riting d ata in a r egister h aving the s tatus f lag . when writing data in the register that has a status flag (especially, an interrupt request flag) to control function , tak ing care not to clear its status flag erroneously must be followed. the program must be written not to clear the flag to the status bit, and then to set the control bits to have the desired value. especially, if multiple control bits are used, the bit instruction cannot be used. (the bit instruction can access to a single bit only.) by t he byte, half - wo rd, or word access , data is written to the control bits and status flag simultaneously. during this time, take care not to clear other bits (in this case, the bits of status flag) erroneously. note: it is not necessary to note that the bit instruction considers this respect compared with the register to which read - modify - write (rmw) is supported. when the bit instruction is used for the register to which read - modify - write (rmw) is not supported, it is necessary to note it. mb91590 series mn705-00009-3v0-e 88
chapter 3: cpu 1 . overview fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 1 c hapter : cpu this chapter explains the cpu. 1. overview 2. features 3. cpu operating description 4. pipeline operation 5. floating point operation processing 6. data structure 7. addressing 8. programming model 9. reset and eit processing 10. memory protection function (mpu) code : 03_mb91590_hm_e_cpu_00 5 _201111 27 mb91590 series mn705-00009-3v0-e 89
chapter 3: cpu 1 . overview fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 2 1. overview this section explains the overview of the cpu. th e fr81 architecture is a microcontroller architecture that uses the fr family instruction set with improved floating point functionality, memory protection functionality and on- chip debugging functionality. the integer family instruction set is compatibl e with the fr80. for details, see "fr family fr81 32 - bit microcontroller programming manual". mb91590 series mn705-00009-3v0-e 90
chapter 3: cpu 2 . features fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 3 2. features this section explains features of the cpu. the fr family is a cpu core for 32 - bit risc - based controllers equipped with a custom fujitsu architecture. in particular, this architecture is optimal as the cpu core in microcontrollers designed for embedded control applications that require high - speed control. ? general ? general - purpose register architecture (32 - bit 16) ? 32- bit address space (4gb) ? 16- bit fixed i nstruction length (excluding immediate data transfer instructions) ? high - speed processing of basic instructions at one instruction per cycle using a 5 - stage pipeline architecture ? 32- bit 32- bit multiplication instruction that completes in 5 cycles ? 32- bit/3 2- bit division instruction by stepped division ? direct addressing instructions for accessing peripherals ? high - speed interrupt processing that finishes in six cycles ? single precision floating point arithmetic instructions ? floa ting point register 32 - bit 16 ? privilege mode and user mode ? protection of some address - mapped registers as system registers during user mode ? protection of some instructions as privilege instructions during user mode ? fpu, instruction access, and data access exception functions ? fpu except ions ? instruction access protection violation exception ? data access protection violation exception ? illegal instruction exception (changed from undefined instruction exception) ? data access error exception ? non - existent fpu exception ? memory protection function ( mpu ) ? eight protection areas can be specified common to instructions and data ? the protection areas are determined in a fixed order of precedence.(the areas can overlap) ? areas are specified by a page address and a page size ? page size : can be specified as 2 n bytes from 16 bytes ? page address : misaligned address also supported ? the following access privileges are controlled using privilege mode and user mode ? instruction fetch (execution) permitted / forbidden ? read permitted / forbidden ? write permitted / forbid den ? the following attributes can be specified for each area ? bufferable/non - bufferable ? access privileges and attributes can be specified for unset areas ? on protection violation, an instruction access protection violation exception or data access protection violation exception occurs mb91590 series mn705-00009-3v0-e 91
chapter 3: cpu 2 . features fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 4 ? floating p oint o perations ? ieee754 compliant ? support single precision ? six exception sources are supported. ? underflow ? overflow ? division - by - zero ? invalid operation ? inexact ? inputs an unnormalized number ? the only rounding mode supporte d is nearest value ? denormalized numbers are truncated to 0 or generate an exception ? floating - point register: 32 - bit 16 sets ? multiply and add, multiply and sub instructions supported ? division and square root operations supported mb91590 series mn705-00009-3v0-e 92
chapter 3: cpu 3 . cpu operating description fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 5 3. cpu operating description this section explains the operation of the cpu. ? cpu operating status the cpu operation state includes the following states: reset state, normal run state, low - power consumption state, and debug run state. the operating state transitions are shown below. figure 3 - 1 cpu operating state transition diagram ? reset state the reset state is the state when the cpu is being reset. resets consist of two levels: initialize level and reset level. when an initialize level reset is issued, everything in the chip is initialized. for the reset level, others exclusive of the debug control functions, clocks, and reset control functions are initialized. ? normal run state the normal run state is the state when sequential instruction and eit process ing are executed. the normal run state has privilege mode and user mode. in user mode, there are restrictions on instructions and access destination, and there are instructions and access destinations that can only be executed in privilege mode. when the cpu enters the normal run state after reset is released, the cpu enters privilege mode, and changes to user mode when reti is executed . the transition from user mode to privilege mode in the normal run state is triggered by reset or the eit execution, and t ransition from privilege mode to user mode is triggered by the reti execution. reset state dsu directive low - power consumption state debug state privilege mode user mode privilege mode user mode user state reti eit reti low - power consumption mode transition sequence execut ion reti eit eit eit low - power consumption mode transition sequence execut ion reset break dsu directive dsu directive ice not connected debug run state normal run state mb91590 series mn705-00009-3v0-e 93
chapter 3: cpu 3 . cpu operating description fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 6 ? low - power consumption state the low - power consumption state is the state when the cpu is stop p ed to reduce the power consumption. the transition to the low - power consumption st ate is carried out by the standby control of the the clock control unit. the low - power consumption state has three modes: sleep, stop and watch mode. recovery from the low - power consumption state is carried out by interrupts. ? debug run state the debug run state is the state when the cpu is connected to ice and debug related functions are enabled. the debug run state has two states: a user state and a debug state. the transition between the debug run state and other states is basically carried via the reset state. however, the transition from the normal run state to the debug run state forcefully is also enabled. the user state has a privilege mode and a user mode as the normal run state. however, when a break for debugging is carried out, the state changes to the debug state. in the debug state, instructions are executed in a privilege mode and all registers and memory can be accessed under the state when the memory protection function, etc. is disabled. the transition from a debug state to a user state is carried by the reti instruction. mb91590 series mn705-00009-3v0-e 94
chapter 3: cpu 4 . pipeline operation fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 7 4. pipeline operation this section explains the pipeline operation of the cpu. in fr81, the common pipeline processing is carried out by the decode stage, and there are two types of pipelines such as an integer pipeline and a floating point pipeline from the execution stage. although the completion between each pipeline processing differs from the sequence of instruction issuance s, the processing results based on the program sequence are guaranteed. for details, see "fr fami ly fr81 32 - bit microcontroller programming manual". mb91590 series mn705-00009-3v0-e 95
chapter 3: cpu 5 . floating point operation processing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 8 5. floating p oint o peration processing the f loating point operation processing for the cpu is show n. this series incorporates fpu. for details of the floating point operation processing, see "fr family fr81 32- bit microcontroller programming manual" . mb91590 series mn705-00009-3v0-e 96
chapter 3: cpu 6 . data structure fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 9 6. data structure this section explains the data structure . the data types which can be handled with fr81 family cpu are the integer type, which can be handled with fr80 family or earlier, and the single precision floating point type. for the integer type, little endian as the bit ordering and big endian as the byte ordering are used. for details, see "fr family fr81 32 - bit microcontroller programming manual". mb91590 series mn705-00009-3v0-e 97
chapter 3: cpu 7 . addressing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 10 7. ad dressing this section explains addressing of the cpu . a m emory space is 32 - bit linear. the cpu manages the address space in bytes. specify a value of 32 - bit for the address on the address space to access from the cpu. figure 7-1 shows the address space. figure 7-1 memory map 0x0000 0000 byte data direct addressing area 0x0000 0100 half - word data 0x0000 0200 word data 0x0000 0400 20- bit addressing area -- -- tbr 0x000f fc00 vector table 0x0010 0000 32- bit addressing area -- -- 0xffff ffff the a ddress space is also called memory space. the a ddress space is the cpu - based logical address space. address conversion is not performed. the cpu - based logic al address is same as the physical address where memory and i/o are actually located. for details, see "fr family fr81 32 - bit microcontroller programming manual". mb91590 series mn705-00009-3v0-e 98
chapter 3: cpu 8 . programming model fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 11 8. program m ing model this section explains the programming model of the cpu. the cpu of fr81 ha s general - purpose registers, dedicated registers, and floating point registers. besides these registers, the fr81 core has address - mapped system registers. mb91590 series mn705-00009-3v0-e 99
chapter 3: cpu 8 . programming m odel fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 12 8.1. general-purpose registers, dedicated registers, and floating point registers this section explains general - purpose registers, dedicated registers, and floating point registers . figure 8-1 shows the initial values for this series. for details of each register, see "fr family fr81 32 - bit microcontroller programming manual". figur e 8-1 initial values of general - purpose registers, dedicated registers, and floating point registers 32 bit [initial value] ac fp sp r15 r14 r13 r12 r11 r10 r9 r8 r7 r6 r5 r4 r3 r2 r1 r0 0000 000 0 h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h 32 bit [initial value] fr15 fr14 fr13 fr12 fr11 fr10 fr9 fr8 fr7 fr6 fr5 fr4 fr3 fr2 fr1 fr0 xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h xxxx xxx x h 32 bit [initial value] pc xxxx xxx x h ps ilm=0111 1 h ssr=001 1 h ccr=xx00xxx x h scr=xx 0 h tbr 000f fc0 0 h rp xxxx xxx x h ssp 0000 000 0 h usp xxxx xxx x h mdh xxxx xxx x h mdl xxxx xxx x h bp xxxx xxx x h fcr xxxx xxx x h esr 0000 000 0 h program counter program status table base register return pointer system stack pointer user stack pointer multiplication and division result register base pointer fpu control register exception status register configuration and initial values of general-purpose registers configuration and initial values of dedicated registers configuration and initial values of floating point registers mb91590 series mn705-00009-3v0-e 100
chapter 3: cpu 8 . programming model fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 13 8.2. system register this section explains system register . system register is an address mapping register for controlling system . these registers can be accessed only in the privilege mode. there are system registers as follows. ? clock control - related register ? reset control - related register ? debug control - related register ? memory protection - related register ? dma - relat ed register ? watchdog timer register ? wild register control register ? flash control register when these registers are written and /or read in the user mode, the illegal instruction exception (data access error) occurs. the access protection to system register s is judged on a priority bases than the memory protection function. therefore, when user access to the system register area is enabled in the memory protection function and access is disabled in the privilege mode, those settings are disabled. read and /or write is enabled only in the privilege mode and read and/or write is disabled in the user mode. mb91590 series mn705-00009-3v0-e 101
chapter 3: cpu 9 . reset and eit processing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 14 9. reset and eit processing this section explains reset and eit processing . reset and eit processing is the processing that is carried out by other than normal p rograms when reset, exception, interrupt and trap are detected. mb91590 series mn705-00009-3v0-e 102
chapter 3: cpu 9 . reset and eit processing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 15 9.1. reset this section explains reset . reset forcibly suspends operations currently running, initializes the device and restarts the program from the reset vector entry address. note: in this seri es, the fixed vector function return s not the value written in the address of 0xf_fffc on flash memory but the first address of + 0x0024 on flash memory to reset vector. see " chapter 10 fixedvector function " for details. mb91590 series mn705-00009-3v0-e 103
chapter 3: cpu 9 . reset and eit processing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 16 9.2. eit processing this section explain s the eit processing. the eit processing suspends operations currently running, stores resum able information into memory and transfers control to the predetermined processing program. mb91590 series mn705-00009-3v0-e 104
chapter 3: cpu 9 . reset and eit processing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 17 9.3. vector table the v ector t able is shown. table 9-1 vector table interruption factor interrupt vector number interrupt level offset address at tbr initial value decimal hexa decimal reset 0 00 - 0x3fc 0x000ffffc system r eserv ed 1 01 - 0x3f8 0x000ffff8 system r eserv ed 2 02 - 0x3 f4 0x000ffff4 system r eserv ed 3 03 - 0x3f0 0x000ffff0 system r eserv ed 4 04 - 0x3ec 0x000fffec fpu exception 5 05 - 0x3e8 0x000fffe8 instruction access protection violation exception 6 06 - 0x3e4 0x000fffe4 data access protection violation exception 7 07 - 0x3e0 0x000fffe0 data access error interrupt 8 08 - 0x3dc 0x000fffdc inte instruction 9 09 - 0x3d8 0x000fffd8 instruction break 10 0a - 0x3d4 0x000fffd4 system r eserv ed 11 0b - 0x3d0 0x000fffd0 system reserved 12 0c - 0x3cc 0x000fffcc system r es erv ed 13 0d - 0x3c8 0x000fffc8 illegal instruction exception 14 0e - 0x3c4 0x000fffc4 nmi request 15 0f 15(0xf) fixed 0x3c0 0x000fffc0 peripheral interrupt #0 16 10 icr00 0x3bc 0x000fffbc peripheral interrupt #1 17 11 icr01 0x3b8 0x000fffb8 peripheral interrupt #2 18 12 icr02 0x3b4 0x000fffb4 peripheral interrupt #3 19 13 icr03 0x3b0 0x000fffb0 peripheral interrupt #4 20 14 icr04 0x3ac 0x000fffac peripheral interrupt #5 21 15 icr05 0x3a8 0x000fffa8 peripheral interrupt #6 22 16 icr06 0x3a4 0x000fffa 4 peripheral interrupt #7 23 17 icr07 0x3a0 0x000fffa0 peripheral interrupt #8 24 18 icr08 0x39c 0x000fff9c peripheral interrupt #9 25 19 icr09 0x398 0x000fff98 peripheral interrupt #10 26 1a icr10 0x394 0x000fff94 peripheral interrupt #11 27 1b icr11 0x390 0x000fff90 peripheral interrupt #12 28 1c icr12 0x38c 0x000fff8c peripheral interrupt #13 29 1d icr13 0x388 0x000fff88 peripheral interrupt #14 30 1e icr14 0x384 0x000fff84 peripheral interrupt #15 31 1f icr15 0x380 0x000fff80 peripheral interr upt #16 32 20 icr16 0x37c 0x000fff7c peripheral interrupt #17 33 21 icr17 0x378 0x000fff78 peripheral interrupt #18 34 22 icr18 0x374 0x000fff74 peripheral interrupt #19 35 23 icr19 0x370 0x000fff70 peripheral interrupt #20 36 24 icr20 0x36c 0x000fff6c peripheral interrupt #21 37 25 icr21 0x368 0x000fff68 peripheral interrupt #22 38 26 icr22 0x364 0x000fff64 peripheral interrupt #23 39 27 icr23 0x360 0x000fff60 peripheral interrupt #24 40 28 icr24 0x35c 0x000fff5c peripheral interrupt #25 41 29 icr 25 0x358 0x000fff58 peripheral interrupt #26 42 2a icr26 0x354 0x000fff54 peripheral interrupt #27 43 2b icr27 0x350 0x000fff50 mb91590 series mn705-00009-3v0-e 105
chapter 3: cpu 9 . reset and eit processing fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 18 interruption factor interrupt vector number interrupt level offset address at tbr initial value decimal hexa decimal peripheral interrupt #28 44 2c icr28 0x34c 0x000fff4c peripheral interrupt #29 45 2d icr29 0x348 0x000fff48 peripheral inte rrupt #30 46 2e icr30 0x344 0x000fff44 peripheral interrupt #31 47 2f icr31 0x340 0x000fff40 peripheral interrupt #32 48 30 icr32 0x33c 0x000fff3c peripheral interrupt #33 49 31 icr33 0x338 0x000fff38 peripheral interrupt #34 50 32 icr34 0x334 0x000fff 34 peripheral interrupt #35 51 33 icr35 0x330 0x000fff30 peripheral interrupt #36 52 34 icr36 0x32c 0x000fff2c peripheral interrupt #37 53 35 icr37 0x328 0x000fff28 peripheral interrupt #38 54 36 icr38 0x324 0x000fff24 peripheral interrupt #39 55 37 i cr39 0x320 0x000fff20 peripheral interrupt #40 56 38 icr40 0x31c 0x000fff1c peripheral interrupt #41 57 39 icr41 0x318 0x000fff18 peripheral interrupt #42 58 3a icr42 0x314 0x000fff14 peripheral interrupt #43 59 3b icr43 0x310 0x000fff10 peripheral in terrupt #44 60 3c icr44 0x30c 0x000fff0c peripheral interrupt #45 61 3d icr45 0x308 0x000fff08 peripheral interrupt #46 62 3e icr46 0x304 0x000fff04 delay interrupt 63 3f icr47 0x300 0x000fff00 system r eserv ed ( for realos use ) 64 40 - 0x2fc 0x000ffefc system r eserv ed ( for realos use ) 65 41 - 0x2f8 0x000ffef8 for int instruction use 66 42 0x2f4 0x000ffef4 | | - | | 255 ff 0x000 0x000ffc00 mb91590 series mn705-00009-3v0-e 106
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 19 10. memory protection function (mpu) this section explains the memory protection function (mpu) of the cpu. 10.1 . overview 10.2 . list of registers 10.3 . description of registers 10.4 . operation s of m emory p rotection f unction (mpu) mb91590 series mn705-00009-3v0-e 107
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 20 10.1. overview the o verview of the m emory protection function (mpu) is shown. this architecture supports a memory protection function. the memory protection function is a function that monitors access to a specified area and generates an exception on prohibited access. however, protection sp ecified on system registers is ignored. ? eight protection areas can be specified that are shared by instructions and data ? the protection area with the highest priority is area 0, with the priority decreasing for areas 1, 2, 3, etc. (the areas can overlap) ? a reas are specified by a page address and a page size ? page size: can be specified in units of 2 n bytes from 16 bytes ? page address: misaligned addresses also supported ? the following access privileges are controlled using privilege mode and user mode ? instruct ion fetch : enabled / disabled ? data read : enabled / disabled ? data write : enabled / disabled ? attributes are specified for each area ? buffer : enabled / disabled ? the access rights and attributes of undefined areas are controlled as a default area ? p rotection violation exception s occur when a protection violation occurs ? the register for the memory protection function can only be accessed in a privilege mode as system register s ? data access error notification function ? i/ o area (00000000 h to 0000ffff h ) is fixed buffer d isabled mb91590 series mn705-00009-3v0-e 108
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 21 10.2. list of registers the l i st of registers is shown. table 10 -1 registers map add re ss register s register function +0 +1 +2 +3 0x0310 reserved mpucr mpu control register 0x0314 reserved 0x0318 reserved 0x031c reserved 0x0320 dpvar data access protection violation address register 0x0 324 reserved dpvsr data access protection violation status register 0x0328 dear data access error address register 0x032c reserved desr data access error status register 0x0330 pabr0 protect ion area base address register 0 0x0334 reserved pacr0 protect ion area control register 0 0x0338 pabr1 protection area base address register 1 0x033c reserved pacr1 protection area control register 1 0x0340 pabr2 protection area base address register 2 0x0344 reserved pacr2 protection area control register 2 0x0 348 pabr3 protection area base address register 3 0x034c reserved pacr3 protection area control register 3 0x0350 pabr4 protection area base address register 4 0x0354 reserved pacr4 protection area control register 4 0x0358 pabr5 protection area base a ddress register 5 0x035c reserved pacr5 protection area control register 5 0x0360 pabr6 protection area base address register 6 0x0364 reserved pacr6 protection area control register 6 0x0368 pabr7 protection area base address register 7 0x036c reserv ed pacr7 protection area control register 7 mb91590 series mn705-00009-3v0-e 109
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 22 10.3. description of registers register s are shown. 10.3.1 . mpu control register (mpucr) 10.3.2 . instruction a ccess p rotection v iolation a ddress r egister (ipvar) 10.3.3 . instruction a ccess p rotection v iolation s tatus r egister (ipvsr) 10.3.4 . data a ccess p rotection v iolation a ddress r egister (dpvar) 10.3.5 . data a ccess p rotection v iolation s tatus r egister (dpvsr) 10.3.6 . data access error a ddress register (dear) 10.3.7 . data a ccess e rror s tatus r egister (desr) 10.3.8 . protection area base address register 0 to 7 (pabr0 to pabr 7) 10.3.9 . protection area control register 0 to 7 (pacr0 to pacr 7) mb91590 series mn705-00009-3v0-e 110
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 23 10.3.1. mpu control register (mpucr) t he bit configuration of the mpu c ontrol r egister (mpucr) is shown. the mpu control register controls whether the mpu is enabled or disabled, and configures the access permissions in privilege mode and user mode to default areas (areas not specified as protection areas). ? mpucr : address 0312 h ( access : half - word ) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 pie pre pwe uie ure uwe reserved be initial value 0 0 0 0 0 0 - 0 attribute r/w r/w r/w r/w r/w r/w r0,w0 r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved pan1 pan0 dee mpe initial value - - - - 0 1 0 0 attribu te r0,w0 r0,w0 r0,w0 r0,w0 r0,wx r1,wx r/w r/w [bit15] pie (privilege mode instruction fetch enable) this bit is for permitting instruction fetch in privilege mode from the default areas (areas that have not been specified as protection areas). pie acces s to default area 0 instruction fetch not permitted in privilege mode (initial value) 1 instruction fetch permitted in privilege mode [bit14] pre (privilege mode read access enable) this bit is for permitting data read access in privilege mode from the default areas (areas that have not been specified as protection areas). pre access to default area 0 read access not permitted in privilege mode (initial value) 1 read access permitted in privilege mode [bit13] pwe (privilege mode write access enable) this bit is for permitting data write access in privilege mode to the default areas (areas that have not been specified as protection areas). pwe access to default area 0 write access not permitted in privilege mode (initial value) 1 write access permit ted in privilege mode mb91590 series mn705-00009-3v0-e 111
chapter 3: cpu 10 . memory protection func tion (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 24 [bit12] uie (user mode instruction fetch enable) this bit is for permitting instruction fetch in user mode from the default areas (areas that have not been specified as protection areas). uie access to default area 0 instruction fe tch not enable at user mode (initial value) 1 instruction fetch enable at user mode [bit11] ure (user mode read access enable) this bit is for permitting data read access in user mode from the default areas (areas that have not been specified as protection areas ). ure access to default area 0 read access not permitted in user mode (initial value) 1 read access permitted in user mode [bit10] uwe (user mode write access enable) this bit is for permitting data write access in user mode to the default ar eas (areas that have not been specified as protection areas). uwe access to default area 0 write access not permitted in user mode (initial value) 1 write access permitted in user mode [bit9] reserved always write "0" when writing . this bit reads out " 0". [bit8] be (buffer enable) the bit permits buffering to be used when performing data access to default areas (areas that are not specified as protection areas). when the use of buffering is forbidden, the cpu stops pipeline operation and waits for the d ata access to finish before starting the next operation. as a result, although the data access efficiency decreases, it is possible to perform data access synchronized to the instruction. illegal instruction exceptions occur when there is an error during d ata access only if buffering is forbidden. when buffering is permitted, data access errors can be notified as interrupts . be buffer enable specification for the default area 0 buffer disabled (initial value) 1 buffer enabled [bit7 to bit 4] reserved the se bits are reserved. always write "0" when writing. mb91590 series mn705-00009-3v0-e 112
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 25 [bit3 , bit 2] pan [1:0] (protection area number) indicates the number of configurable protection areas that can be specified. this bit is read - only and indicates the number of areas implemented in hard ware . pan [1:0] number of memory protection areas implemented 00 reserved 01 8 areas 10 12 areas 11 16 areas [bit1] dee (data access error interrupt enable) this bit permits interrupts to occur when a data access error occurs in areas where buffer ope ration is enabled. if a data access error occurs in an area where buffer operation is permitted while this bit is enabled, a data access error interrupt occurs. at this time, the address where the error occurred is stored in the data access error address register (dear), and the details of the access are stored in the data access error status register (desr). if interrupts are disabled, the above registers are updated only. dee data access e rror interrupt e nabled 0 data access error interrupt disabled (ini tial value) 1 data access e rror interrupt enable [bit0] mpe (memory protection unit enable) this bit is for enabling the memory protection function. if the memory protection function is disabled, buffering is configured as disabled for accesses to all a reas . mpe memory protection function 0 memory protection function disabled (initial value) 1 memory protection function enabled mb91590 series mn705-00009-3v0-e 113
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 26 10.3.2. instruction access p rotection violation address register (ipvar) t he bit configuration of the i nstruction access p rotection v iolation a ddress r egister is shown. this register stores the address where an instruction access protection violation occurred . also see " 10.4.2 . i nstruction a ccess p rotection violation " and " 10.4.7 . notes ". ? ipvar : address 0318 h (a ccess : word ) bit 31 ? ? ? bit 0 ipva[31:0] initial value x ? ? ? x attribute r,wx ? ? ? r,wx [bit31 to bit 0] ipva [31:0] (instruction fet ch protection violation address) this register stores the address where an instruction access protection violation occurred when a violation has not occurred in the instruction access protection violation status register (ipvsr:ipv =0). this is not aligned . note: this register is a prohibition of use. mb91590 series mn705-00009-3v0-e 114
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 27 10.3.3. instruction access p rotection violation s tatus register (ipvsr) t he bit configuration of the i nstruction access p rotection v iolation s tatus r egister is shown. this register indicates the status when an inst ruction access protection violation occurs. the content of this register is updated by hardware only when ipv=0. only writing "0" to the ipv bit has an effect. writes to any other bits and writing "1" to ipv are ignored . also see " 10.4.2 . i nstruction a ccess p rotection violation " and " 10.4.7 . notes ". ? ipvsr : address 031e h (a ccess : half - word ) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 reserved initial value - - - - - - - - attribute r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved sz [1:0] md reserved ipv initial value - - 0 0 0 - - 0 attribute r0,w0 r0,w0 r,wx r,wx r,wx r0,w0 r0,w0 r,w [bit15 to bit 6, bit 2 , bit 1] reserved these bits are reserved. always write "0" to th ese bit s. [bit5 , bit 4] sz [1:0] the access size when the violation occurred . sz[1:0] access size 00 byte 01 half - word 10 word 11 reserved [bit3] md indicates the mode of the access . md operation mode 0 access in user mode 1 access in privilege mode mb91590 series mn705-00009-3v0-e 115
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 28 [bit0] ipv (instruction fetch protection violation) this bit indicates that an instruction access protection violation occurred. in order to save the details of new prot ection violations, clear this bit . ipv i nstruction access protection violation 0 instruction access protection violation not detected (initial value) 1 instruction access protection violation detected note: this register is a prohibition of use. mb91590 series mn705-00009-3v0-e 116
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 29 10.3.4. data access p rotection v iolation address register (dpvar) t he bit configuration of the d ata access p rotection v iolation a ddress r egister is shown. the address where the violation of the data access protection occurs is saved . ? dpvar : address 0320 h (a ccess : wo rd ) bit 31 ? ? ? bit 0 dpva[31:0] initial value x ? ? ? x attribute r,wx ? ? ? r,wx [bit31 to bit 0] dpva [31:0] (data access protection violation address) this register stores the address where a data access protection violation occurre d when a violation has not occurred in the data access protection violation status register (dpvsr:dpv =0). this register indicates the address requested by the cpu, and the address is not aligned . mb91590 series mn705-00009-3v0-e 117
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 30 10.3.5. data access p rotection v iolation s tatus r egister (dpvsr) t he bit configuration of the d ata access p rotection v iolation s tatus r egister is shown. this register indicates the status when a data access protection violation occurs. the content of this register is updated by hardware only when dpv=0. writing "0" to dpv only is valid. writes to any other bits and writing "1" to dpv are ignored . ? dpvsr a ddress 0326 h (a ccess : half - word ) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w 0 r0,w0 r0,w0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw [1:0] sz [1:0] md reserved dpv initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r,wx r0,w0 r0,w0 r,w [bit15 to bit 8, bit 2 , bit 1] reserved these bits are reserved. always write "0" to th ese bit s. [bit7 , bit 6] rw [1:0] (read/write) the access type when the violation occurred. when a read - modify - write is executed, because both read and write access rights are required and the determination is made in the initial read cycle, rw=01 b read (read - modify - write) even if the violation occurs in the write part of the read - modify - write. rw [1:0] a ccess type 00 read 01 read ( read - modify - write ) 10 write 11 reserved mb91590 series mn705-00009-3v0-e 118
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 31 [bit5 , bit 4] sz [1:0] the access size when the violation occurred . sz[1:0] acc ess size 00 byte 01 half word 10 word 11 reserved [bit3] md indicates the mode of the access. md operation mode 0 access in user mode 1 access in privilege mode [bit0] dpv (data access protection violation) this bit indicates that a data access p rotection violation occurred. in order to save the details of new protection violations, clear this bit. writing "0" to this bit only is valid. writing "1" to the bit is ignored. dpv data access protection violation 0 data access protection violation not detected (initial value) 1 data access protection violation detected mb91590 series mn705-00009-3v0-e 119
chapter 3: cpu 10 . memory protection func tion (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 32 10.3.6. data access error address register (dear) t he bit configuration of the d ata access e rror address r egist er is shown. this register stores the address where a data access error occurred . ? dear : a ddress 0328 h (a ccess : word ) bit 31 ? ? ? bit 0 dea[31:0] initial value x ? ? ? x attribute r,wx ? ? ? r,wx [bit31 to bit 0] dea [31:0] (data access error address) this register stores the address where a data access error occurred when a violation has not occurred in the data access error status register (desr:dae =0). if the protection violation occurred while accessing system registers, the access address from the cpu is stored as it is without being aligned. if the result of performing a bus access is an error, the address is aligned. mb91590 series mn705-00009-3v0-e 120
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 33 10.3.7. data access e rror status register (desr) t he bit configuration of the d ata access e rror s tatus r egister is shown. this register indicates the status when a data access error occurs. the content of this register is updated by hardware only when dae=0. writing "0" to dae only is valid. writes to any other bits and writing "1" to dae are ignored . ? desr : a ddress 032e h ( a ccess : half - word ) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rw [1:0] sz [1:0] md reserved dae initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r,wx r0,w0 r0,w0 r,w [bit15 to bit 8, bit 2 , bit 1] reserved these bits are reserved. always write "0" to th ese bit s . th ese bit s read out "0" . [bit7 , bit 6] rw [1:0] (read/write) the access type when the error occurred . rw [1:0] a ccess type 00 read 01 read ( read - modify - wri te ) 10 write 11 reserved [bit5 , bit 4] sz [1:0] the access size when the error occurred . sz [1:0] a ccess size 00 byte 01 half - word 10 word 11 reserved mb91590 series mn705-00009-3v0-e 121
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 34 [bit3] md this bit i ndicates the mode of the access . md operation mode 0 access in user mode 1 access in privilege mode [bit0] dae (data access error) this bit indicates that a data access error occurred. in order to save the details of new data errors, clear this bit. the interrupt request is withdrawn by clearing this bit when the data access error interrupt is effectively done. only "0" writing is effective to this bit. "1" writing is invalid. dae data a ccess error 0 data access error not detected (initial value) 1 data access error detected mb91590 series mn705-00009-3v0-e 122
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 35 10.3.8. protection area base address register 0 to 7 (pa br0 to pabr 7) t he bit configuration of p rotection a rea b ase a ddress r egister 0 to 7 is shown. these registers set the base addresses of the protection areas for each mpu channel. ? pabr0 to pabr 7 : a ddress 0330 h , 0338 h , 0340 h ??? ( access : word ) bit31 ? ? ? bit8 pabr[31:8] initial value x x ? ? ? x x x attribute r/w r/w ? ? ? r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pabr[7:0] initial value x x x x 0 0 0 0 attribute r/w r/w r/w r/w r0,wx r0,wx r0,wx r0,wx [bit31 to bit 0] pabr [31:0] (protection area base address register) these registers point to the base address of the protection area. the area from the address specified here to the size specified by the protection area control registers (pacr0 to pacr7) is the protection area. the address does not need to be aligned to the protection area size. the lower 4 bits of the pabr register are fixed at " 000 0 b ". mb91590 series mn705-00009-3v0-e 123
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 36 10.3.9. protection area control register 0 to 7 (pacr0 to pacr 7) t he bit configuration of p rotection a rea c ontrol r egis ter 0 to 7 is shown. these registers set access permissions and restrictions for each mpu channel. ? pacr0 to pacr 7 address 0336 h , 033e h , 0346 h ??? (a ccess : half - word ) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 pie pre pwe uie ure uwe reserv ed be i nitial value 0 0 0 0 0 0 - 0 attribute r/w r/w r/w r/w r/w r/w r0,w0 r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 asz[4:0] reserved pae initial value 0 0 0 0 0 - - 0 attribute r/w r/w r/w r/w r/w r0,w0 r0,w0 r/w [bit15] pie (privilege mode instru ction fetch enable) this bit is for enabling instruction fetch in privilege mode for the specified protection area . pie access to the specified protect ion area 0 instruction fetch not permitted in privilege mode (initial value) 1 instruction fetch permit ted in privilege mode [bit14] pre (privilege mode read access enable) this bit is for enabling data read access in privilege mode for the specified protection area . pre access to the specified protect ion area 0 read access not permitted in privilege mod e (initial value) 1 read access permitted in privilege mode [bit13] pwe (privilege mode write access enable) this bit is for enabling data write access in privilege mode for the specified protection area . pwe access to the specified protec tion area 0 w rite access not permitted in privilege mode (initial value) 1 write access permitted in privilege mode mb91590 series mn705-00009-3v0-e 124
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 37 [bit 12] uie (user mode instruction fetch enable) this bit is for enabling instruction fetch in user mode for the specified protection area . uie acces s to the specified protect ion area 0 instruction fetch not permitted in user mode (initial value) 1 instruction fetch permitted in user mode [bit11] ure (user mode read access enable) this bit is for enabling data read access in user mode for the spec ified protection area . ure access to the specified protect ion area 0 read access not permitted in user mode (initial value) 1 read access permitted in user mode [bit10] uwe (user mode write access enable) this bit is for enabling data write access in u ser mode for the specified protection area . uwe access to the specified protect ion area 0 write access not permitted in user mode (initial value) 1 write access permitted in user mode [bit9] reserved always write "0" to this bit. this bit reads out "0 ". [bit8] be (buffer enable) this bit permits buffering to be used during data access for the specified protection area. when the use of buffering is forbidden, the cpu stops pipeline operation and waits for the data access to finish before starting the ne xt operation. as a result, although the data access efficiency decreases, it is possible to perform data access synchronized to the instruction . illegal instruction exceptions occur when there is an error during data access only if buffering is forbidden. when buffering is permitted, data access errors can be notified as interrupts . be buffer enable specification for the specified protection area 0 buffer disable (initial value) 1 buffer enable [bit7 to bit 3] asz [4:0] (area size) these bits specify the size of the specified protection area. the specified address does not need to be aligned to the sizes described below. furthermore, if the lower limit of the area specified by the address and size exceeds ffffffff h , the lower limit of the area is treated as ffffffff h . asz[4:0] size of the specified protectorate area 00000 reserved 00001 reserved mb91590 series mn705-00009-3v0-e 125
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 38 asz[4:0] size of the specified protectorate area 00010 reserved 00011 16b 00100 32b 00101 64b 00110 128b 00111 256b 01000 512b 01001 1kb 01010 2kb 01011 4kb 01100 8kb 01101 16kb 01110 32kb 01111 64kb 10000 128kb 10001 256kb 10010 512kb 10011 1mb 10100 2mb 10101 4mb 10110 8mb 10111 16mb 11000 32mb 11001 64mb 11010 128mb 11011 256mb 11100 512mb 11101 1gb 11110 2gb 11111 4gb [bit2 , bit 1] reserved these bits are reserved. always writ e "0" when writing . mb91590 series mn705-00009-3v0-e 126
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 39 [bit0] pae (protection area enable) this bit is for enabling the memory protection function. pae memory protection area 0 specified memory protection area disabled (initial value) 1 specified memory protection area enabled mb91590 series mn705-00009-3v0-e 127
chapter 3: cpu 10 . memory protection func tion (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 40 10.4. operatio n s of memory p rotection f unction (mpu) this section explains o peration s of the m emory p rotection f unction (mpu) of the cpu. 10.4.1 . setting up m emory p rotect ion areas 10.4. 2 . i nstruction a ccess p rotection violation 10.4.3 . d ata a ccess p rotection v iolation 10.4.4 . data access errors 10.4.5 . memory p rotection o peration by d elay s lot 10.4.6 . dear and desr update 10.4.7 . notes mb91590 series mn705-00009-3v0-e 128
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 41 10.4.1. setting up m emory p rotect ion areas t his section explains s etting up m emory p rotection a reas of the cpu. the memory protection function is configured by settings whether instructions, data reads, and data writes are permitted or forbidden in privilege mode and user mode for a maximum of eight protection areas specified by address and size, and default areas that are not contained in these protection areas. the buffer permitted or forbidden setting can also be configured for each area at the same time. if th ere are overlaps between specified protection areas, the area with the smallest number takes precedence. when the memory protection function is disabled (mpucr:mpe =0), access is performed with access permitted to all areas and buffering disabled. mb91590 series mn705-00009-3v0-e 129
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 42 10.4.2. i nstruction access p rotection violation t his section explains i nstruction access p rotection v iolation of the cpu. the memory protection unit (mpu) monitors cpu instruction fetches and determines whether instruction fetches are permitted to the accessed areas. the instruction address when an instruction access protection violation exception occurs can be determined from the pc value saved on the system stack. mb91590 series mn705-00009-3v0-e 130
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 43 10.4.3. data access p rotection v iolation t his section explains d ata access p rotection v iolation of the cpu. the me mory protection unit (mpu) monitors cpu data accesses and determines whether accesses (reads and writes) to the corresponding area are permitted. if an access was not permitted, the mpu stores that address and access information in the data access protection violation address register (dpvar) and the data access protection violation status register (dpvsr). however, if data access protection violation information already exists in the above register (dpvsr:dpv =1), this is not overwritten. the data access t hat caused the violation at this time is not performed. if a data access protection violation occurs during the execution of an instruction that performs multiple data accesses, the data accesses that had executed up until the violation occurred are not cancelled. if a data access protection violation exception occurs during the ldm0, ldm1, stm0, stm1, fldm, or fstm instructions, the list of remaining registers is stored in the exception status register esr:rl. if a data access protection violation occurs d uring the eit processing sequence or the reti instruction, the cpu is halted and can only be recovered by break interrupt or reset . mb91590 series mn705-00009-3v0-e 131
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 44 10.4.4. data access errors this section explains d ata access e rrors of the cpu. if the following conditions are satisfied during a d ata access, this is treated as a data access error and the access information at that time are stored in the data access error address register (dear) and data access error status register (desr). however, if data access error information already exists in the above register (desr:dae =1), this is not overwritten . ? system register access in user mode ? bus error during data access the operation after a bus error occurs during data access differs between accesses with buffering enabled and accesses with buffering disabled. system register accesses in user mode are always processed as illegal instruction exceptions (data access). if a data access error occurs during access to an unbufferable area, the cpu processes this as an illegal instruction exception (data access error). if a data access error occurs during access to a bufferable area, and if the data access error interrupt is enabled by mpu control register mpucr:dee =1, the data access error interrupt is triggered and the cpu performs data access error interrupt processing. if a data access error occurs during access to a bufferable area, because the cpu is executing a subsequence instruction, the pc saved when the data access error interrupt occurs is not the pc value for the instruction that performed th e data access. if an illegal instruction exception (data access error) occurs during the execution of an instruction that performs multiple data accesses, the data accesses that had executed up until the error occurred are not cancelled. if an illegal instruction exception (data access error) occurs during the ldm0, ldm1, stm0, stm1, fldm, or fstm instructions, the list of remaining registers is stored in the exception status register esr : rl, and the bit indicating a data access error esr:inv6 is set. if an illegal instruction exception (data access error) occurs during the eit processing sequence or the reti instruction, the cpu is halted and can only be recovered by break interrupt or reset. mb91590 series mn705-00009-3v0-e 132
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 45 10.4.5. memory p rotection o peration by dela y s lot the m emory p rotection o peration by a d elay s lot is shown. the instruction arranged in the delay slot is processed as 16 - bit. therefore, the exception is generated as an illegal instruction exception (instruction that cannot be arranged in the delay slot) even if there are an instruction access protection violation factor and an instruction access error factor in the lower 16- bit by arranging 32 - bit instruction in the delay slot. mb91590 series mn705-00009-3v0-e 133
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 46 10.4.6. dear and desr update the dear and the desr update are shown. the d ata access error address register (dear) and the data access error status register (desr) are renewed in the following cases. ? system register access in user mode (illegal instruction exception) ? bus error in buffer prohibition area access (illegal instruction e xception) ? bus error in buffer permission area access (data access error interrupt) dear and desr are renewed in the instruction that did the corresponding access and it is renewed to the asynchronization with the instruction operation in the case where the data access error interrupt is generated in the case where the illegal instruction exception is generated. it gives priority to the illegal instruction exception factor when the factor is generated at the same time. mb91590 series mn705-00009-3v0-e 134
chapter 3: cpu 10 . memory protection function (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 47 10.4.7. notes this section explains notes of the memory protection function (mpu). ? access protection violation exception will occur when an instruction of access protection violation is executed. for details, see "fr family fr81 32 - bit microcontroller programming manual". for details of the instruction access protection violation and the instruction access protection violation exception, also see " 10.4.2 . i nstruction a ccess p rotection violation ". ? if the boundary of delay slot is different from tha t of instruction access protection area, the instruction access protection violation occurs regardless of whether the branch is established or not. pc with occurrence of exception is pc of delayed branch instruction. beq:d l_myproc2 nop protection specified (instruction fetch) mb91590 series mn705-00009-3v0-e 135
chapter 3: cpu 10 . memory protection func tion (mpu) fujitsu semiconductor limited chapter: cpu fujitsu semiconductor confidential 48 mb91590 series mn705-00009-3v0-e 136
chapter 4: operation mode 1 . overview fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 1 c hapter : operation mode this chapter explains the operation mode. 1. overview 2. features 3. configuration 4. register 5. operation code : 04_mb91590_hm_e_mode_00 5 _201111 27 mb91590 series mn705-00009-3v0-e 137
chapter 4: operation mode 1 . overview fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 2 1. overview this section explains the overview of the operation mode. this chapter explains the operation mode of this type of item decided after reset is released. see " chapter : power consumption control " for the mode of each power consumption control and the mode of each clock selection. mb91590 series mn705-00009-3v0-e 138
chapter 4: operation mode 2 . features fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 3 2. features this section explains features of the operation mode. this device sup ports the following operation modes. ? user mode the external bus of the 16- bit bus width for gdc only can be used. the program starts from the built - in flash. ? serial writer mode it is a mode to which the built - in flash is programmed by using the s er i al wri ter. the program starts from the built - in boot - rom. mb91590 series mn705-00009-3v0-e 139
chapter 4: operation mode 3 . configuration fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the operation mode. figure 3-1 block diagram mode decision circuit reset control circuit on - chip b us address decoder i/o function mode se lector md0, md1, md2 external pin p127 exte rnal pin 4 mb91590 series mn705-00009-3v0-e 140
chapter 4: operation mode 4 . register fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 5 4. register this section explains the register of the operation mode. address register register function +0 +1 +2 +3 0x07fc bmodr reserved reserved reserved bus mode data register ? bus m ode register : bmodr (bus mode register ) this register indicates the mode that has been set during startup. the register data can be read only. data writing does not affect on this register value. ? bmodr : address 07fc h ( access : byte , half - word , word ) bi t 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bmod[7:0] initial value * * * * * * * * attribute r,wx r,wx r,wx r,wx r,wx r,wx r,wx r,wx * it depends on o peration m ode. [b it 7 to bit0 ] bmod[ 7:0] : operation mode these bits indicate the current operation mode. data w riting is ineffective. bmod[7 : 0] operation mode 0101xx x x user m ode 0111xx 1x serial writer mode mb91590 series mn705-00009-3v0-e 141
chapter 4: operation mode 5 . operation fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 6 5. operation this section shows operation s of the operation mode. 5.1 . md0 , md1 , md2, p127 pins settings 5.2 . fetching the operation mode 5.3 . explanation of each operation mode mb91590 series mn705-00009-3v0-e 142
chapter 4: operation mode 5 . operation fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 7 5.1. md0, md1, md2, p127 pins settings md0 , md1 , md2 and p127 p ins s ettings are shown. table 5-1 pin settings operation mode md2 md1 md0 p127 user mode 0 0 0 - serial writer mode 0 0 1 1 mb91590 series mn705-00009-3v0-e 143
chapter 4: operation mode 5 . operation fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 8 5.2. fetching the operation mode this section explains fetching the o peration m ode . the operation mode is fetched by sampling the rst (reset). during the time when an rst is issued and when it is released, the md0, md1 , md2 and p127 pin inputs must be determined. (the p127 pin needs no t be determined in the user mode.) the following shows an operation sequence from an occurrence of reset cause to the determi nation of an operation mod e. figure 5-1 operation mode fetch timing chart notes: (*1) continue fixing md0, md1 and md2 pins even after operating mode determined. when in serial writer mode, the p127 pin needs not be fixed after operating moded etermined. (*1) (*1) when the initialize reset (init) occurs; when reset (rst) occurs; (oscillation stabilization wait time) + pclk ? 4 cycles pclk ? 16 cycles pclk ? 16 cycles pclk ? 4 cycles pclk ? 16 cycles + chip reset sequence l bus idle waiting pclk factor pclk factor init (settings initialization reset) operation mode pin rst (operation initialization reset) init (settings initialization reset) operation mode pin rst (operation initialization reset) chip reset sequence when the initialization reset (init) occurs; rst (setting initialization reset) "l" determined. mb91590 series mn705-00009-3v0-e 144
chapter 4: operation mode 5 . operation fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 9 5.3. explanation of each operation mode this section explains e ach o peration m ode . the following details each operation mode. ? user mode an external bus pin is reset immediately when a reset is entered for the external reset pin. for details, see " d. pin status in cpu status " in " appendix ". ? serial writer mode contact their representatives . mb91590 series mn705-00009-3v0-e 145
chapter 4: operation mode 5 . operation fujitsu semiconductor limited chapter : operation mode fujitsu semiconductor confidential 10 mb91590 series mn705-00009-3v0-e 146
chapter 5: clock 1 . overview fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 1 chapter : clock this chapter explains the clock. 1. overview 2. features 3. configuration 4. register 5. operation code : 05_mb91590_ hm_e_clock _0 11 _2011112 7 mb91590 series mn705-00009-3v0-e 147
chapter 5: clock 1 . overview fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 2 1. overview this section explains the overview of the clock. the b uilt - in oscillation circuit generates a dual clock p roduct, which generate s individual clock systems on the chip. this product also implements the cr oscillation circuit for watchdog timer 1. ? external pins for the built - in oscillation circuit : main clock : connects to the crystal oscillator sub clock : connects to the crystal oscillator ? generation of source clocks : selects from the clocks which are multiplied by pll/sscg of main clock (mclk) or divided by 2 of main clock, or sub clock (sbclk). ? division of source clock : divides the source clock and generates operating clocks for supplying to each unit. mb91590 series mn705-00009-3v0-e 148
chapter 5: clock 1 . overview fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 3 figure 1-1 diagram of the clock generation system cr oscillat ion for wdt1 wdt1( hardware watchdog ) cr oscillation circuit (100khz) rtc/ wdt1 correction ( calibration ) source clock (srcclk) main clock (mclk) sub clock (sbclk) pll clock (pllclk) * non spread clock pll/sscg clock (pllssclk) * select a ble non sp read clock or spread clock microcontroller clock c ontrol main clock generation unit main clock (mclk) sub clock generation unit sub clock (sbclk) on - chip debugger (ocd) clock generation unit for debug i/f pll clock (m_pclk) rtc clock (watclk) to real time clock for debug i/f main clock ( m_mclk) watch ? power man age ment clock generation unit pmu clock (pmuclk) s ource clock select ion unit divided by 2 mclk2 / sbclk / pllssclk pll/sscg clock generation unit can prescaler clock can pr escaler clock selection unit selector peripheral clock (pclk2) peripheral clock divider control unit on chip bus clock (hclk) cpu clock (cclk) peripheral clock (pclk1) external bus clock (tclk) oscillation stop request/oscillation stop release req uest to ma in ? sub ? pll/sscg clock generation unit from main ? sub ? pll/sscg clock generation unit o scillation stabilization wait timer interrupt clock divider control uni t gdc pll/sscg c lock generation unit gdc clock control gdc pll clock (gpllclk) * ntsc and dotcl k gdc sscg clock (gsscgclk) * excluding ntsc and dotclk mb91590 series mn705-00009-3v0-e 149
chapter 5: clock 2 . features fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 4 2. features this section explains features of the clock. ? 2 system on - chip oscillators is implemented. ? the main clock (mclk) is multiplied by on - chip pll/sscg. ? mic rocontroller/gdc multiply clock is supplied by independent pll/sscg. ? each clock has been forced not to supply by using the timer until it becomes stabilized (oscillation stabilization wait timer). ? oscillation stabilization wait end interrupt can be generat ed. ? main clock oscillation stabilization wait timer (main timer) and sub clock oscillation stabilization wait timer (sub timer) can be used as a general - purpose interrupt interval timer after the oscillation stabilization of each clock for main, and sub t akes place. ? the clock for the real time clock can be selected from the main clock (mclk) and the sub clock (sbclk). ? implements a cr oscillation circuit for 100khz wdt1 clock. see "chapter : rtc/wdt1 calibration" for configuration (calibration) of this oscillation circuit. ? generates the clock for can prescaler. use the pll clock (pllclk) [non spread clock ] when using a pll, otherwise use the on - chip bus clock (hclk). ? for the noise decrement , the sscg clock [ spread clock ] can be selected as cpu and a clock of the resource. mb91590 series mn705-00009-3v0-e 150
chapter 5: clock 3 . configuration fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 5 3. configuration this section explains the configuration of the clock. figure 3-1 connection diagram of clock (1) -1 main clock gener a tion unit main timer mte mtc mcen oscillation stop request x 1 x0 mtmcr : mtif mosw mts mtie cmonr : mcrdy icr30 main timer interrupt mclk main clock stop mode cselr : mtmcr : mtmcr : cstbr : mtmcr : mtmcr : mb91590 series mn705-00009-3v0-e 151
chapter 5: clock 3 . configuration fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 6 figure 3-2 connection diagram of clock (1) - 2 sub clock gener a tion unit figure 3-3 connection diagram of clock (1) - 3 pll clock gener a tion unit sub timer ste stc scen oscillation stop request x1a x 0a stmcr: stif sosw sts stie cmonr : scrdy icr 30 sub timer interrupt sbclk sub clock stop mode cselr : stmcr : stmcr : cstbr: stmcr : stmcr : pl l timer ptmcr . pti f posw ptmcr . ptie cmonr . pcrdy pcen sscg - pll pll (non - sscg ) divider divider ccpsselr . pcsel pllssclk pll/sscg clock 1 0 pllclk pll clock mcl k main clock divider pllcr . pds ccpsdivr . pods ccpsdivr . sods ccpllfbr . idiv ccssfbr 0 ccssfbr1 ccssccr0 ccssccr1 cccgrcr1 cccgrcr 2 cccgrcr0 clock gear sscg enable pll enable sscgclk sscg clock icr 30 interrupt pll timer cselr . pllcr . mb91590 series mn705-00009-3v0-e 152
chapter 5: clock 3 . configuration fujitsu semiconductor limited c hapter : clock fujitsu semiconductor confidential 7 figure 3-4 connection diagram of clock (2) source clock s election unit figure 3-5 connection diagram of clock (3) divider control peripheral clock (pclk2) source clock (srcclk) base clock pll clock (pllclk) * non spread clock (divr0 . divb) 1/1 to 1/ 8 cloc k divider control uni t peripheral clock divider control unit picd . pdiv 1/1 to 1/16 peripheral clock (pclk1) (divr2 . divp) 1/1 to 1/16 external bus clock (tclk) (divr1 . divt) 1/1 to 1/ 8 on chip bus clock (hclk) 1 cpu clock (cclk) 1 (sacr . m) selector divider ( 1/2) mclk 2/pll s sclk/sbclk source clock clock select ion contro l cselr . cks cmonr . ckm 00 01 01 11 pllssclk pll/sscg cloc k sbclk sub clock mclk main clock mclk 2 main clock 2 division mb91590 series mn705-00009-3v0-e 153
chapter 5: clock 3 . configuration fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 8 figure 3-6 connection diagram of clock (4) ca n p rescaler cl ock generat ion figure 3-7 connection diagram of cloc k (5) gdc clock generation on chip bus clock (hclk) can prescaler clock pll clock (pllclk) * non spread clock 1 0 can prescaler clock selection unit pll/sscg oscillation enables (cselr:pcen) pll timer gpllcr . g_pcrdy ptimcr gpllcr . g_ pcen sscg - pll pll ( non - sscg ) divider divider gsscgclk gdc sscg c lock gpllclk gdc pll clock mclk ma i n clock pedivcr . pods pedivcr . sods pdivcr sdivcr 0 sdivcr 1 ssscr 0 ssscr 1 sgrcr 1 sgrcr 0 clock gear sscg enable pll enable pgrcr 1 pgrcr 0 clock gear pgrcr 2 sgrcr 2 mb91590 series mn705-00009-3v0-e 154
chapter 5: clock 3 . configuration fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 9 figure 3-8 connection diagram of clock (6) watch/power management clock generation figure 3-9 diagram of the clock system from master to slave from master to slave camera pixel fifo line buffer sprite engine command decoder display controller bus bridge line engine frame buffer video capture ntsc decoder adc c la mp i/o ( digital rgb) i/o ram sig rld dma external bus pin (for gdc external memory) rd y, a 00 - 24 , be 0x, be 1x w ex ,r ex , cs0x,cs1x, d0-15 i/o (ext. bus) ext. bus external lcd fr 81 s c pu core regulator power-on reset cr oscillator instruction mpu data d ebug i nterface xbs cross ba r s wi tch xbs on chip bus ram flash main flash workflash 64kb ram ec c control ( xbs -ram) can (3ch) bus bridge ext.bus i/f ram ecc control backup -ram can prescaler rtc/wdt1 calibration i/o port setting lin-uart (6ch) free-run timer (2ch) multi-function serial interface (2ch) input capture (6ch) output compare(4ch) base-timer (2ch) pp g ( 24 ch) a /d converter gd c external control stepping motor controller ( 6ch) reload timer (4ch) watchdog timer (sw and hw) generation and clear of dma transfer request interrupt request batch read interrupt controller delay interrupt rstx nmix wo t clock control (clock setting, main timer, sub timer, pll timer) low-voltage detection (ext. power supply low-voltage detection) low-voltage detection (int. power supply low-voltage detection) nmi clock supervisor real time clock external interrupt input ( 16 ch) bus bridge ( 32 -bit 16 -bit) sound generator (5ch) cr c 16-bit peripheral bus 16-bit peripheral bus 32-bit peripheral bus peripheral bus bridge operation mode register bus performance counter dmac bus master regi ster on chip bus layer 2 on chip bus layer 1 i/o port ca nr x0-2, cantx0-2 m d0 ,m d1 ,m d2 ,p 12 7 s go 0-4,sga0-4 int0- 15 , input interception inhibiting signal sot2-7 ,sin2-7, sck2-7 sot0-1,sin0-1, sck0-1 i cu 0-5 o cu 0-3 t io a0-1, t io b0-1 trg0-5, pp g0-23 adt g, an0-31 pwm1m0-5, pwm1p0-5, pwm2m0-5 tin0-3,tot0-3 f rc k0-1 wild register 16 32 i/o port external flash memory (for video) ahb bus bri dge a synchro nous type clock control (divide setting), reset control, low-power consumption control asynchronous bus bridge (pclk1 ? pclk2) asynchronous bus bridge (pclk1 ? pclk2) mclk (pmuclk) pmu clock 0 1 ccrt selr : csc sbclk (watclk) rtc clock ccpmucr0 : fdiv ccpmucr1 : gdiv 0 1 main clock (128 to 512 division ) divider (f divider) pmu clock (1 to 32division ) divider ( gdivider ) cpu clock(cclk) on - chip bus clock peripheral clock(pclk2) peripheral clock(pclk1) gdc pll clock(gpllclk) gdc sscg clock (gsscgclk) can prescaler clock external bus clock main clock rtc clock cr oscillator ocd clock gdc external clock clock supervisor ( main clock and cr oscillation ) external bus pin (for gdc external memory) rdy,a00 -24, wex,rex, cs0x ,cs1x, d0 - 15 mb91590 series mn705-00009-3v0-e 155
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 10 4. registers this section explains registers of the clock. table 4-1 registers map address registers r egister function +0 +1 +2 +3 0x0488 divr0 divr1 divr2 reserved division configuration register 0 division configuration register 1 division configuration register 2 0x0510 cselr cmonr mtmcr stm cr clock source configuration register clock source monitor register main timer control register sub timer control register 0x0514 pllcr cstbr ptmcr pll setting register oscillation stabilization wait setting register pll clock oscillation stabilization w ait timer control register 0x0520 ccpsselr reserved reserved ccpsdivr pll/sscg clock selection register pll/sscg output clock division setting register 0x0524 reserved ccpllfbr ccssfbr0 ccssfbr1 pll feedback division setting register sscg feedback divisi on setting register 0 sscg feedback division setting register 1 0x0528 reserved ccssccr0 ccssccr1 sscg configuration setting register 0 sscg configuration setting register 1 0x052c reserved cccgrcr0 cccgrcr1 cccgrcr2 clock gear configuration setting regi ster 0 clock gear configuration setting register 1 clock gear configuration setting register 2 0x0530 ccrtselr reserved ccpmucr0 ccpmucr1 rtc/pmu clock selection register pmu clock division register 0 pmu clock division register 1 0x0534 reserved reserve d reserved reserved reserved 0x0538 reserved reserved reserved reserved reserved 0x053c reserved reserved reserved reserved reserved 0x0f50 reserved gpllcr ptimcr pedivcr gdc pll control register gdc pll timer setting register gdc pll external division setting register 0x0f54 reserved pdivcr sdivcr0 sdivcr1 gdc pll multiply setting register gdc pll_sscg multiply setting register 0 gdc pll_sscg multiply setting register 1 mb91590 series mn705-00009-3v0-e 156
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 11 address registers r egister function +0 +1 +2 +3 0x0f58 reserved ssscr0 ssscr1 gdc pll_sscg spread spectrum setting register 0 gdc pll_sscg spread spectrum setting register 1 0x0f5c reserved pgrcr0 pgrcr1 pgrcr2 gdc pll clock gear setting register 0 gdc pll clock gear setting register 1 gdc pll clock gear setting register 2 0x0f60 reserved sgrcr0 sgrcr1 sgrcr2 gdc pll_sscg clock gea r setting register 0 gdc pll_sscg clock gear setting register 1 gdc pll_sscg clock gear setting register 2 0x1000 sacr picd reserved reserved sync/async control register peripheral interface clock divider mb91590 series mn705-00009-3v0-e 157
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 12 4.1. division configuration register 0 : divr0 ( divisi on clock configuration register 0) the bit configuration of the division c onfiguration r egister 0 is shown . this register controls division of clocks. ? divr0 : address 0488 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 divb[2 :0] reserved initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w [b it7 to bit 5 ] divb[2:0] ( division ratio of baseclock) : base clock division setting these bits configure a division in the area where the base clock is generated from the source clock (srcclk) as follows. the cpu clock (cclk) and the on- chip bus clock (hclk) have the same frequency as that of the base clock. divb[2:0] division ratio 000 do not divide ( initial value ) 001 2 division 010 3 division 011 4 division 10 0 5 division 101 6 division 110 7 division 111 8 division [ bit4 to bit0 ] ( reserved ) mb91590 series mn705-00009-3v0-e 158
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 13 4.2. division c onfiguration register 1 : divr1 (division clock configuration register 1) the bit configuration of the division c onfiguration r egister 1 is shown . this regis ter controls division of clocks . ? divr1 : address 0489 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tstp divt[2:0] reserved initial value 0 0 0 1 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w [ bit7 ] tstp (tclk stop) : external bus clock stop enable this bit configures whether to stop the external bus clock (tclk) when going into sleep mode. tstp tclk in sleep mode 0 do not stop ( initial value ) 1 stop [b it6 to bit 4 ] divt[2:0] (divide ratio of tclk) : external bus clock division setting these bits configure the division ratio when generating the external bus clock (tclk) from the base clock. divt[2:0] base clock tclk division ratio 000 do not divide 001 2 division ( initial value ) 010 3 division 011 4 division 100 5 division 101 6 division 110 7 division 111 8 division note: set this register so that the external bus clock (tclk) definitely becomes 40mhz or less. [ bit 3 to bit0 ] ( reserved ) mb91590 series mn705-00009-3v0-e 159
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 14 4.3. division c onfiguration register 2 : divr2 (division clock configu ration register 2) the bit configuration of the division c onfiguration r egister 2 is shown . this register controls division of clocks . ? divr2 : address 048a h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 divp[3:0] reserved in itial value 0 0 1 1 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w [b it7 to bit 4 ] divp[3:0] ( division ratio of pclk) : peripheral clock division setting these bits configure the division ratio when generating the peripheral clock (pclk 1 ) from the base clock. divp[3:0] base clock pclk 1 division ratio 0000 do not divide 0001 2 division 0010 3 division 0011 4 division ( initial value ) 0100 5 division 0101 6 division 0110 7 division 0111 8 division 1000 9 division 1001 10 division 1010 11 division 1011 12 division 1100 1 3 division 1101 14 division 1110 15 division 1111 16 division note: set this register to peripheral clock (pclk 1 ) to be sure to become 40mhz or less. [ bit 3 to bit0 ] ( reserved ) mb91590 series mn705-00009-3v0-e 160
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 15 4.4. clock source selection register : cselr (clock source selection register) the bit configuration of the clock source select ion r egister is shown . this register selects a control and a source clock (srcclk) for each clock source. note: the value set for this register and the value read out from this register are not actually co ntrolled and selected. you can make sure that the value set for this register would really take effect by reading out cmonr. after making sure that the value of this register is the same as that of cmonr, rewrite the register. while switching clocks is in progress (cks[1:0] ckm[1:0]), a write operation to this register will be ignored. ? cselr : address 0510 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scen pcen mcen reserved cks[1:0] initial value * 0 1 0 0 0 0 0 attribute r,w r,w r,w r0, wx r0,wx r0,wx r,w r,w *: this bit is initialized to ?0? . but this bit is not initialized by the return from the watch mode (power shut - down ). [b it7 ] scen (sub clock enable) : sub clock oscillation enable this bit controls an oscillation circuit for sub clock (sbclk) as follows . scen oscillation control for sub clock 0 stop oscillation ( initial value ) 1 oscillate this bit cannot be rewritten when a sub clock (sbclk) is selected as the source clock (srcclk) . the o scillation circuit for sub clock alway s stops in stop mode regardless of the value of this bit. the s ub timer is cleared when this bit is set to "0". for a single clock product, this bit always reads "0" and therefore a write operation would not be affected. note: it takes main clock about 3 cycles + sub clock about 3 cycles until the switch operation of rtc and pmu clock completes after rewriting the csc bit . when main clock and sub clock oscillation are stopped during the switching operation, the switching operation does not complete co rrectly. the oscillation must always be stooped in the status that the cst bit is "0" (the status of the completion of switching. the csc bit is not initialized by the return from the standby watch mode (power shut - down). moreover, any reset factors other than those, caused by power on reset/internal low voltage reset/rstx - nmix simultaneous assertion, can not be accepted because an internal reset signal is generated while returning from the standby watch mode (power shut - down). at this time the csc bit is not initialized. initialize this bit in case of need, when the reset signal comes from rstx terminal input or external low - voltage detection is flagged after the return from power shut - down. mb91590 series mn705-00009-3v0-e 161
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 16 [ bit6 ] pcen (pll clock enable) : pll oscillation enable this bi t controls the pll /sscg clock oscillation circuit as follows . pcen oscillation control for pll / ss cg clock (pll ss clk) 0 stop oscillation ( initial value ) 1 oscillate this bit cannot be rewritten when a pll /sscg clock (pll ss clk) is selected as the source clock (srcclk) . also, this bit cannot be rewritten when the main clock oscillation is stopped or during the main clock oscillation stabilization wait time (cmonr . mcrdy=0). set this bit to "0" before switching to the stop mode. rewriting the mcen bit with "0" causes this bit to set to "0". note: pll enters the stat us of the oscillation enable regardless of the value of this bit while communicating the mdi in high - speed. [ bit5 ] mcen (main clock enable) : ma in clock oscillation enable this bit controls an oscillation circuit for main clock as follows. mcen oscillation control for main clock 0 stop oscillation 1 oscillate ( initial value ) this bit cannot be rewritten when a main clock (mclk) or pll /sscg clock (pll ss clk) is selected as the source clock ( srcclk ). the o scillation circuit for main clock always stops in stop mode regardless of the value of this bit. the m ain timer is cleared when this bit is set to "0". no te: the m ain clock enters the stat us of the oscillation enable regardless of the value of this bit while communicating the mdi in low - speed. [b it4 to bit 2 ] ( reserved ) [b it1 , bit 0 ] cks[1:0] (clock select) : source clock select tion these bits select the source clock (srcclk) as follows . cks [1:0] source select ion 00 division of the m ain cloc k (mclk) by 2 ( initial value ) 01 division of the main clock (mclk) by 2 10 pll /sscg clock (pll ss clk) 11 sub clock (sbclk) mb91590 series mn705-00009-3v0-e 162
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 17 however, when cks[1:0] ckm[1:0], these bits cannot be rewritten. when the clock oscillation which you are trying to switch operations by these bits stops or is waiting for a stabilization (cmonr:xcrdy=0), this bit cannot also be rewritten. a direct switch from pll /sscg clock ( pll ss clk) to the sub clock (sbclk) or vice versa cannot be performed. possible combinations for changing these bits are shown below. cks value before change eligible values rewritten conditions ineligible values 00 00, 01 mcrdy=1 11 10 pcrdy=1 01 00, 01 mcrdy=1 10 11 scrdy=1 10 00 mcrdy=1 01,11 10 pcrdy=1 11 01 mcrdy=1 00,10 11 scrdy=1 do not write the values which cannot be rewritten. mb91590 series mn705-00009-3v0-e 163
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 18 4.5. clock source mo nitor register : cmonr (clock source monitor register) the bit configuration of the clock s ource m o nitor r egister is shown . this register displays a stat us and a source clock (srcclk) for each clock source. you can confirm that the value set at cselr is really reflected in the actual stat us by reading this register. note: if you have changed cselr, do not write next value on cselr until cmonr is equal to cselr. ? cmonr : address 0511 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scrdy pcrdy mcrdy reserved ckm[1:0] initial value * 0 1 0 0 0 0 0 attribute r,wx r,wx r,wx r0,wx r0,wx r0,wx r,wx r,wx *: this bit is initialized to ?0? . but this bit is not initialized by the return from the watch mode (power shut - down ). [ bit7 ] scrdy (sub clock ready) : sub clock ready this bit shows the sub clock (sbclk) stat us as follo ws. scrdy sub clock (sbclk) stat us 0 oscillation stops or in the oscillation stabilization wait stat us . 1 it is in the oscillation stabilization stat us and available for the source clock. this bit cannot select a sub clock (sbclk) as the source clock (srcclk) when this bit is set to "0". note: scrdy=1 may be read immediately after changing scen=1 to 0. [ bit6 ] pcrdy (pll clock ready) : pll clock ready this bit shows the pll /sscg clock (pll ss clk) stat us as follows . pcrdy pll /sscg clock (pll ss clk) sta t us 0 oscillation stops or in the oscillation stabilization wait stat us . 1 it is in the oscillation stabilization stat us and available for the source clock. this bit cannot select a pll /sscg clock (pll ss clk) as the source clock (srcclk) when this bit i s set to "0". mb91590 series mn705-00009-3v0-e 164
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 19 note: pcrdy=1 may be read immediately after changing pcen=1 to 0. pll enters the stat us of the oscillation enable regardless of the value of this bit while communicating the mdi in high - speed. [ bit5 ] mcrdy (main clock ready) : main clock r eady this bit shows the main clock (mclk) stat us as follows. mcrdy main clock (mclk) stat us 0 oscillation stops or in the oscillation stabilization wait stat us . 1 it is in the oscillation stabilization stat us and available for the source clock. this bi t cannot select a main clock (mclk) or a pll /sscg clock (pll ss clk) as the source clock (srcclk) when this bit is set to "0". the i nit ial value of "1" for this bit means that it is oscillation stabilized at the first reset vector fetch after power - on reset, not that it is already oscillation stabilized immediately after power - on reset. note: mcrdy=1 may be read immediately after changing mcen=1 to 0. the m ain clock enters the stat us of the oscillation enable regardless of the value of this bit while communi cating the mdi in high - speed. [b it4 to bit 2 ] ( reserved ) [b it1 , bit 0 ] ckm[1:0] (clock monitor) : source clock display these bits show the source clock (srcclk) currently selected . ckm[1:0] source selection 00 division of main clock (mclk) by 2 01 divis ion of main clock (mclk) by 2 10 pll /sscg clock (pll ss clk) 11 sub clock (sbclk) mb91590 series mn705-00009-3v0-e 165
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 20 4.6. main timer control register : mtmcr (main clock timer control register) the bit configuration of the main timer control r egister is shown . this register controls the main ti mer which runs with the main clock (mclk). ? mtmcr : address 0512 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mtif mtie mtc mte mts[3:0] initial value 0 0 0 0 1 1 1 1 attribute r(rm1),w r/w r(rm0),w r/w r1,wx r/w r/w r/w because the main timer is used for generating the oscillation stabilization wait time for main clock (mclk), it can be used only after the main clock oscillation is stabilized. the m ain timer is cleared when the main clock oscillation stops (mcen=0) or i t is in the stop mode. when the operation of the main timer is not allowed (mte=0), the main timer stops except that it is waiting for a main clock oscillation stabilization. the write operation to this register becomes enabled only when mcrdy=1 except for mtie. thus a main timer clear executed by mtc=1 in main clock oscillation stabilization wait stat us (mcen=1 and mcrdy=0) is not effective. when the main timer stops (mte=0) it will be cleared and while being cleared mtc=1 will be read out. at that time th e main timer interrupt flag (mtif) is not set. the main timer overflow period (mts[3:0]) should be changed at the time when the main timer stops (mte=0). when rewriting mte=1 with 0, the main timer will continue to operate until the mtc bit is set to "0" . in this interval, the main timer interrupt flag may turn to "1". when writing mtc=1, the main timer will continue to operate until the mtc bit is set to "0" . in this interval, the main timer interrupt flag may turn to "1". if a mte=0 to 1 rewrite and a mtc=1 write occur at the same time, the operation starts after a clear takes place, so the start will be delayed. [ bit7 ] mtif (main clock timer interrupt flag) : main timer interrupt flag the flag to indicate that an overflow happens in the interval for which the main timer has selected. when the mtie bit is "1" and this bit is set, a main timer interrupt request is generated. clear factor ? " 0 " write ? a dma transfer is generated by the main timer interrupt. set factor ? an overflow occurred in the interval set by mts[3:0] ? the end of oscillation stabilization wait time of the main clock after setting mcen=0 to 1. ? the end of oscillation stabilization wait time of the main clock (mclk) after exiting the stop mode. (a set will not take place at the end of oscillation stabilization wait time after reset by sinit.) writing "1" to this bit is ineffective. when the mtie bit is set to "0", this bit will not be cleared by dma transfer. for read - modify - write instructions, "1" will be read out. if a set factor and a clear factor occur at the same time, the set factor will take precedence. mb91590 series mn705-00009-3v0-e 166
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 21 [ bit6 ] mtie (main clock timer interrupt enable) : main timer interrupt enable d this bit controls interrupts by main timer overflow as follows. mtie main timer interrupt 0 interrupt disab led ( initial value ) 1 interrupt enabled (outputs the interrupt request at the time when the mtif bit is "1") [ bit5 ] mtc (main clock timer clear) : main timer clear this bit clears the main timer. mtc write 0 does nothing. 1 clear the main timer. m tc read 0 operating normally 1 clearing the main timer this bit automatically returns to "0" after writing "1". for read - modify - write instructions, "0" will be read out. when writing mtc=1 at the time of mtc=1, the second write will be ignored . [ bit4 ] m te (main clock timer enable) : main timer operation enable this bit controls the operation of the main timer as follows. mte main timer operation 0 operation disabled ( initial value ) 1 operation enabled at the time of mtc=1, mte=1 write is prohibited. when you perform a pll /sscg clock oscillation stabilization wait, make sure to set this bit to "0" and stop the main timer. [b it3 to bit 0 ] m ts[3:0] (main clock timer interval selection ) : main timer interval selection these bits select the overflow interval of the main timer as follows . mts[3:0] main timer overflow interval at 4mhz 1000 2 9 main clock cycle 128.0[ s] 1001 2 10 main clock cycle 256.0[ s] 1010 2 11 main clock cycle 512.0[ s] 1011 2 12 main clock cycle 1024.0[ s] 1100 2 13 main clock cycle 2048.0[ s] 1101 2 14 main clock cycle 4096.0[ s] 1110 2 15 main clock cycle 8192.0[ s] 1111 2 16 main c lock cycle ( initial value ) 16384.0[ s] t he mts3 bit always reads "1". change mts[3:0] at the time when the main timer stops (mte=0). mb91590 series mn705-00009-3v0-e 167
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 22 4.7. sub timer control register : stmcr (sub clock timer control register) the bit configuration of the sub timer control r egi ster is shown . this register controls the sub timer which runs with the sub clock. ? stmcr : address 0513 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stif stie stc ste reserved sts[2:0] initial value 0 0 0 0 0 1 1 1 attribute r(rm1),w r/w r(rm0),w r/w r0,wx r/w r/w r/w because the sub timer is used for generating the oscillation stabilization wait time for the sub clock (sbclk), it can be used only after the sub clock oscillation is stabilized. the s ub timer is cleared whe n the sub clock oscillation stops (scen=0) or it is in the the stop mode. when the operation of the sub timer is not allowed (ste=0), the sub timer stops except that it is waiting for a sub clock oscillation stabilization. the write operation to this regis ter becomes enabled only when scrdy=1 except for stie. thus a sub timer clear executed by stc=1 in sub clock oscillation stabilization wait stat us (scen=1 and scrdy=0) is not effective. when the sub timer stops (ste=0) it will be cleared and while being cl eared stc=1 will be read out. at that time the sub timer interrupt flag is not set. the sub timer overflow period (sts[2:0]) should be changed at the time when the sub timer stops (ste=0). when rewriting ste=1 with 0, the sub timer will continue to operate until stc is set to "0" . in this interval, the sub timer interrupt flag may turn to "1". when writing stc=1, the sub timer will continue to operate until stc is set to "0" . in this interval, the sub timer interrupt flag may turn to "1". if a ste=0 to 1 re write and a stc=1 write occur at the same time, the operation starts after a clear takes place, so the start will be delayed. [ bit7 ] stif (sub clock timer interrupt flag) : sub timer interrupt flag the flag to indicate that an overflow happens in the interval for which the sub timer has selected. when the stie bit is "1" and this bit is set, a sub timer interrupt request is generated. clear factor ? "0" write ? a dma transfer is generated by the sub timer interrupt. set factor ? an overflow occurred in the inter val set by sts[2:0]. ? the end of oscillation stabilization wait time of the sub clock after setting scen=0 to 1. ? the ends of oscillation stabilization wait time of the sub clock after exiting the stop mode. writing "1" to this bit is ineffective. when t he stie bit is set to "0", this bit will not be cleared by dma transfer. for read - modify - write instructions, "1" will be read out. if a set factor and a clear factor occur at the same time, the set factor will take precedence. mb91590 series mn705-00009-3v0-e 168
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 23 [ bit6 ] stie (sub clock time r interrupt enable) : sub timer interrupt enable this bit controls interrupts by sub timer overflow as follows. stie sub timer interrupt 0 interrupt disabled ( initial value ) 1 interrupt enabled (output the interrupt request at the time stif bit is "1") [ bit5 ] stc (sub clock timer clear) : sub timer clear this bit clears the sub timer. stc write 0 does nothing. 1 clear the sub timer . stc read 0 operating normally 1 clearing the sub timer this bit automatically returns to "0" after writing "1". for read - modify - write instructions, "0" will be read out. when writing stc=1 at the time of stc=1, the second write will be ignored. [ bit4 ] ste (sub clock timer enable) : sub timer operation enabled this bit controls the operation of the sub timer as follows. ste sub timer operation 0 operation disabled ( initial value ) 1 operation en abled at the time of stc=1, ste=1 write is prohibited. [ bit3 ] ( reserved ) [b it2 to bit 0 ] sts[2:0] (sub clock timer interval selection ) : sub timer interval selection these bits select the overflow interval of the sub timer as follows. sts[2:0] sub timer overflow interval at 3 2 khz 000 2 8 sub clock cycle 8[ms] 001 2 9 sub clock cycle 16[ms] 010 2 10 sub clock cycle 32 [ms] 011 2 11 sub clock cycle 64 [ms] 100 2 12 sub clock c ycle 1 28 [ms] 101 2 13 sub clock cycle 0.25 6 [s] 110 2 14 sub clock cycle 0.5 12 [s] 111 2 15 sub clock cycle ( initial value ) 1 .024 [s] mb91590 series mn705-00009-3v0-e 169
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 24 4.8. pll setting register : pllcr (pll configuration register) the bit configuration of the pll setting r egister is shown . thi s register configures the multiplication rate or division ratio in the pll /sscg clock oscillation circuit and the oscillation stabilization wait time. ? pllcr : address 0514 h ( access : byte , half - word , word ) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved reserved reserved initial value 0 0 0 0 0 0 0 0 attribute r 0 ,w 0 r 0 ,w 0 r0,wx r 0 ,w 0 r 0 ,w 0 r 0 ,w 0 r 0 ,w 0 r 0 ,w 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 posw[3:0] pds[3:0] initial value 1 1 1 1 0 0 0 0 attribute r1,wx r,w r,w r,w r,w r,w r,w r ,w this register configures the parameter s in the pll /sscg clock oscillation circuit generating the pll /sscg clock (pll ss clk) from the main clock (mclk). when pll/sscg clock oscillation is allowed (cselr:pcen=1), writing to this register will be disabled . [b it15 , bit 14] reserved always write "0". [b it13 ] ( reserved ) [b it12 to bit 8 ] reserved always write "0". mb91590 series mn705-00009-3v0-e 170
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 25 [b it7 to bit 4] posw[3:0] (pll clock clock osc wait) : pll clock oscillation stabilization wait selection these bits select the oscillation stabiliz ation wait time for the pll /sscg clock (pll ss clk) as follows. posw[3:0] pll /sscg clock oscillation stabilization wait time at 4mhz at 8mhz 1000 2 9 main clock cycle 128.0[ s] 64 .0[ s] 1001 2 10 main clock cycle 256.0[ s] 128.0[ s] 1010 2 11 main clock cycle 512.0[ s] 256.0[ s] 1011 2 12 main clock cycle 1024.0[ s] 512.0[ s] 1100 2 13 main clock cycle 2048.0[ s] 1024.0[ s] 1101 2 14 main clock cycle 4096.0[ s] 2048.0[ s] 1110 2 15 main clock cycle 8192.0[ s] 4096.0[ s] 1111 2 16 main clock c ycle ( initial value ) 16384.0[ s] 8192.0[ s] posw3 always reads "1". note: t he pll/sscg c lock oscillation stabilization wait time specification in this model is 2 00[ s]. reserve the 2 00[ s] wait time or more by either of the following methods. ? select 256 [ s] posw[3:0] or more . ? reserve the 2 00[ s] wait time or more by software processing, regardless of posw[3:0] settings . mb91590 series mn705-00009-3v0-e 171
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 26 [b it3 to bit 0 ] pds[3:0] (pll input clock divider selection ) : pll input clock divider selection these bits select the main clock (mclk ) division for the pll /sscg input clock as follows. pds[3:0] pll/sscg input clock divider select 0000 pll/sscg input clock = main clock / 1 0001 pll/sscg input clock = main clock / 2 0010 pll/sscg input clock = main clock / 3 0011 pll/sscg input clock = main clock / 4 0100 pll/sscg input clock = main clock / 5 0101 pll/sscg input clock = main clock / 6 0110 pll/sscg input clock = main clock / 7 0111 pll/sscg input clock = main clock / 8 1000 pll/sscg input clock = main clock / 9 1001 pll/sscg inp ut clock = main clock / 10 1010 pll/sscg input clock = main clock / 11 1011 pll/sscg input clock = main clock / 12 1100 pll/sscg input clock = main clock / 13 1101 pll/sscg input clock = main clock / 14 1110 pll/sscg input clock = main clock / 15 111 1 pll/sscg input clock = main clock / 16 * follow the configuration steps for your appropriate pll/sscg and system specifications. * see " 5.1.3 pll/sscg clock ( pllssclk ) " for configuration samples. a set value is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 172
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 27 4.9. clock stabilization selection register : cstbr (clock stabilization selection register) the bit configuration of the oscillation stabilization select ion re gister is shown . this register configures the oscillation stabilization wait for each clock source. the o scillation stabilization wait time set by this register will be used at the time when returning from th e stop/watch mode. it will also be used for a period from the time when the oscillation of a clock which have not been selected as the source clock is allowed until the ready stat us (cmonr: * crdy) of that clock switches to "1". if an oscillation stabilizati on wait is ne c es s ary at reset, it will always be set to the stabilization wait time selected as an initial value by this register. write operations to mosw[3:0] will not be effective at the main clock oscillation stabilization wait time (mcen=1 and mcrdy=0 ). write operations to sosw[2:0] will not be effective at the sub clock oscillation stabilization wait time (scen=1 and scrdy=0). ? cstbr : address 0516 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sosw[2:0] mosw[3:0 ] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r,w r,w r,w r,w r,w r,w r,w [b it7 ] ( reserved ) [b it6 to bit 4 ] : sosw[2:0] (sub clock osc wait) : sub clo ck oscillation stabilization wait s election these bits select the oscillation stabilization wait tim e for the sub clock (sbclk) as follows . sosw[2:0] sub clock oscillation stabilization wait time at 32 khz 000 2 8 sub clock cycle ( initial value ) 8[ms] 001 2 9 sub clock cycle 1 6[ms] 010 2 10 sub clock cycle 32 [ms] 011 2 11 sub clock cycle 64 [ms] 1 00 2 12 sub clock cycle 128 [ms] 101 2 13 sub clock cycle 0.25 6 [s] 110 2 14 sub clock cycle 0.5 12 [s] 111 2 15 sub clock cycle 1 .024 [s] mb91590 series mn705-00009-3v0-e 173
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 28 [b it3 to bit 0 ] mosw[3:0] (main clock osc wait) : main clo ck oscillation stabilization wait s election the main ti mer interval is set by the set value for mosw[3:0]. these bits select the oscillation stabilization wait time for the main clock (mclk) as follows. mosw[3:0] main clock oscillation stabilization wait time at 4mhz 0000 2 15 main clock cycle ( initial valu e ) 8[ms] 0001 2 1 main clock cycle 500[ns] 0010 2 5 main clock cycle 8[ s] 0011 2 6 main clock cycle 16[ s] 0100 2 7 main clock cycle 32[ s] 0101 2 8 main clock cycle 64[ s] 0110 2 9 main clock cycle 128[ s] 0111 2 10 main clock cycle 256[ s] 1000 2 11 main clock cycle 512[ s] 1001 2 12 main clock cycle 1[ms] 1010 2 13 main clock cycle 2[ms] 1011 2 14 main clock cycle 4[ms] 1100 2 17 main clock cycle 33[ms] 1101 2 19 main clock cycle 131[ms] 1110 2 21 main clock cycle 524[ms] 1111 2 23 main clock cycle 2[s] note: note that the determination detection is done while waiting for the oscillation stability when the cycle of the determination detection is shorter than a set cycle of this register when the clock supervisor function is effective. mb91590 series mn705-00009-3v0-e 174
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 29 4.10. pll clock osci l lation timer c on trol register : ptmcr (pll clock osc timer control register) the bit configuration of the pll clock oscil l ation timer c ontrol r egister is shown . the timer that works with the main clock that does pll /sscg clock oscillation stabilization wait is controlled. the pll /sscg clock oscillation stabiliza tion wait timer is used only at the oscillation stabilization wait time of the pll /sscg clock (pllssclk) . the pll /sscg clock oscillation stabilization wait time becomes time set by pllcr:posw[3:0]. when pll/sscg clock oscillation is enabled(cselr.pcen=1), pll/sscg clock stabilization timer starts couting up. after the oscilation stabilization time elapses, pll/sscg clock stabilization timer stops . moreover, when pll /sscg clock oscillation stop (cselr : pcen =0) is done, it is cleared. ? ptmcr : address 0517 h (a ccess : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ptif ptie reserved initial value 0 0 0 0 0 0 0 0 attribute r(rm1),w r/w r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] ptif (pll clock osc wait timer interrupt flag) : pll clock osc illation stabilization wait timer interrupt flag it is a flag that shows that the overflow at the time set by pll clock oscillation s tabilization wait selection (pllcr: posw [3:0] ) was generated. if this bit is set when the ptie bit is "1" , pll /sscg clock oscillation stabilization wait timer interrupt request is generated. clear factor ? "0" write ? generation of dma transfer with pll /sscg oscillation stabilization wait timer set factor ? end of the oscillation stabilization wait time for pll/sscg clock oscillat ion stabilization wait clock after pcen=0 1 the "1" writing in this bit is invalid. when the ptie bit is ?0', the clearness of this bit by the dma forwarding is not done. in the read modif y write instruction, "1" is read. the set factor is given priority when a set factor and a clear factor are generated at the same time. [b it6 ] ptie (pll clock osc wait timer interrupt enable) : pll clock oscillation stabilization wait timer interrupt enable the interrupt by the overflow of pll /sscg clock oscillation stabi lization wait timer is controlled as follows. ptie o p eration 0 interrupt disabled ( initial value ) 1 interrupt enabled (the interrupt request is output when the ptif bit is "1" .) [ bit 5 to bit0 ] ( reserved ) mb91590 series mn705-00009-3v0-e 175
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 30 4.11. pll/sscg c lock select ion register : ccpsselr (cctl pll/sscg clock selection register) the bit configuration of the pll/sscg clock select ion r egister is shown . it is a register that selects the clock source supplied to system . this register can be written only at pll /sscg clock oscillation stop (cselr :p cen = 0) . ? ccpsselr : address 0520 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pcsel initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r 0, w x r0,wx r0,wx r0,wx r0,wx r0,wx r / w [b it 7 to bit1] ( reserved ) [b it 0] pcsel (pll c lock source s election ) : pll /sscg clock source selection it selects the pll /sscg c lock source. pcsel pll or sscg 0 selects pll 1 selects sscg no te: sscg (because it is unused) always becomes a reset stat us for pcsel=0. the pll clock is supplied to can and ocdu for pcsel=1 . mb91590 series mn705-00009-3v0-e 176
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 31 4.12. pll/sscg output clock division setting register : ccpsdivr (cctl pll/sscg clock division register) the bit configuration of the pll/sscg output clock division setting r egister is shown . it is a register that sets the ratio of d ividing frequency of the pll/sscg clock. this register can be written only at pll /sscg clock oscillation stop (cselr : pcen = 0) . ? ccpsdivr : address 0523 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pods[2:0] reserved sods[2:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r / w r / w r / w r0,wx r / w r / w r / w [b it 7] ( reserved ) [b it6 to bit 4] pods [2:0] (pll oscillator divider selection ) : selection of pll macro oscillation clock dividing frequency ratio the ratio of divi ding frequency of the pll clock is set. pods [2:0] dividing frequency ratio setting 000 pll clock = pll macro oscillation clock /2 001 pll clock = pll macro oscillation clock /4 010 pll clock = pll macro oscillation clock /6 011 pll clock = pll macro os cillation clock /8 100 pll clock = pll macro oscillation clock /10 101 pll clock = pll macro oscillation clock /12 110 pll clock = pll macro oscillation clock /14 111 pll clock = pll macro oscillation clock /16 note: it is only dividing of the even number in the setting by this bit. the odd number dividing frequency cannot be set. duty of the output clock becomes 50%. please set for the pll clock to become 128mhz or less. (the operation guarantee that exceeds 128mhz is not done. ) [b it 3] ( reserved ) mb91590 series mn705-00009-3v0-e 177
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 32 [b it 2 to bit0] sods [2:0] (sscg oscillator divider selection ) : sscg selection of sscg macro oscillation clock dividing frequency ratio the ratio of dividing frequency of the sscg clock is set . sods [2:0] dividing frequency ratio setting 000 sscg clock = ss cg macro oscillation clock /2 001 sscg clock = sscg macro oscillation clock /4 010 sscg clock = sscg macro oscillation clock /6 011 sscg clock = sscg macro oscillation clock /8 100 sscg clock = sscg macro oscillation clock /10 101 sscg clock = sscg ma cro oscillation clock /12 110 sscg clock = sscg macro oscillation clock /14 111 sscg clock = sscg macro oscillation clock /16 note: it is only dividing of the even number in the setting by this bit. the odd number dividing frequency cannot be set. duty of the output clock becomes 50%. please set for the sscg clock to become 128mhz or less. (the operation guarantee that exceeds 128mhz is not done. ) a set value is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 178
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 33 4.13. pll feedback division setting register : ccpllfbr (cctl pll fb clock division register) the bit configuration of the pll feedback division setting r egister is shown . it is a register that sets the multiple ratio o f pll. this register can be written only at pll /sscg clock oscillation stop (cselr : pcen = 0) . ? ccpllfbr : address 0525 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved idiv[6:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r / w r / w r / w r / w r / w r / w r / w [b it 7] ( reserved ) [b it6 to bit0] idiv [6:0] (pll feedback input d iv ider ratio s e ttings) : setting of pll macro fb input dividing frequency ratio pll multiple rario is set. idiv [ 6 :0] dividing frequency ratio setting 000 0000 to 000 1011 setting is prohibited 0001100 13 0001101 14 000 1110 15 ? ?? 1100010 99 1100011 100 1100100 to 1111111 setting is prohibited a set value is limited. see " 5.1.4 limitations whe n pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 179
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 34 4.14. sscg feedback division setting register 0 : ccssfbr0 (cctl sscg fb clock division register 0) the bit configuration of the sscg feedback division setting r egister 0 is shown . it is a register that sets multiple r atio of sscg. the m ultiple ratio of sscg bec omes p n together with the setting of ccssfbr1. this register can be written only at pll /sscg clock oscillation stop (cselr : pcen = 0). ? ccssfbr0 : address 0526 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reserved ndiv[5:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r 0, w x r / w r / w r / w r / w r / w r / w [b it 7, bit6] ( reserved ) [b it 5 to bit0] ndiv [5:0] (sscg feedback input n-d iv ider ratio s e ttings) : sscg macro fb input n dividing frequency ratio setting it sets the sscg multiple ratio n. ndiv [ 5 :0] dividing frequency ratio setting 000000 setting is prohibited 000001 2 000010 3 000011 4 ? ?? 111101 62 111110 63 111111 setting is prohibited a set value is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 180
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : cl ock fujitsu semiconductor confidential 35 4.15. sscg feedback division setting register 1 : ccssfbr1 (cctl sscg fb clock division register 1) the bit configuration of the sscg feedback divi sion setting r egister 1 is shown . it is a register that sets the multipl e ratio p of sscg. the multiplication ratio of sscg becomes p n along with the setting of ccssfbr0. this register can be written only at pll /sscg clock oscillation stop (cselr . pcen = 0). ? ccssfbr 1 : address 0527 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pdiv[4:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r 0, w x r 0, w x r / w r / w r / w r / w r / w [b it 7 to bit5] ( reserved ) [b it 4 to bit0] pdiv [4:0] (sscg feedback input p-d iv ider ratio s e ttings) : sscg macro fb input p divider frequency ratio setting it sets the sscg multipl e ratio p. pdiv[4:0] dividing frequency ratio setting 00000 1 0 0001 2 00010 3 00011 4 ? ?? 11101 30 11110 31 11111 setting is prohibited a set value is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 181
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 36 4.16. sscg configuration setting register 0 : ccssccr0 (cctl sscg config. register 0) t he bit configuration of the sscg configuration setting r egister 0 is shown . sscg is variously set. this register can be written only at pll /sscg clock oscillation stop (cselr : pcen = 0) ? ccssccr0 : address 0529 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sfreq[1:0] smode ssen initial value 0 0 0 1 0 0 0 0 attribute r 0, w x r 0, w x r 0, w x r / w r / w r / w r / w r / w [b it 7 to bit4] ( reserved ) [b it 3 , bit2] sfreq [1:0] (spread s pectrum m odulation freq uency settings) : spread s pectrum m odulation frequency settings the spread s pectrum modulation frequency of sscg is set. sfreq [ 1 :0] modulation frequency 00 1/1024 01 1/2048 1x 1/4096 [b it 1] smode (spread s pectrum m odulation mode settings) : spread s pectrum m odulation mode setting s sets spread spectrum modulation mode of sscg. smode modulation mode 0 down spread 1 center spread ? down spread time target period modulation rate 1/modulation frequency c ycle to cycle jitter mb91590 series mn705-00009-3v0-e 182
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 37 ? center spread time target period modulation rate 1/modulation frequency c ycle to cycle jitter [b it 0] ssen (spread s pectrum enable) : spread s pectrum enable t his bit e nables supread spectrum of sscg. ssen spread s pect rum enable 0 s pread spectrum disabled 1 s pread spectrum enabled note: diffusivity of the spread spectrum become s 0% regardless of a setting of the ccssc c r1:ratesel when ssen is set disabled. mb91590 series mn705-00009-3v0-e 183
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 38 4.17. sscg configuration setting register 1 : ccssccr1 (cctl sscg config. register 1) the bit configuration of the sscg configuration setting r egister 1 is shown . sets various settings of sscg. this register can be written only when pll /sscg clock oscillation stops. (cselr:pcen = 0). ? ccssccr 1 : address 052a h ( access : ha lf - word , word ) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 ratesel [2:0] reserved initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r 0, w x r 0, w x r 0, w x r / w 0 r / w 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved initial value 0 0 0 0 0 0 0 0 attribute r / w 0 r / w 0 r / w 0 r / w 0 r / w 0 r / w 0 r / w 0 r / w 0 [b it 15 to bit13] ratesel [2:0] (spread s pectrum m odulation rate selection) : spread s pectrum m odulation rate selection sets the spread spectrum modulation rate of sscg. ratesel [ 2 :0] m odulation rate 00x 0.5% 010 1% 011 2% 100 3% 101 4% 110 5% 111 setting is prohibited [b it 12 to bit 1 0] ( reserved ) writing has no effect. [b it 9 to bit0] (reserved) always write "0" to these bits. mb91590 series mn705-00009-3v0-e 184
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 39 4.18. clock gear configuration setting register 0 : cccgrcr0 (cctl clock gear config. register 0 ) the bit configuration of the clock gear configuration setting r egister 0 is shown . sets various settings of clock gear . ? cccgrcr0 : address 052d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 grsts[1 :0 ] rese rved grstr gren initial value 0 0 0 0 0 0 0 0 attribute r , w x r , w x r 0, w x r 0, w x r 0, w x r 0, w x r (rm0), w 1 r / w [b it 7, bit6] grsts [1:0] (clock gear status flags) : clock gear status flags displays stat us of clock gear. grsts [1:0] status 00 stop in the state of clock gear low - speed oscillation or no use of clock gear (cccgrcr0 : gren=0) or in the stat us of pll /sscg reset (cselr : pcen=0) 01 in operation of gear up 10 stop in the stat us of clock gear high - speed oscillation 11 in operation of gear down [b it 5 to bit2] ( reserved ) [b it 1] grstr (clock gear start) : clock gear start writing "1" to this bit starts the operation of clock gear the operation of clock gear depends on the value of the grsts bits. ( gear up or gear down) when grsts =00 grstr operation "0" w rite not affect the operation "1" write start the operation of gear up when grsts =01/11 grstr operation "0" write not affect the operation "1" write not affect the operation mb91590 series mn705-00009-3v0-e 185
chapter 5: clock 4 . registe rs fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 40 when grsts =10 grstr operation "0" write not affect the operation "1" wri te start the operation of gear down note: this bit can be written only when cselr:cks [1:0] =10 (pll /sscg clock (pllssclk) selection) and cccgrcr0:gren=1 (clock gear enabled). this bit is automatically cleared to "0" after the operation of clock gear up (do wn) complete. also, this bit is cleared to "0" when cselr:pcen=0 (pll /sscg clock oscillat i on stopped). in the instruction of read modify write "0" is always read from this bit.when writing is executed while this bit is "1", writing for the second and subsequent times is ignored. [b it 0] gren (clock gear enable) : clock gear enable t his bit e nables the operation of clock gear. gren operation 0 no use of clock gear 1 use of clock gear note: this bit can be written only when pll /sscg clock oscillation is s topped (cselr:pcen = 0). mb91590 series mn705-00009-3v0-e 186
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 41 4.19. clock gear configuration setting register 1 : cccgrcr1 (cctl clock gear config. register 1) the bit configuration of the clock gear configuration setting r egister 1 is shown . sets various settings of clock gear. this register can be written only when pll /sscg clock oscillation is stopped (cselr:pcen = 0). ? cccgrcr 1 : address 052e h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 grst p [1:0 ] grstn [5:0] initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r / w r / w r / w [b it 7, bit6] grstp [1:0] (clock gear step selection ) : clock gear step selection these bits select the step number at the time of clock gear up/down (the number of increment /decrement) . grstp [1:0] step number 00 1 01 2 10 3 11 4 [b it 5 to bit0] grst n [5:0] (clock gear start step number selection ) : clock gear start step number selection these bits select the step at the start of clock gear operation and select the step between 0 and 63 . grstn [5:0] step number 000000 0 000001 1 0 00010 2 ? ?? 111101 61 111110 62 111111 63 note: the gear does not operate at grstn =111111(number 63 of steps) setting. mb91590 series mn705-00009-3v0-e 187
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 42 4.20. clock gear configuration setting register 2 : cccgrcr2 (cctl clock gear config. register 2) the bit configuration of the clock g ear configuration setting r egister 2 is shown . sets various settings of clock gear . this register can be written only when pll /sscg clock oscillation is stopped. (cselr:pcen = 0) . ? cccgrcr 2 : address 052f h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 gr lp [ 7:0 ] initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r / w r / w r / w [b it 7 to bit0] gr lp [7:0] (clock gear loop number selection ) : clock gear loop number selection t hese bits s elect the loop number of one step. t he setting enabled number of iteration is between 1 to 256. step is incremented/decremented when the number set to this bit is completed. grlp [7:0] loop number 0000_0000 1 0000_0001 2 0000_0010 3 ? ?? 1111_1101 254 1111_1110 255 1111_1111 256 mb91590 series mn705-00009-3v0-e 188
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 43 4.21. rtc/ pmu clock selection r egister : ccrtselr (cctl rtc pmu clock se lection register) the bit configuration of the rtc/pmu clock select ion r egister is shown . selects rtc/pmu clock source. ? ccrtselr : address 0530 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cst reserved csc initial value * 0 0 0 0 0 0 * attribute r , w x r 0, w x r 0, w x r 0, w x r 0, w x r 0, w x r 0, w x r / w *: these bits are initialized to ?0? . but these bit s are not initialized by the return from the watch mode (power shut - dow n ). [b it 7] cst ( clock source selection status monitor): clock source selection st atus monitor a time lag by clock switch occurs until the csc bit is written and then the clock switch completes. whether the switch completes or not is monitored by this bit. cst monitor 0 the completion of clock switch 1 during clock switch note: when single clock products (subdis=1), this bit is always fixed with "0". normally, switch completes by main clock about 3 cycles + sub clock about 3 cycles. [b it 6 to bit1] ( reserved ) [b it 0] csc (clock source selection ) : clock source selection selects clock source of rtc/pmu clock. csc clock source 0 main oscillation clock 1 sub oscillation clock note: the csc bit can be rewritten only when scrdy=1 and mcrdy=1. when sing le clock products , this bit is always fixed with "0" in spite of the written value. mb91590 series mn705-00009-3v0-e 189
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 44 note: it takes main clock about 3 cycle s + sub clock about 3 cycle s until the switch operation of rtc and pmu clock completes after rewriting the csc bit . when main clock and sub clock oscillation are stopped during the switching operation, the switching operation does not complete correctly. the oscillation must always be stooped in the stat us that the cst bit is "0" (the stat us of the completion of switching. the csc bit is not initialized by the return from the standby watch mode (power shut - down). moreover, any reset factors other than those, caused by power on reset/internal low voltage reset/rstx - nmix simultaneous assertion, can not be a ccepted because an intern al reset signal is generated w hile returning from the standby watch mode (power shut - down) . at this time the csc bit is not initialized. initialize this bit in case of need, when the reset signal comes from rstx terminal input or external low - voltage detection is flagged after the return from power shut - down. mb91590 series mn705-00009-3v0-e 190
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 45 4.22. pmu clock division setting register 0 : ccpmucr0 (cctl pmu clock division register 0) the bit configuration of the pmu clock division setting r egister 0 is shown . this register does the setting of div iding frequency of the pmu clock. . ? ccpmucr0 : address 0532 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 fst reserved fdiv [1:0] initial value 0 0 0 0 0 0 0 0 attribute r , w x r 0, w x r 0, w x r 0, w x r 0, w x r 0, w x r /w r / w [b it 7] fst (f - divider status monitor): f - divider status monitor a time lag by clock switch occurs until fdiv[1:0] register is written and the written value is reflected. whether the setting value is reflected can be monitored by this bit. normally, it takes rtc c lock about 4 cycle s + pclk 1 about 4 cycle s to reflect the setting value of the register . fst monitor 0 completion of reflecting the written value 1 during reflecting the w r itten value [b it 6 to bit2] ( reserved ) [b it 1 to bit0] fdiv [1:0] (f- divide ratio setting): f - divide ratio setting sets the division rate of f - divider. the clock less than 32khz must be provided with pmu. when c crtselr : csc=0 (selection of main oscillation clock), this bit is set to be less than 32khz by f divider. fdiv[1:0] d ivisio n rate target main oscillation frequency 00 divided by 128 ( initial value ) 4mhz 01 divided by 256 8mhz 10 divided by 384 12mhz 11 divided by 512 16mhz note: writing to this bit is ignored while the ccpmucr0:fst bit is "1". when ccrtselr:csc=1 (selection of sub oscillation clock), f - division rate become undivided in spite of the value of this bit. mb91590 series mn705-00009-3v0-e 191
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 46 4.23. pmu clock division setting register 1 : ccpmucr1 (cctl pmu clock division register 1) the bit configuration of the pmu clock division setting r egister 1 is shown . this register does the setting of divi ding frequency of the pmu clock . ? ccpmucr 1 : address 0533 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gst reserved g div [4:0] initial value 0 0 0 0 0 0 0 0 attribute r , w x r 0, w x r 0, w x r /w r / w r / w r /w r / w [b it 7] gst (g - divider status monitor): g - divider status monitor a time lag by clock switch occurs until gdiv[4:0] register is written and the written value is reflected. whether the setting value is reflected can be monitored b y this bit. normally, it takes rtc clock about 4 cycle s + pclk 1 about 4 cycle s to reflect the setting value of the register. gst monitor 0 completion of reflecting the written value 1 during reflecting the w r itten value note: writing to ccpmucr1:gdi v[4:0] is ignored while this bit is "1". [b it 6, bit5] ( reserved ) [b it 4 to bit0] gdiv [4:0] (g - divide ratio setting) : g - divide ratio setting t hese bits s et the division rate of g - divider. the period of the pmu clock must be more than four times the period of the bus clock (apb) which is provided with pmu. the division rate of the pmu clock is set by this divider to meet the above relation. gdiv[4:0] d ivision rate 00000 do not divide ( initial value ) 00001 2 00010 3 ? ?? 11101 30 11110 31 11111 32 mb91590 series mn705-00009-3v0-e 192
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 47 n ote: writing to this bit is ignored while ccpmucr1:gst bit is "1". mb91590 series mn705-00009-3v0-e 193
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 48 4.24. sync/async control r egister : sacr (sync/async control register) the bit configuration of the sync/async control r egister is shown . selects the peripheral clock (pclk2) . ? sacr : address 100 0 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved m initial value 1 1 1 1 1 1 1 0 attribute r 1, w x r 1, w x r 1, w x r 1, w x r 1, w x r 1, w x r 1, w x r / w [b it 7 to bit1] ( reserved ) [b it 0] m : synchronous/asynchronous setting reg ister of peripheral clock (pclk2) the peripheral clock (pclk2) is switched when cpu selects the sscg clock. m synchronous/asynchronous setting 0 synchronous ( pll/ sscg clock for cpu/peripheral ) 1 asynchronous ( pll/ sscg clock for cpu, pll clock for periphera l) mb91590 series mn705-00009-3v0-e 194
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clo ck fujitsu semiconductor confidential 49 4.25. peripheral interface clock divider : picd ( peripheral interface clock divider ) the bit configuration of peripheral interface clock divider is shown . the setting of dividing frequency of the peripheral clock made from the pll clock (pllclk) is done. ? pi cd : address 1001 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pdiv[3:0] initial value 1 1 1 1 0 0 1 1 attribute r 1, w x r 1, w x r 1, w x r 1, w x r / w r / w r / w r / w [b it 7 to bit 4] ( reserved ) [b it 3 to bit0] pdiv [3:0] : se ts peripheral clock division rate the ratio of dividing frequency of the peripheral clock (pclk2) is set from the pll clock (pllclk) [ non spread spectrum clock ] at sacr . m=1. pdiv[3:0] pll clock (pllclk)[ non spread spectrum clock ] pclk2 division rate 0000 do not divide 0001 2 division 0010 3 division 0011 4 division ( initial value ) 0100 5 division 0101 6 division 0110 7 division 0111 8 division 1000 9 division 1001 10 division 1010 11 division 1011 12 division 1100 13 division 1101 14 division 1110 15 division 1111 16 division mb91590 series mn705-00009-3v0-e 195
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 50 note: set this register so that the peripheral clock (pclk2) definitely becomes 40mhz or less. mb91590 series mn705-00009-3v0-e 196
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 51 4.26. gdc pll control register : gpllcr the bit configuration of the gdc pll control register is s hown . displays the status of pll /sscg oscillation in gdc and sets interrupt. ? g pllcr : address 0 f51 h ( access : byte , half - word , word ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 g_pcrdy reserved g_pcen initial value 0 0 0 0 0 0 0 0 attribute r,w x r x ,w x r x ,w x r x ,w x r x ,w x r / w 0 r / w 0 r / w [b it 7] g_pcrdy : pll clock ready flag it is a flag to confirm whether pll / sscg in the gdc can be used . g_pcrdy pll /sscg clock ready in the gdc 0 oscillation is stopped or oscillation stabilization wait 1 oscillation stab ilization and enabled [b it 6 to bit3 ] reserved the reading value is undefined . writing has no effect. [b it 2, bit1] reserved always write "0" to these bits. [b it 0] g_pcen : pll clock enabled this bit controls pll/sscg clock oscillation circuit for gdc as f ollows. g_pcen pll / sscg clock enabled in gdc 0 o scillation stopped 1 o scillation enabled mb91590 series mn705-00009-3v0-e 197
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 52 4.27. gdc pll timer setting register : ptimcr: the bit configuration of the gdc pll timer setting r egister is shown . sets the oscillation stabilization wait time of pl l sscg in gdc. note: this register can be written only when gpllcr:g_pcen=0 . ? p timcr : address 0 f52 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved posw [3:0] initial value 0 0 0 0 1 1 1 1 attribute r 0 ,wx r 0 ,wx r 0 ,w x r 0 ,wx r / w r / w r / w r / w [b it7 to bit 4 ] reserved [b it 3 to bit0] posw[3:0] : pll oscillation stabilization wait time selection these bits select the oscillation stabilization wait time of pll/sscg for gdc as follows : posw[3:0] o scillation stabilization wa it time of pll/sscg for gdc at 4mhz 1000 2 9 main clock period 128.0[ s] 1001 2 10 main clock period 256.0[ s] 1010 2 11 main clock period 512.0[ s] 1011 2 12 main clock period 1024.0[ s] 1100 2 13 main clock period 2048.0[ s] 1101 2 14 main clock period 4096.0[ s] 1110 2 15 main clock period 8192.0[ s] 1111 2 1 6 main clock period ( initial value ) 16384.0[ s] "1" is always read from posw3 . mb91590 series mn705-00009-3v0-e 198
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 53 4.28. gdc pll external division setting register : pedivcr the bit configuration of the gdc pll external division setting r egister is shown . sets the division rate of pll sscg output clock in gdc. note: this register can be written only when gpllcr:g_pcen=0 . ? p edivcr : address 0 f53 h ( access : byte , half - word , word ) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 reserved pods[2:0] reserved sods[2:0] initial value 0 0 0 0 0 0 0 0 attri bute r 0 ,w x r/w r/w r/w r 0 ,w x r/w r/w r/w [b it 7] ( reserved ) [b it6 to bit 4 ] pods [2:0] : pll macro oscillation clock division rate selection selects the division rate when the pll macro oscillation clock in gdc is converted to the pll clock in gdc (which i s input into clock gear) from the followings : pods [2:0] division rate setting 000 gdc pll clock = gdc pll macro oscillation clock /2 001 gdc pll clock = gdc pll macro oscillation clock /4 010 gdc pll clock = gdc pll macro oscillation clock /6 011 gdc p ll clock = gdc pll macro oscillation clock /8 100 gdc pll clock = gdc pll macro oscillation clock /10 101 gdc pll clock = gdc pll macro oscillation clock /12 110 gdc pll clock = gdc pll macro oscillation clock /14 111 gdc pll clock = gdc pll macro osci llation clock /16 note: setting by this bit is only division by an even number. division by an odd number can not be set. the duty of the output clock is 50%. [b it 3] ( reserved ) mb91590 series mn705-00009-3v0-e 199
chapter 5: clock 4 . register s fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 54 [b it 2 to bit0] sods [2:0] : pll_sscg macro oscillation clock division rate selection selects the division rate when the sscg macro oscillation clock in gdc is converted to the sscg clock in gdc (which is input into clock gear) from the followings : sods [2:0] division rate setting 000 gdc sscg clock = gdc sscg macro oscillation clock /2 001 gdc sscg clock = gdc sscg macro oscillation clock /4 010 gdc sscg clock = gdc sscg macro oscillation clock /6 011 gdc sscg clock = gdc sscg macro oscillation clock /8 100 gdc sscg clock = gdc sscg macro oscillation clock /10 101 gdc sscg clock = gdc sscg macro oscillation clock /12 110 gdc sscg clock = gdc sscg macro oscillation clock /14 111 gdc sscg clock = gdc sscg macro oscillation clock /16 note: setting by this bit is only division by an even number. division by an odd number can not be set. the duty of the output clock is 50%. a set value is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 200
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 55 4.29. gdc pll multiplier setting register : pdivcr the bit configuration of the gdc pll multiplier setting r egister is shown . sets the multiplication rate of pll in gdc. note: this register can be written only when gpllcr:g_pcen=0 . ? pdivcr : address 0f55 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved idiv[6:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r / w r / w r / w r / w r / w r / w r / w [b it 7] ( reserved ) [b it6 to bit0] idiv [6:0] : pll clock multiplication rate selection selects the multiplication rate of the pll macro osci llation clock in gdc from the following : idiv [ 6 :0] multiplication rate 0000000 - 0001011 setting is prohibited 0001100 13 ? ?? 1100010 99 1100011 100 1100100 - 1111111 setting is prohibited a set value is limited. see " 5.1. 4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 201
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 56 4.30. gdc pll_sscg multiplier setting register 0 : sdivcr0 the bit configuration of the gdc pll_sscg multiplier setting r egister 0 is shown . this is a register to set the multiplication rate n of sscg in gdc. the multiplication ratio of sscg for gdc is p x n with the setting of sdivcr1 . note: this register can be written only when gpllcr:g_pcen=0 . ? sdivcr0 : address 0f56 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ndiv[5:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r 0, w x r / w r / w r / w r / w r / w r / w [b it 7, bit6] ( reserved ) [b it 5 to bit0] ndiv [5:0] : pll_sscg clock multiplication rate (n - divider) selection selects the multiplicat ion rate of the sscg macro oscillation clock (the part of n - divider) in gdc from the followings : ndiv [ 5 :0] multiplication rate 000000 setting is prohibited 000001 2 000010 3 000011 4 ? ?? 111101 62 111110 63 111111 setting is prohibited a set val ue is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 202
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 57 4.31. gdc pll_sscg multiplier setting register 1 : sdivcr1 the bit configuration of the gdc pll_sscg multiplier setting r egister 1 is shown . this is a register to set the multiplication rate p of sscg in gdc. the multiplication ratio of sscg for gdc is p x n with the setting of sdivcr0 . note: this register can be written only when gpllcr:g_pcen=0 . ? sdivcr 1 : address 0f57 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pdiv[4:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w x r 0, w x r 0, w x r / w r / w r / w r / w r / w [b it 7 to bit5] ( reserved ) [b it 4 to bit0] pdiv [4:0] : pll_sscg clock multiplic ation rate (p - divider) selection selects the multiplication rate of the sscg macro oscillation clock (the part of p - divider) in gdc from the followings : pdiv[4:0] multiplication rate 00000 1 0 0001 2 00010 3 00011 4 ? ?? 11101 30 11110 31 11111 se tting prohibited a set value is limited. see " 5.1.4 limitations when pll/ sscg c lock is used " when you set it. mb91590 series mn705-00009-3v0-e 203
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 58 4.32. gdc pll_sscg spread spectrum setting register 0 : ssscr0 the bit configuration of the gdc pll_sscg spread spectrum setting r egister 0 is shown . sets various settings of sscg in gdc. note: this register can be written only when gpllcr:g_pcen=0 . ? s sscr0 : address 0f59 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sfreq[1:0] smode sen initial value 0 0 0 1 0 0 0 0 attribute r 0, w x r 0, w x r 0, w x r1,w1 r / w r / w r / w r / w [b it 7 to bit4] ( reserved ) always write " 1 " to bit 4. [b it 3, bit2] sfreq [1:0] : spread spectrum modulation frequency selection t hese bits s elect a spread spectrum modulation frequency of sscg in gdc from the followings : sfreq [ 1 :0] modulation frequency 00 1/1024 01 1/2048 1x 1/4096 [b it 1] smode : spread spectrum modulation mode selection these bits s elect spread spectrum modulation mode of sscg in gdc from the followings : smode modulation mode 0 down spread 1 center spread ? down spread time target period modulation rate 1/modulation frequency c ycle to cycle jitter mb91590 series mn705-00009-3v0-e 204
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 59 ? center spread time target period modulation rate 1/modulation frequency c ycle to cycle jitter [b it 0] sen : spread spectrum enabled t his bit c ontrols spread spectrum enabled /di s abled of sscg in gdc . sen spread spectrum enabl ed 0 spread spectrum disabled 1 spread spectrum ena bled note: diffusivity of the spread spectrum becomes 0% regardless of a setting of the s sscr1:ratesel when sen is set disabled. mb91590 series mn705-00009-3v0-e 205
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 60 4.33. gdc pll_sscg spread spectrum setting register 1 : s sscr 1 the bit configuration of the gdc pll_sscg spread spectrum setting r egister 1 is shown . sets various settings of sscg in gdc. no te: this register can be written only when gpllcr:g_pcen=0 . ? s sscr 1 : address 0f5a h ( access : half - word , word ) bit15 bit14 bit13 bit12 bi t11 bit10 bit9 bit8 ratesel [2:0] reserved initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r 0, w x r 0, w x r 0, w x r /w0 r /w0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved initial value 0 0 0 0 0 0 0 0 attribute r /w0 r /w0 r /w0 r /w0 r /w0 r /w0 r /w0 r /w0 [b it 15 to bit13] ratesel [2:0] : spread spectrum modulation rate selection selects the spread spectrum modulation rate of sscg in gdc from the followings. ratesel [ 2 :0] modulation rate 00x 0.5% 010 1% 011 2% 100 3% 101 4% 110 5% 111 setti ng is prohibited [b it 12 to bit 1 0] ( reserved ) writing has no effect. [b it 9 to bit0] (reserved) always write "0" to these bits. mb91590 series mn705-00009-3v0-e 206
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 61 4.34. gdc pll clock gear setting register 0 : pgrcr0 the bit configuration of the gdc pll clock gear setting r egister 0 is shown . se ts various settings of pll clock gear in gdc . ? p grcr0 : address 0f5d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p grsts[1 :0 ] reserved p grstr p gren initial value 0 0 0 0 0 0 0 0 attribute r , w x r , w x r 0, w x r 0, w x r 0, w x r 0, w x r , w r / w [b it 7, bit6] pgrsts [1:0] : pll clock gear status flag t hese bits i ndicate the status of a clock gear for controlling pll clock in gdc . pgrsts [1:0] s t atus 00 stop in the stat us of low - speed oscillation or no use of clock gear 01 in the operati on of gear up 10 stop in the stat us of high - speed oscillation 11 in the operation of gear down [b it 5 to bit2] ( reserved ) [b it 1] pgrstr : pll clock gear start the clock gear starts when pgrstr=1(this bit) and pgren=1. after the opera t ion of gear comp letes, this bit is cleared to "0". when p grsts =00 pgrstr operation "0" write not affect the operation " 1 " write start the operation of gear up when p grsts =01/11 pgrstr operation "0" write not affect the operation "1" write not affect the operation wh en p grsts =10 pgrstr operation "0" write not affect the operation "1" write start the operation of gear down mb91590 series mn705-00009-3v0-e 207
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 62 note: write "1" to this bit when gpllcr:g_pcen=1 the operation of this bit depends on the setting value of the pgrsts bit. the clock gear does not operate while pgren=0 even if "1" is written to this bit. [b it 0] pgren pll clock gear enabled enables the operation of the clock gear. pgren operation 0 no use of clock gear 1 u se of clock gear note: this bit can be set when gpllcr:g_pcen =0. on ly use of the clock gear up or the clock gear down is disabled. mb91590 series mn705-00009-3v0-e 208
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 63 4.35. gdc pll clock gear setting register 1 : pgrcr1 the bit configuration of the gdc pll clock gear setting r egister 1 is shown . sets the various settings of the pll clock gear in gdc. no te: thi s register can be written only when gpllcr:g_pcen=0 . ? p grcr 1 : address 0f5e h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p grst p [1 :0 ] p grstn [5:0] initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r / w r / w r / w [b it 7, bit6] p grst p [1:0] : pll clock gear step selection t hese bits s elect the number of steps (the number of increments/decrements) at the time of the clock gear up/down. pgrstp [1:0] the number of steps 00 1 01 2 10 3 11 4 [b it 5 to bit0] p grst n [5:0] : pll clock gear start step selection t hese bits s elect the step at the start of the clock gear operation. the step between 0 to 63can be selected. pgrstn [5:0] the number of steps 000000 0 000001 1 000010 2 ? ?? 111101 61 111110 62 111111 63 mb91590 series mn705-00009-3v0-e 209
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 64 no te: the gear does not operate at p grstn =111111(number 63 of steps) setting. mb91590 series mn705-00009-3v0-e 210
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 65 4.36. gdc pll clock gear setting register 2 : pgrcr2 the bit configuration of the gdc pll clock gear setting r egister 2 is shown . sets the various settings of the pll clock gear in gd c. no te: this register can be written only when gpllcr:g_pcen=0 . ? p grcr 2 : address 0f5f h ( access : byte , half - word , word ) 7 6 5 4 3 2 1 0 p gr lp [ 7:0 ] initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r / w r / w r / w [b it 7 to bit0] p gr lp [7:0 ] : pll clock gear repeat count selection selects the repeat count of 1 step. the repeat count between 1 to 256 can be set. the step is incremented/decremen t ed when the repeat count set by this bit completes. pgrlp [7:0] the number of loop 0000_0000 1 00 00_0001 2 0000_0010 3 ? ?? 1111_1101 254 1111_1110 255 1111_1111 256 mb91590 series mn705-00009-3v0-e 211
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 66 4.37. gdc pll_sscg clock gear setting register 0 : sgrcr0 the bit configuration of the gdc pll_sscg clock gear setting r egister 0 is shown . sets the various settings of the sscg clock ge ar in gdc. ? s grcr0 : address 0f61 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s grsts[1 :0 ] reserved s grstr s gren initial value 0 0 0 0 0 0 0 0 attribute r , w x r , w x r 0, w x r 0, w x r 0, w x r 0, w x r , w r / w [b it 7, bit6] sgrsts [1:0] : pll_sscg clock gear status flag t hese bits i ndicate the status of the clock gear which controls the sscg clock in gdc . sgrsts [1:0] status 00 stop in the stat us of low - speed oscillation or no use of clock gear 01 in the operation of gear up 10 stop in the stat us of high - speed oscillation 11 in the operation of gear down [b it 5 to bit2] ( reserved ) [bit1] grstr : pll_sscg clock gear start the operation of the clock gear starts when sgrstr=1 (this bit) and sgren=1. this bit is cleared to "0" when the operation of gear completes. when s grsts =00 sgrstr operation "0" write not affect the operation "1" write start the operation of gear up when s grsts =01/11 sgrstr operation "0" write not affect the operation " 1 " write not affect the operation mb91590 series mn705-00009-3v0-e 212
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 67 whe n s grsts =10 sgrstr operation "0" write not affect the operation "1" write start the operation of gear down no te: write "1" to this bit when gpllcr:g_pcen=1 . the operation of this bit depends on the setting value of the sgrsts bit. the clock gear does not operate while sgren =0 even if "1" is written to this bit. [b it 0] sgr en : pll_sscg clock gear enabled t his bit e nables the operation of the clock gear. sgren operation 0 no use of clock gear 1 u se of clock gear note: this bit can be set when gpl lcr:g_pcen=0 . only use of the clock gear up or the clock gear down is disabled. mb91590 series mn705-00009-3v0-e 213
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 68 4.38. gdc pll_sscg clock gear setting register 1 : s grcr 1 the bit configuration of the gdc pll _sscg clock gear setting r egister 1 is shown . sets the various settings of the sscg c lock gear in gdc. note: this register can be written only when gpllcr:g_pcen=0 . ? s grcr 1 : address 0f62 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s grst p [1 :0 ] s grstn [5:0] initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r / w r / w r / w [b it 7, bit6] s grst p [1:0] : pll_sscg clock gear step selection selects the number of steps (the number of increments/decrements) at the time of the clock gear up/down. sgrstp [1:0] the number of steps 00 1 01 2 10 3 11 4 [b it5 to bit0] s grst n[5 :0] : pll_sscg clock gear start step selection selects the step at the start of the clock gear operation. the step between 0 to 63 can be selected. sgrstn [ 5 :0] the number of steps 000000 0 000001 1 000010 2 ? ?? 111101 61 111110 62 111111 63 mb91590 series mn705-00009-3v0-e 214
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 69 no te: the gear does not operate at s grstn =111111(number 63 of steps) setting. mb91590 series mn705-00009-3v0-e 215
chapter 5: clock 4 . registers fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 70 4.39. gdc pll _sscg clock gear setting register 2 : s grcr 2 the bit configuration of the gdc pll _sscg clock gear setting r egister 2 is shown . sets the various sett ings of the sscg clock gear in gdc. no te: this register can be written only when gpllcr:g_pcen=0 . ? s grcr 2 : address 0f63 h ( access : byte , half - word , word ) 7 6 5 4 3 2 1 0 s gr lp [ 7:0 ] initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r / w r / w r / w [b it 7 to bit0] s gr lp[7 :0] : pl l_sscg clock gear repeat count selection th ese bits s elect the repeat count of one step. the repeat count between 1 to 256 can be set. the step is incremented/decremen t ed when the repeat count set by this bit complet es. sgrlp [ 7 :0] the number of loops 0000_0000 1 0000_0001 2 0000_0010 3 ? ?? 1111_1101 254 1111_1110 255 1111_1111 256 mb91590 series mn705-00009-3v0-e 216
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 71 5. operation this section explains operation s of clock. 5.1 . oscillation cont rol 5.2 . oscillation s tabilization w ait 5.3 . selecting the s ource c lock (srcclk) 5.4 . timer 5.5 . notes when c locks c onflict 5.6 . the c lock g ear c ircuit 5.7 . operations during mdi c om munications 5.8 . about pmu clock ( pmuclk ) mb91590 series mn705-00009-3v0-e 217
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 72 5.1. oscillation control this section explains o scillation c ontrol . 5.1.1 . ma in clock (mclk) 5.1.2 . sub clock (sbclk) 5.1.3 . pll/sscg clock ( pllssclk ) 5.1.4 . limitations when pll/ sscg c lock is us ed mb91590 series mn705-00009-3v0-e 218
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 73 5.1.1. main clock (mclk) the m ain clock ( mclk ) is shown. the oscillation of the main clock stops on any of the following conditions. ? sinit reset ( see " chapter : reset ".) ? during the stop mode ? while the sub clock (sbclk) are selected as the source clock (src clk) and "0" is set to cselr : mcen after all the above conditions of the oscillation stop are cancelled and then the oscillation stabilization wait time which is set to cstbr:mosw[3:0] goes by, supplying the clock starts. the oscillation stabilization wai t time specified by the initial value is required because cstbr:mosw[3:0] is initialized at the time of return from the reset input. no te: for the single clock products, the main clock oscilation enable is always enabled (mcen=1). mb91590 series mn705-00009-3v0-e 219
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 74 5.1.2. sub clock (sbclk) the s ub clock (sbclk) is shown. the oscillation of the sub clock stops on any of the following conditions. ? after the occurrence of reset (the bus idle wait time before stop is required. see "chapter : r eset" .) ? during the stop mode ? while a clock other than th e sub clock (sbclk) are selected as the source clock (srcclk) and "0" is set to cselr:scen. ? when the clock is used as a port because the clock is used for sub oscillation and port (metal option). after all the above conditions of the oscillation stop are cancelled and then the oscillation stabilization wait time which is set to cstbr:sosw[2:0] goes by, supplying the clock starts. the sub clock oscillation stops until "1" is set to because cselr:scen is initialized to "0" at the time of return from the reset input or the init stat us . notes: ? for the single clock products, the sub clock oscilation enable is always disabled (scen=0). ? for the single clock product, the sub timer cannot be used. mb91590 series mn705-00009-3v0-e 220
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 75 5.1.3. pll/sscg clock ( pllssclk ) the pll/sscg clock ( pllssclk ) is show n. this lsi has pll and sscg (pll which generates spread spectrum clock) and can select sscg for reducing noise. the combinations of clocks which cpu and peripheral functions can select are as follows. table 5-1 clock m ode clock mode run1 run2 run3 cpu pll sscg sscg can pll pll pll peripheral pll sscg pll ocdu pll pll pll gdc(ntsc) pll pll pll gd c (other than above) sscg sscg sscg the cpu/peripheral (timer/communication) cloc k is selected by ccpsselr:pcsel. also, when cpu is operated by the sscg clock, peripheral (timer/communications) can be operated by the pll clock. in this case, the peripheral clock is selected by sacr:m and divided by picd:pdiv [3 :0]. note: when the cpu is operated by sscg and the perippherals are operated by pll, b ecause the asynchronization transfer enters between cpu/ peripheral , the penalty of 5 pclk2 to 8 pclk2 is added to the access cycle. in this case, the frequency of pclk2 must be same as that of pclk1. select synchronization with sacr:m when you want to make both cpu/peripheral operation with the pll clock. the oscillation of the pll /sscg clock (pll ss clk) stops on any of the following conditions. ? after the occurrence of reset (the bus idle wait time before stop is required. see "chapter : reset" . ) ? while the main clock oscillation stops (pcen=0) ? during the time of main clock oscillation stabilization wait (pcen=0) ? du ring the watch mode ? while a clock other than the pll /sscg clock (pllssclk) a re selected as the source clock (srcclk) and "0" is set to cselr:pcen. after all the above conditions of the oscillation stop are cancelled and then pll /sscg clock lock wait time which is set to pllcr:posw[3:0] goes by, supplying the clock starts. the pl l /sscg clock oscillation stops until "1" is set to because cselr:pcen is initialized to "0" at the time of return from the reset input or the init stat us . mb91590 series mn705-00009-3v0-e 221
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 76 the formula for calculating the clock frequency and the multiplication rate related to pll /sscg is a s follows: ( pll/sscg setting in micro controller unit ) ? pll /sscg input clock frequency = (main oscillation frequency) / (pllcr:pds[3:0] division ratio) ? pll /sscg multiplication rate =( ccpllfbr:idiv[6:0] fb input division ratio ) sscg multiplication rate = ( ccssfbr0:ndiv[5:0]fb input division ratio)(ccssfbr1:pdiv [4:0] fb input division ratio) ? pll macro oscillation clock frequency = (pll /sscg input clock frequency) pll multiplication rate sscg macro oscillation clock frequency = (pll /sscg input clock frequenc y) sscg multiplication rate ? pll clock frequency = (pll macro oscillation clock frequency) / ( ccpsdivr:pods[2:0] division ratio ) sscg clock frequency = (sscg macro oscillation clock frequency)/ ( ccpsdivr :sods[2:0] division ratio) figure 5-1 pll peripheral block diagram in microcontroller unit figure 5-2 sscg peripheral block diagram in microcontroller unit ( pll/sscg setting in gdc unit ) ? pll /sscg input clock frequency = (main oscillation frequency) ? pll multiplication rate = ( pdivc r :idiv[6:0] fb input division ratio) sscg multiplication rate = ( sdivc r0 :ndiv[5:0] fb input division ratio) ( sdivc r 1:pdiv[4:0] fb input division ratio) ? pll macro oscillation clock frequency = (pll /sscg input clock frequency) pll multiplication rate sscg macro oscillation clock frequency = (pll /sscg input clock frequency) sscg multiplica tion rate ? pll clock frequency = (pll macro oscillation clock frequency) / ( pe div cr :pods[2:0]division ratio ) sscg clock frequency = (sscg macro oscillation clock frequency) / ( p ediv cr :sods[2:0] division ratio ) sscg ccp sdivr : sods[2:0] ccssfbr0:ndiv[5:0] ccssfbr1:pdiv[4:0] pllcr : pds[3:0] pll ccpsdivr : pods[2:0] ccpllfbr : idiv[6:0] pllcr: pds[3:0] mb91590 series mn705-00009-3v0-e 222
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 77 figure 5-3 pll peripheral block diagram in gdc unit figure 5-4 sscg peripheral block diagram in gdc unit pll /sscg input clock, pll /sscg multipl ication rate and pll /sscg macro oscillation clock must be set within the operating condition ranges for built - in pll /sscg in this series. for the operating condition ranges of pll /sscg , see the data sheet. notes: ? in debug operation (e_dbcr:plock =1), pll can not stop because always supplying the pll clock is required for mdi communication. ? interrupts can not be transferred normally in switching pll - sscg. therefore, when switching pll - sscg synchronous/asynchronous, disable the interrupt from resource. ? the pll/sscg macro oscillation clock frequency has the upper bound and the lower bound. set the multiplication rate of pll/sscg so as not to exceed the following range. pll/sscg in micro controller unit : ? 200mhz pll macro oscillation clock frequency 333mhz ? 200mhz sscg macro oscillation clock frequency 333mhz (down spread) pll/sscg in gdc unit : ? 200mhz pll macro oscillation clock frequency 400mhz ? 200mhz sscg macro oscillation clock frequency 400mhz (down spread) sscg pedivcr: sods[2:0] sdivcr0:ndiv[5:0] sdivcr1:pdiv[4:0] pll pedivcr: pods[2:0] pdivcr: idiv[6:0] mb91590 series mn705-00009-3v0-e 223
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 78 5.1.4. limitations when pll/ sscg clock i s used the limitations of the pll/sscg clock are shown. u se it according to the following limitations when you use the pll/ sscg clock. microco ntroller unit clock control pll clock f requency f requency (max) fctlr : faw ccpsselr : pcsel remarks 128mhz 01 0 80 mhz 00 0 note: set pllcr or ccpsdivr and ccpllfbr so as not to exceed frequency (max). microco ntroller unit c l ock control sscg c lock f requency f requency (max) fctlr : faw ccpsselr: pcsel ccssccr0 : ssen ccssccr0 : smode ccssccr1 : ratesel remarks 128mhz 0 1 1 1 0 / 1 000 to 110 72mhz 00 1 1 0 000 to 110 downspread 72mhz 00 1 1 1 000 centerspread (0.5%) 72mhz 00 1 1 1 010 centerspread (1%) 72mhz 00 1 1 1 011 centerspread (2%) 71mhz 00 1 1 1 100 centerspread (3%) 71mhz 00 1 1 1 101 centerspread (4%) 7 0mhz 00 1 1 1 110 centerspread (5%) 128mhz 01 1 0 0 /1 000 to 110 spread 0 % 80 mhz 00 1 0 0 /1 000 to 110 spread 0 % no te: set ccpsdivr, ccssfbr0 and ccssfbr1 so as not to exceed frequency (max) . gdc unit clock control pll cl ock fr equency f requency (max) remarks 108mhz no te: set pedivcr and pdivcr so as not to exceed frequency (max). mb91590 series mn705-00009-3v0-e 224
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 79 gdc unit clock control sscg clock fr equency f requency (max) ssscr0 : ssen ssscr0 : smode ssscr1 : ratesel remarks 81mhz 1 0 / 1 000 to 110 81mhz 0 0 / 1 000 to 110 spread 0 % no te: set pedivcr, sdivcr0 and sdivcr1 so as not to exceed frequency (max). relation m odulation r ate and division r atio when sscg is used ccssccr1 : ratesel[2:0] ssscr1 : ratesel[2:0] ccssfbr0 : ndiv[5:0] sdivcr0 : ndiv[5:0] m odulation rate set value r ange o f division ratio set value lower limit set value upper limit 0.50% 00x 8 - 60 7 h 3b h 1.00% 010 8 - 60 7 h 3b h 2.00% 011 8 - 48 7 h 2f h 3.00% 100 8 - 31 7 h 1e h 4.00% 101 8 - 23 7 h 16 h 5.00% 110 8 - 18 7 h 11 h mb91590 series mn705-00009-3v0-e 225
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 80 5.2. oscillation stabilization wait oscillation stabilization wait is shown. this section describes oscillation stabilization wait for each clock input. mb91590 series mn705-00009-3v0-e 226
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 81 5.2.1. conditions for generating stabilization wait t ime conditions for the generating stabilization wait time are shown. the cancellation of the oscillation stop control for each clock enters the oscillation stabilization wait stat us . after the oscillation stabilization wait time specified by each clock, the oscillation stabilization wait stat us is cancelled and supplying clock restarts. the main (mclk) clo ck enters the oscillation stabilization wait status when the oscillation stops before cancellation of reset because the setting register is initialized by reset. the main clock does not enter the oscillation stabilization wait stat us when the main clock os cillates by reset of init and rst level because the main clock oscillation does not stop by reset of init and rst level. mb91590 series mn705-00009-3v0-e 227
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : cl ock fujitsu semiconductor confidential 82 5.2.2. selecting s tabilization w ait t ime selecting the stabilization wait time is shown. the stabilization wait time for each clock can be ch anged by setting of cstbr and pllcr . initial values after reset for clock oscillation stabilization wait time ? main clock : cstbr; mosw[3:0] bit 2 15 main clock period ? pll /sscg clock : pllcr: posw[3:0] bit 2 16 main clock period ? sub clock : cstbr: so sw[2:0] bit 2 8 sub clock period the main clock oscillation stabilization wait time is always specified by the initial value because cstbr: mosw[3:0] is initialized by reset (init or rst). except that case, the main clock oscillation stabilization wait t ime can be changed by setting to cstbr:mosw[3:0]. the pll /sscg clock lock wait time is always specified by the initial value because pllcr:posw[3:0] is initialized by reset (init or rst). except that case, the pll /sscg clock lock wait time can be changed b y setting to pllcr:posw[3:0]. set "1" to cselr:pcen after setting to pllcr:posw[3:0]. for details, see the explanation of posw in " 4.8 pll setting r egister : pllcr (pll c onfiguration register) ". the sub clock oscillation stabilization wait time is always specified by the initial value because cstbr:sosw[2:0] is initialized by reset (init or rst). except that case, the sub oscillation stabilization wait time can be change d by setting to cstbr:sosw[2:0]. mb91590 series mn705-00009-3v0-e 228
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 83 5.2.3. end of the stabilization wait t ime the e nd of the stabilization wait time is shown. the operations are stopped while the clock which is selected as a source clock (srcclk) is the stat us of the oscill a tion stabilization wai t time. the operations restart after the end of the oscill a tion stabilization wait time. you can verify that the clock which is not selected as the source clock has entered the oscillation stabilization wait time by checking the value of the ready bit corresponding to each clock for cmonr register when each clock is enabled. displays the clock oscillation stabilization wait stat us and the oscillation stabilization stat us ? m ain clock : cmonr: mcrdy = "0" , cmonr:mcrdy = "1" ? pll/sscg clock (pllssclk) : cmonr : pcrdy = "0" , cmonr:pcrdy = "1" ? sub clock (sbclk) : cmonr: scrdy = "0" , cmonr:scrdy = "1" mb91590 series mn705-00009-3v0-e 229
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 84 5.3. selecting the s ource c lock (srcclk) selecting the source clock (srcclk) is shown. this section explains the selection control of the source clock (srcclk) which functions as the operation clock. mb91590 series mn705-00009-3v0-e 230
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 85 5.3.1. selecting the s ource clock at the t ime of initialization selecting the source clock at the time of initialization is shown. after reset (rst) the main clock (mclk) divided by 2 is selected as the source clock (srcclk) . after program operation the source clock can be changed by setting cselr:cks[1:0]. mb91590 series mn705-00009-3v0-e 231
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 86 5.3.2. procedure of switching the source cloc k the p rocedure of switching the source clock is shown. the source clock (srcclk) can not be directly switched from the pll /sscg clock (pll ss clk) to the sub clock (sbclk) and from the sub clock to the pll /sscg clock. switch the main clock divided by 2 once. set the oscillation stop as necessary because the value of the oscillation enabled bit (cselr:xcen) is held, even though the source clock is switched. figure 5-5 procedure of switching the source clock 1. t he main clock divided by 2 pll /sscg clock while selecting the main clock divided by 2 as the source clock (cmonr:ckm[1:0]=00) pll/sscg multiplication rate, sscg modulation, pll/sscg selection, setting pll /sscg lock wait time (setting pllcr/ ccpsselr/ ccpsdivr/ ccpllfbr/ ccssfbr 0/ ccssfbr1/ ccssccr0/ ccssccr1) -- when pll /sscg oscillation is not enabled -- sets clock gear (cccgrcr0:gren/cccgrcr1/cccgrcr2) clears pll /sscg clock oscillation stabilization wait timer interrupt source (ptif=0) ( as necessary ) setting pll /sscg cloc k oscillation stabilization wait timer interrupt enabled (ptie=1) pll /sscg oscillation begins (pcen=0 1) pll /sscg lock wait loop (loop until when pcrdy=1), or interrupt wait pll /sscg clock oscillation stabilization wait timer interrupt clear (ptif=0, ptie=0) switches from the source clock to pll /sscg clock (cselr:cks[1:0]=00 10) division of main clock by 2 pll/sscg sub clock clock mb91590 series mn705-00009-3v0-e 232
chapter 5: clock 5 . operati on fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 87 the clock gear begins (cccgrcr0:grstr=1) ve r i f ies that the clock gear high - speed oscillation is stopped (cccgrcr0:grsts[1:0]=10) while selecting pll /sscg clock as the source clock (cmonr:ckm[1:0]=10) 2. pll /sscg clock the main clock divided by 2 while selecting pll /sscg clock as the source clock (cmonr:ckm[1:0]=10) clock gear begins (cccgrcr0:grstr=1) ve r i f ies that the clock gear low - speed oscillation is stopped ( cccgrcr0:grsts[1:0]=00) switches the source clock to the main clock divided by 2 (cselr:cks[1:0]=10 00) while selecting the main clock as the source clock (cmonr:ckm[1:0]=00) 3. the main clock divide by 2 sub clock while selecting the main clock divided by 2 as the source clock (cmonr:ckm[1:0]=01) sets the sub clock oscillation stabilization wait time (sets cstbr:sosw[2:0]) ? when sub oscillation is not enabled ? clears the sub timer interrupt source (stif=0) (as necessary) sets sub timer interrupt enable (stie=1) the sub oscillation begins (scen=0 1) sub clock oscillation stabilization wait loop (loop until when scrdy=1 ) , or interrupt wait clears sub timer interrupt (stif=0) switches the source clock to the sub clock (cselr:cks[1:0]=01 11) mb91590 series mn705-00009-3v0-e 233
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 88 while selecting the sub clock as the source clock (cmonr:ckm[1:0]=11) 4. the sub clock the main clock divided by 2 while selecting the sub clock as the sou r ce clock (cmonr:ckm[1:0]=11) sets the main clock oscillation stabilization wait time (sets cstbr:mo sw[3:0]) ? when the main oscillation is not enabled ? clears the main timer interrupt source (mtif=0) (as necessary) sets the main timer interrupt enable (mtie=1) the main oscillation begins (mcen=0 1) the main clock oscillation stabilization wait loop (loop until when mcrdy=1), or interrupt wait clears the main timer interrupt (mtif=0) switches the source clock to the main clock divided by 2 (cselr:cks[1:0]=11 01) while selecting the main clock as the source clock (cmonr:ckm[1:0]=01) mb91590 series mn705-00009-3v0-e 234
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 89 figure 5-6 example of pll /sscg mode setting main pll/sscg yes main clock mode is confirmed. yes pll /sscg clock stabilization wait time is set. the sscg use is judged. no yes select sscg select pll m ultip lication rate of pll is set. multiplication rate of pll is set. (for can and ocd) multiplication rate of sscg is set. the method of sscg's s pread is set. the gear use is judged. no yes th e gear is set to the valid stat us . the gear is set to the invalid stat us . setting of gear step no yes pll /sscg clock oscillation stabilization wait timer interrupt flag is clear. pll /sscg clock oscillation s tabili zation wait timer interrupt to effective the operation of pll/sscg starts the operation of pll/sscg begins. pll /sscg clock oscillation stabilization is fixed. no the pll/sscg clock operation stabil ity is judged. yes dividing various clocks (cpu/peripheral) is set. when sscg is used , peripheral resource is judged and whether it operates with pll clock is judged. when pll is use d, it is always synchronization no yes dividing the asynchronous p eripheral clock is set. the relation of the cpu/peripheral clock is set a synchronously. the relation of the cpu/peripheral clock is set synchronously. when pll /sscg clock exceeds 80mhz, i insert wait cycle into flash access . change to the pll/sscg clo ck no comfirm whether the source clock has switched pll/sscg. yes when the gear is used, the gear is begun. no yes no it is confirmed that the clock has low - speed stopped . yes gear start no t he gear completion is confirmed . yes start c monr. c k m =00 c sel r . ck s =00 pllcr .posw cccgrcr0 . gren=1 is the gear used? cccgrcr1.grstp cccgrcr1.grstn cccgrcr2.grlp cselr . pcen=1 cmonr . pcrdy=1 divr0 . divb divr2 . divp sacr . m=1 cselr . cks=10 cmonr . ckm=10 cccgrcr0 . gren=0 is the gear used? cccgrcr0 . g rsts=00 cccgrcr0 . grstr=1 cccgrcr0 . grsts =10 pll/sscg operation is the sscg used? ccpsselr . pcsel=1 ccpsselr . pcsel=0 ccpsdivr . sods ccssfbr0. ndiv ccssfbr1 . pdiv pllcr.pds ccpsdivr.pods ccpllfbr . idiv pllcr.pds ccpsdivr.pods ccpllfbr . idiv ccssccr0 . sfre q ccssccr0 . smode ccssccr0 . ssen ccssccr1 . ratesel peripheral resource a synchronously ? sacr . m=0 picd . pdiv fctlr . faw is the interrupt used? ptmcr . ptif =0 ptmcr . ptie=0 cselr.pcen=1 pll oscillati on stabilization wait timer interrupt generation no yes yes yes yes yes yes mb91590 series mn705-00009-3v0-e 235
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 90 figure 5-7 example of pll /sscg mode setting pl l /sscg main n o pll /sscg clock mode is confirmed. yes the gear use is judged. no yes no it is confirmed that the clock has high - speed stopped. yes gear start no the gear completion is confirmed. yes change to the main clock n o comfirm whether the source clock has switched the main oscillation. the operation of pll /sscg is stopped. when pll /sscg clock exceeds 80mhz, flash access is set to no wait, again. dividing various clocks (cpu/peripheral) is set. when sscg is used , peripheral resource is judged and whether it operates with pll clock is judged. when pll is used, it is always synchronization. no yes the relation of the cpu/peripheral clock is set synchronously. start c monr. ck m =10 c selr. ck s =10 is the gear used? cccgrcr0 . grsts =10 cccgrcr0 . grstr=1 cccgrcr0 . grsts =00 cselr . cks=00 cmonr . ckm= 0 0 cselr . pcen=0 main operation divr 2. div p divr 0. div b peripheral resource a synchronously ? sacr . m=0 fctlr . faw yes mb91590 series mn705-00009-3v0-e 236
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 91 5.4. timer the timer is shown. 5.4.1 . m ain c lock o scillation s tabilization w ait t imer (m ain t imer ) 5.4.2 . s ub c lock o scillation s tabilization w ait t imer (sub t imer ) 5.4.3 . pll/sscg c lock o scillation s tabilization w ait t imer ( pll t imer ) 5.4. 4 . setting 5.4.5 . procedure for s etting the t imer i nterrupt 5.4.6 . timer operations 5.4. 7 . watch m ode and t imer i nterrupt mb91590 series mn705-00009-3v0-e 237
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 92 5.4.1. main clock oscillation stabilization wait t imer (m ain timer) the main clock oscillation stabilization wait timer (m ain t imer ) is explained. the main timer is operated by the main clock (mclk). it is used for tha main clock stabilization time counter. when main clock is stabilized, the timer can be used as the timer which generates interrupt after the specified period. mb91590 series mn705-00009-3v0-e 238
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 93 5.4.2. s ub clock oscillation s tabilization w ait t imer (sub timer) the sub clock osc illation stabilization wait timer (sub t imer ) is explained. the sub timer is operated by the sub clock (sbclk). this timer is used for the generation of the sub clock oscillation stabilization wait time, and in the the sub clock stabilization stat us other than those can be used as the timer which generates interrupt after the specified period. mb91590 series mn705-00009-3v0-e 239
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 94 5.4.3. pll /sscg clock oscillation stabilization wait timer ( pll timer ) the pll /sscg clock oscillation stabilization wait timer ( pll t imer ) is shown. the pll timer is operat ed by the main clock and only for generation of the pll /sscg clock oscillation stabilization wait time. this timer can not be used for a general - purposed timer. mb91590 series mn705-00009-3v0-e 240
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 95 5.4.4. setting setting is shown. if the main timer operation is enabled (mtmcr:mte=1), the count ope ration of the main timer starts. if the main timer operation is disabled (mtmcr:mte=0), the count operation of the main timer stops and the main timer is cleared. if the main timer is cleared (mtmcr:mtc=1), the main timer is cleared. mtmcr:mtc=1 is read until clear. the period of interrupt can be set by mtmcr:mts[3:0]. when mtmcr:mtie=1, if mtmcr:mtif=1, the main timer interrupt occurs. mtmcr:mtif is cleared by writing "0". if the s u b timer operation is enabled (stmcr:ste=1), the count operation of the sub timer starts. if the sub timer operation is disabled (stmcr:ste=0), the count operation of the sub timer stops and the sub timer is cleared. if the sub timer is cleared (stmcr:stc=1), the sub timer is cleared. stmcr:stc=1 is read until clear. the period of interrupt can be set by stmcr:sts[2:0]. when stmcr:stie=1, if stmcr:stif=1, the sub timer interrupt occurs. stmcr.stif is cleared by writing "0". note: for setting the period of the timer interrupt (mts and sts), set the period more than pclk 1 5 clock . when the period of the timer interrupt is set to the extremely short time, the interrupt source may not be set. mb91590 series mn705-00009-3v0-e 241
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clo ck fujitsu semiconductor confidential 96 5.4.5. procedure for s etting the timer i nterrupt the procedure for setting the timer interrupt is shown. this section describes the procedure for setting interrupt. the examples of the procedure for setting interrupt are shown as follows. sets the timer interrupt di s able (mtmcr:mtie=0)/(stmcr:stie=0) and the interrupt flag clear(mtmcr:mtif=0)/(stmcr:stif=0) sets the timer operation disable (mtmc r:mte=0)/(stmcr:ste=0) verifies mtc=0/stc=0 sets the period of the timer (mtmcr:mts=1000 to 1111)/(stmcr:sts=000 to 111) sets the timer interrupt enable (mtmcr:mtie=1)/(stmcr:stie=1) sets the timer operation enable (mtmcr:mte=1)/(stmcr:ste=1) th e interrupt occurs after setting time to the interrupt routine sets the interrupt flag clear (mtmcr:mtif=0)/(stmcr:stif=0) verifies the interrupt flag (mtmcr:mtif=0)/(mtmcr:stif=0) program operations reti * repeat reading until "0" is read bec ause actual setting of the interrupt flag clear is delayed. mb91590 series mn705-00009-3v0-e 242
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 97 5.4.6. timer operations timer o perations are shown. when mtmcr:mte=1, the main timer counts up by the main clock (mclk). if the timer overflows by the period which is selected by mtmcr:mts[3:0], mtmcr:m tif is "1" . while stmcr:ste=1, the sub timer counts up by the sub clock (sbclk). if the timer overflows by the period which is selected by stmcr:sts[2:0], stmcr : stif is "1". mb91590 series mn705-00009-3v0-e 243
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 98 5.4.7. watch m ode and t imer i nterrupt watch mode and timer interrupt are shown. watch m ode stops the specific functions and all operations other th an timer. (see "chapter : power consumption control") the wake - up from the watch mode is enabled by using main/sub timer interrupt or rtc interrupt. the example for switching of the watch mode in t he setting of wake - up from the sub timer is shown as follows. figure 5-8 w ake - up from the w atch m ode sub clock selection sub timer inter r upt sub timer setting w atch mode setting sub w atch mode wak eup wak eup o vf mb91590 series mn705-00009-3v0-e 244
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 99 5.5. notes when clocks c onflict notes when clocks conflict is shown. notes that if peripheral interrupt activated by the very low frequency lower than the cpu clock (cclk) in the interrupt handler is cleared and the interrupt handler is immediately stopped, the peripheral can not complete the internal process within the period of interrupt handler and the interrupt handler may be called over again. mb91590 series mn705-00009-3v0-e 245
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 100 5.6. the clock gear circuit the clock gear circuit is shown. when the main clock is switched to the pll/sscg clock or the pll/sscg clock is switched to the main clock, the power supply current fluct uates widely because the frequency fluctuates rapidly. using the clock gear circuit in the part of the clock switching can gradually fluctuate the operating frequency from a low frequency to a high frequency or from a high frequency to a low frequency and therefore can reduce the fluctuation of the power supply current. mb91590 series mn705-00009-3v0-e 246
chapter 5: clock 5 . opera tion fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 101 5.6.1. procedure of gear up the p rocedure of gear up is shown. 1. the clock of the start step set to the clock gear start step selection is output after the oscillation stabilization wait timer compl etes . 2. when the clock gear start ( cccgrcr0 : grstr, pgrcr0 : pgrstr and sgrcr0 : sgrstr ) is set to "1" and the rising is detected, the clock gear status flag (cccgrcr0 : grsts[1:0], pgrcr0 : pgrsts[1:0] and sgrcr0 : sgrsts[1:0]) transits to " 00 "->" 01 " (give up start). 3. the gear up is executed according to the clock gear step selection and the repeat number selection. the step number is the smaller and the repeat number is the larger that the operation changes the more gradually 4. when the clock reaches the maximum step, th e clock gear status flag (cccgrcr0 : grsts[1:0], pgrcr0 : pgrsts[1:0] and sgrcr0 : sgrsts[1:0]) transits to "01" - >"10" (the end of gear up, the gear stops). after this, a clock is output at the maximum step (64 step s ). 5. after the ge a r stops, the clock gear start ( cccgrcr0 : grstr,pgrcr0.pgrstr and sgrcr0 : sgrstr ) is cleared to "0" by hardware. mb91590 series mn705-00009-3v0-e 247
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 102 5.6.2. procedure of gear d own the p rocedure of gear down is shown. 1. when the clock gear start (cccgrcr0 : grstr, pgrcr0 : pgrstr and sgrcr0 : sgrstr) is set to " 1 " and the rising is detec ted, the clock gear status flag (cccgrcr0 : grsts[1:0], pgrcr0 : pgrsts[1:0] and sgrcr0 : sgrsts[1:0]) transits to "10" - >"11" (give down start). 2. the gear down is executed according to the clock gear step selection and the repeat number selection. the step number is the smaller and the repeat number is the larger that the operation changes the more gradually. 3. when the clock reaches the minimum step, the clock gear status flag (cccgrcr0 : grsts[1:0], pgrcr0 : pgrsts[1:0] and sgrcr0 : sgrsts[1:0]) transits to "11" - >"00" (the end of gear down, the gear stops). after this, the clock of the start step set for the clock gear start step selection is output. 4. after the gear stops, the clock gear start (cccgrcr0 : grstr, pgrcr0 : pgrstr and sgrcr0 : sgrstr) is cleared to " 0 " by hardware . mb91590 series mn705-00009-3v0-e 248
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 103 5.7. operations during mdi c ommunications operations during mdi communications are shown. the main oscillation is controlled so as not to be stopped during mdi communications even if the stop mode is transited to. moreover, (e_dbcr:plock=1) is controlled so that the pll reference clock is supplied even if cselr:pcen is cleared while communicating the mdi high speed. the value of the register related to pll is maintained and not updated. however, when software sets cselr:pcen=0, the value of the register rela ted to pll can be freely updated (write). when a value set to the register related to pll last time and a different value are written and the pll/sscg clock oscillation permission is assumed to be effective (cselr:pcen=1), the frequency of the pll clock is not updated. (pll : because it maintains the locked stat us . ) norma l ly, a lways write the same value in the register related to pll usually. when you change the setting value in the debug, m onitor the value of e_dbcr:plock and rewrite the regis ter related to pll in the stat us of e_dbcr:plock =0. * the register related to pll is as follows. ? ccpsdivr :p ods ? ccpllfbr : idiv ? pllcr: p ds mb91590 series mn705-00009-3v0-e 249
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 104 5.8. about pmu clock ( pmuclk ) the pmu clock ( pmuclk ) is shown. the pmu clock is an operation clock of power management uni t (pmu). c omplete the setting of this clock before controlling the standby mode. figure 5-9 watch/power management clock generation unit the frequency of the pmu clock can be cal culated by the following expressions. ? when ccrtselr : csc =0 ( main clock is selected ) pmu clock frequency = (main clock frequency ) / ( ccpmucr0 : fdiv [1:0] division ratio) / ( ccpmucr1 :g div[4:0] division ratio ) ? when ccrtselr :c sc =1 ( sub clock is selected ) pmu c lock frequency = (sub clock frequency ) / ( ccpmucr1 : gdiv[4:0] division ratio ) moreover, observe the following specification limitation to the pmu clock. (there is a possibility that the shutdown processing is not normally done when this limitation is not defended. ) (1 ) s elect s the clock under the oscillation about ccrtselr: c sc. * (2 ) the pmu clock must use the machine of f divid er frequency to become 32khz or less. (3 ) please use the machine of g dividing frequency to become 1/4 of the frequencies of p eripheral clock (pclk1). *: always ccrtselr: c sc = "0" is always read for single clock products. it explains each specification limitation as follows. (1) s elect s the clock under the oscillation about ccrtselr: c sc. please confirm the cmonr: mcrdy register and the cmonr : scrdy register to the oscillation of the main clock and a sub - clock. moreover, when the ccrtselr: c sc register is rewritten, the processing of the handshaking of the main clock and a sub - clock (clock transfer) is generated. if both clocks are oscillating (cmonr:mcrdy = cmonr:scrdy = 1) , the change operation is not normally completed for this period. please confirm the stat us of the clock transfer by the ccrtselr: c st register . mclk (pmuclk) pmu clock 0 1 ccrtselr . csc sbclk (watclk) rtc clock ccpmucr0 : fdiv ccpmucr1 : gdiv 0 1 main clock (128 to 512 division ) divider (f divider) pmu clock (1 to 32division ) divider ( gdivider ) mb91590 series mn705-00009-3v0-e 250
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 105 (2 ) the pmu clock must use the machine of f divid er frequency to become 32khz or l ess. the pmu clock is used to control the power switch, and the frequency of 32khz or less is recommended for the reasons for the stabilization at the pressure rising time when the power supply is input etc. as for the pmu clock, the main clock is selected for ccrtselr: c sc=0 as a source clock. please set the ccpmucr0: f div register so that the frequency of the pmu clock may become 32khz or less. the machine of f divid er frequency does not influence operation for ccrtselr: c sc=1. fdiv[1:0] division rate targ et main oscillation frequency 00 128 division ( initial va lue ) 4mhz 01 256 division 8mhz 10 384 division 12mhz 11 512 division 16mhz (3 ) please use the machine of g dividing frequency to become 1/4 of the frequencies of p eripheral clock (pclk1). signal t ransfer between peripheral clock (pclk) and pmu clock (pmuclk) needs 4 pmu clock cycles. when the source clock of peripheral clock(pclk1) is sub oscillation clock (cmonr:ckm=10), the frequency of peripheral clock(pclk1) should be set quadruple (or more hig her) frequency of pmu clock. it can be set by ccpmucr1:gdiv register. when the source clock of peripheral clock(pclk1) is main oscillation clock (cmonr:ckm=00 or cmonr:ckm=01). if the frequency of peripheral clock(pclk1) is slower than 128khz (depends on d ivr0:divb and divr2:divp), ccpmucr1:gdiv register should be set as same. gdiv[4:0] division ratio 00000 do not divide ( initial value ) 00001 2 division 11110 31 division 11111 32 division [ reference ] the frequency of the p eripheral clock (pclk1 ) can be calculated by the following expressions. peripheral clock ( pclk1 ) frequency =(c lock frequency selecting it by cmonr :c km ) / ( divr0 :d ivb[2:0] division ratio ) /(di vr2 :d vp[3:0] division ratio ) mb91590 series mn705-00009-3v0-e 251
chapter 5: clock 5 . operation fujitsu semiconductor limited chapter : clock fujitsu semiconductor confidential 106 mb91590 series mn705-00009-3v0-e 252
chapter 6: clock reset state transition 1 . overview fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 1 c ha pter: clock reset state transition s this chapter explains clock reset state transitions. 1. overview 2. device states and transitions 3. device state and regulator mode corresponding to those states code : 06_mb91590_hm_e_clockreset_00 4 _201111 27 mb91590 series mn705-00009-3v0-e 253
chapter 6: clock reset state transition 1 . overview fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 2 1. overview this section explains the overview of clock reset state transitions. this chapter explains state transition of clock and reset. for features and settings of power consumption control state, see " chapter : power c onsumption control " . for the operations of reset, see " chapter : reset " . for the regulator mode, see " chapter : regulator control ". mb91590 series mn705-00009-3v0-e 254
chapter 6: clock reset state transition 2 . device states and transitions fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 3 2. device sta tes and transitions this section explains device states and transitions of clock reset state transitions . 2.1 . diagram of state transitions 2.2 . ex planation of each states 2.3 . priority of state transition requests mb91590 series mn705-00009-3v0-e 255
chapter 6: clock reset state transition 2 . device states and transitions fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 4 2.1. d iagram of state t ransitions this section shows d iagram of s tate t ransitions . the device state transitions for this series are shown below. figure 2-1 diagram of device state transitions power on or low - voltage detect pll sleep pll run pll clock mode sub clock mode sub sleep main clock mode sub stop sub run main sleep sub watch mode initialization ( sinit ) sub watch mode (shutdown) sub stop (shutdown) main stop main stop (sh u tdown) main watch mode main run main watch mode (shutdown) main oscillation wait sub oscillation wait program reset (rst) main oscillation stabilization wai t (reset) setting initialization ( init ) *1 power - on reset or internal low - voltage detect ion or external reset and simultaneous assert of nmi power - on reset release and internal low - voltage release and external reset and release simultaneous assert o f nmi end of oscillation stabilization wait end of oscillation stabilization wait (if the reset factor is or ) init release rst release software reset software watchdog reset (including irregular) or software reset (irregular) external re set input (nmi disabled ) or external low - voltage detection external reset input (nmi disabled + irregular) or external low - voltage detection (irregular) ? hardware watchdog reset (including irregular) ? sleep mode (write instruction) ? stop mode (write instruction) ? watch mode (write instruction) ? interrupt (including ? and ? ) ? interrupt (clock not required)/nmi ? main timer interrupt/sub timer interrupt/rtc interrupt ? switch from main to sub (write instruction) ? switch from sub to main (write instr uction) ? switch from main to pll (write instruction) (21) switch from pll to main (write instruction) (22) illegal standby mode transition (23) illegal standby mode transition detection reset (24) stop mode and shutdown (write instruction) (25) watch mode and shutdown (write instruction) mb91590 series mn705-00009-3v0-e 256
chapter 6: clock reset state transition 2 . device states and transitions fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 5 *1 : there is a register not reset when returning from the watch mode (shutdown) and returning from the stop mode (shutdown). see "limitations of the stan d by control power shutdown/usually" in "chapter : power consumption control" for detail. note s: ? the transition may be different from above diagram when connecting to ocd tool. see " chapter : on chip debugger (ocd)" for details. ? the sub clock mode is not transmitted to because single clock products do not include the sub clock input. mb91590 series mn705-00009-3v0-e 257
chapter 6: clock reset state transition 2 . device states and transitions fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 6 2.2. explanation of each states this section e xpla ins each s tate . device operation states for this series are shown below. ? run state (normal operation) the program is running. all internal clocks supply and all circuits are ready to operate. high - impedance controls for the external pins in the stop state and watch mode state will be released . ? sleep mode the program is not running. the state transits by progra m operations. there are some settings; one to stop program execution of the cpu only (cpu sleep mode) and the other to stop the cpu, on - chip bus (on - chip bus) and on- chip bus clock (hclk) driven peripheral (bus sleep mode). for details, see " chapter : power consumption control ". ? watch mode state the devices are not running. the state transits by program operations. internal circuits other than oscillation circuits (main clock generation unit, sub clock generation unit) stop. stop pll oscillation before going into the watch mode state. it is also possible to use the external pins altogether (except for some pins) for high impedance by the settings. transits to the run state by some specific (no clock required) effective interrupts, main timer interrupts, sub t imer interrupts and watch counter interrupts. for details, see " chapter : power consumption control ". ? watch mode ( power shutdown ) state the device is stopped while the power supply unnecessary for the watch mode is turned off. the state transits by program operation. the power supply for the internal circuit in microcontroller/gdc unit is turned off and the internal circuits other than the oscillation circuits (the main clock generation unit and the sub clock generation uni t) are stopped. stop pll oscillati on before going into t he watch mode (power shutdown ) state . it is also possible to use the external pins altogether (except for some pins) for high impedance by the settings. transits to the setting initialization (init) state by some specific (no clock re quired) effective interrupts , the main timer interrupt, the sub timer interrupt and the watch counter interrupt. for details, see " chapter : power consumption control" . ? stop state the devices are not running. the state transits by program operations. all in ternal circuits will stop. stop pll oscillation before going into the stop mode state. it is also possible to use the external pins altogether (except for some pins) for high - impedance by the settings. transits to the oscillation stabilization wait run sta te by nmi interrupt. for details, see " chapter : power consumption control" . ? stop ( power shutdown ) state the device is stopped while the power supply unnecessary for the stop state is turned off. the state transits by program operation. the power supply for the internal circuit in microcontroller/gdc unit is turned off and all the internal circuits are stopped. stop pll oscillation before going into the st op (power shutdown) state . it is also possible to use the external pins altogether (except for some pins ) for high impedance by the settings. transits to the main oscillation stabilization wait (reset) state by nmi interrupt. for details, see " chapter : power consumption control" . ? main oscillation stabilization wait, sub oscillation stabilization wait (run) s tate the devices are not running. transits after returning from the stop state. all the internal circuits except for the timer operations for oscillation stabilization wait will stop. all internal clocks stop but the enabled oscillation circuits will still be running. after the elapse of the oscillation stabilization wait time interval set, transits to the run state (normal operation). mb91590 series mn705-00009-3v0-e 258
chapter 6: clock reset state transition 2 . device states and transitions fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 7 ? main oscillation stabilization wait (reset) state the devices are not running. transits after returning from the initializa tion (sinit) state. all the internal circuits except for the timer operations for oscillation stabilization wait will stop. all internal clocks stop but the main oscillation circuit will still be running. outputs the program reset (rst) to the internal cir cuits. when the accepted reset level is an initialization reset, outputs also the setting initialization reset (init). after the elapse of the main clock oscillation stabilization wait time (2 15 main clock cycle), transits to the setting initialization ( init) state. ? program reset (rst) state the program is initialized. transits after accepting the operation initialization reset (rst) request or at the end of the setting initialization (init) state. outputs the program reset (rst) to the internal circuits. when transiting from the init state, ocd chip reset sequence ( 1026+ 3 pclk cycles) will be performed. transits to the run state (normal operation) when removing the operation initialization reset (rst) request. for details, see " chapter : reset ". ? setting in itialization (init) state all settings are initialized. transits after accepting a setting initialization (init) request. the main oscillation circuit continues to run but the sub oscillation circuit and pll will stop operations. outputs a setting initiali zation (init) and a program reset (rst) to the internal circuits. transits to the program reset (rst) state when removing the setting initialization (init) request and this state being released . for details, see " chapter : reset ". mb91590 series mn705-00009-3v0-e 259
chapter 6: clock reset state transition 2 . device states and transitions fujitsu semiconductor limited chapter: clock reset s tate transitions fujitsu semiconductor confidential 8 2.3. priority of state transition requests priority of s tate t ransition r equests is shown. the state transition requests are prioritized in the following order in any states. however, since some requests are generated only in the specific states, they are enabled only in those states. [h ighest priority ] i nitialization (sinit) request setting initialization (init) request the end of the oscillation stabilization wait time (generates an oscillation stabilization wait reset state and an oscillation stabilization wait run state only.) program reset (rst) request effective interrupt request (generates run, sleep, stop, watch mode states only) stop mode request (register write) (generates run state only) watch mode request (register write) (generates run state only) [ lo west priority ] s leep mode request (register write) (generates run state only) mb91590 series mn705-00009-3v0-e 260
chapter 6: clock reset state transition 3 . device state and regulator mode corresponding to those states fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 9 3. device state and regulator mode corresponding to those states device state and regulator mode corresponding to those states are shown. the regulator mode corresponding to each device state is shown in the following table. for regulator mode, see " chapter : regulator control" . table 3-1 relationship between device state and regulator mode ( single clock product ) d evice state m ain clock r egulator mode main run oscillation main mode main sleep oscillation main mode main watch mode oscillation standby mode main w atch mode ( shutdown ) oscillation standby mode main stop stop standby mode main stop ( shutdown ) stop standby mode main oscillation wait oscillation main mode pll run oscillation main mode pll sleep oscillation main mode mb91590 series mn705-00009-3v0-e 261
chapter 6: clock reset state transition 3 . device state and regulator mode corresponding to those states fujitsu semiconductor limited chapter: clock reset state transitions fujitsu semiconductor confidential 10 table 3-2 relationship between device state and regulator mode ( dual clock product ) d evice state m ain clock s ub clock r egulator mode main run oscillation oscillation or stop main mode main sleep oscillation oscillation or stop main mode main watch mode oscillation oscillation or stop standby mode main watch mode (shutdown) oscillation oscillation or stop standby mode main stop stop stop standby mode main stop (shutdown) stop stop standby mode main oscillation wait oscillation oscillation or stop main mode sub run 1 oscillation oscillation main mode sub run 2 stop oscillation sub mode sub sleep 1 oscillation oscillation main mode sub sleep 2 stop oscillation sub mode sub watch mode oscillation or stop oscillation standby mode sub watch mode ( shutdown ) oscillation or stop oscillation standby mode sub stop stop stop standby mode sub stop ( shutdown ) stop stop standby mode sub oscillation wait 1 oscillation oscillation main mode sub oscillation wait 2 stop oscillation sub mode pll run oscillation oscillation or stop main mode pll sleep oscillation oscillation or stop main mode note: when ocd tool is connected, the regulator mode is a main mode in the above any tables. mb91590 series mn705-00009-3v0-e 262
chapter 7: reset 1 . overview fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 1 chapter : reset this chapter explains the reset. 1. overview 2. features 3. configuration 4. regisyers 5. operatio n description code : 07_mb91590_hm_e_reset_00 6 _2011112 7 mb91590 series mn705-00009-3v0-e 263
chapter 7: reset 1 . overview fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 2 1. overview this section explains the overview of the reset. when a reset factor is generated, the device terminates al l programs and most of the hardware operations and initializes the state . this state is referred to as a reset. mb91590 series mn705-00009-3v0-e 264
chapter 7: reset 2 . features fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 3 2. features this section explains features of the reset. this product, which has the following reset factors, issues a reset by accepting each fact or to initialize the components in the device. ? power - on reset ? rstx p in input ? watchdog reset 0 (software watchdog) ? watchdog reset 1 (hardware watchdog) ? software reset ? illegal standby mode transition detection reset ? flash security violation ? in ternal low - vo ltage detection ? external low - voltage detection ? clock supervisor reset ? recovery reset from stand by (power shutdown) other than the case of irregular reset (see " 4.1 reset source register : rstrr ( rese t result register ) " ), the contents of memory being accessed by the reset (ram, flash) will not be destroyed since all resets are issued once the completion of all bus accesses have been confirmed. to issue a forced reset in case the bus does not return the response within a certain time frame, the device waits for the reset issue delay counter. if there is no response within the specified time frame, a reset will be issued whether or not the bus has responded. (reset timeout) see " chapter : clock superviso r" for clock supervisor reset . mb91590 series mn705-00009-3v0-e 265
chapter 7: reset 3 . configu ration fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the reset. figure 3-1 configuration diagram of reset ( *2 ) always power supply on block external reset asynchronous reset factor (*1) reset mask (external interrupt ) reset mask (rtc) s ynchronous reset factor power - on r eset cpu isolator r eturn from power shutdown and shutdown other always power supply on block reset control i/o clock control rtc and pmu isolator (*1) p owe r - on re set is contained (*2) active at return from power shutdown and shutdown csv rese t hwwd reset external interrupt and s ynchronous reset mb91590 series mn705-00009-3v0-e 266
chapter 7: reset 3 . configuration fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 5 figure 3-2 configuration diagram of reset ( reset control ) figure 3-3 generation diagram of illegal standby mode transition detection reset factor cpuar : ps t f cpuar : pstre set when the pll /sscg clock is selected as a clock source transition to watch mode or stop mode is generated illeg a l s t a nd b y mode tr ans ition detec tion re s et f a ctor wa tchdog rese t 1 generate rese t factor ext end counter extend counter in itialize rese t (ini t) extend counter re se t (rst) srst de lay counter rdly 8bi t 2bit s 4bit 4bit pclk : bit nam e of regis ter wa tchdog rese t 0 de lay se lector r irrst ers t wd g0 wd g1 srst rs tcr rs tcr rs trr rs trr re ad re se t request bu s idle response o n - c h i p b u s software reset re quest generate rese t re se t request flag pclk in debug stat e po we r-on rese t reset request from ocd too l unused (1 ? b0) flash sec urity violation rese t factor unus ed unus ed scrt cleared when read low vol tage detection( ext ernal pow er sup pl y low-voltage detection) illegal standby transi tion de tection reset factor cpuar: hw df q pclk s r q pclk in debug state no ise filter no ise filter pclk factor ext end counter 2bi t generate rese t re se t request flag in debug state pclk factor ext end counter 2bi t pclk factor ext end counter 2bi t pclk factor ext end counter 2bi t s r q s r q s r q s r q generate rese t re se t request flag in debug stat e generate rese t re se t request flag in debug stat e generate rese t re se t request flag in debug state s r q generate rese t re se t request flag in debug state s r q generate rese t re se t request flag pclk factor ext end counter 2bi t pclk factor ext end counter 2bi t unused (1 ? b0) reset request by simultaneously assert of rstx and nmix rs tx pin no ise filter nmix pin low- voltage detec tion (interna l powe r low- voltage detect ion) clock supervisor reset > on - chip bus mb91590 series mn705-00009-3v0-e 267
chapter 7: reset 4 . registers fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 6 4. regi sters this section explains the registers of the reset. table 4-1 registers map address registers register function +0 +1 +2 +3 0x0480 rstrr rstcr reserved reserved reset source register reset control register 0x 0 518 reserved reserved cpuar reserved cpu a bnormal o peration register 0x0590 pmustr reserved reserved reserved pmu status register note: please note that the register of "chanpter : power consumption control" is allocated in address 0x0482, 0x0591, and 0x0592. mb91590 series mn705-00009-3v0-e 268
chapter 7: reset 4 . registers fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 7 4.1. reset source register : rstrr (reset result register) the bit configuration of the reset source register is shown. this register displays various reset factors generated until just before. note: when this register is read out, all bits will be cleared. this register is not cleared in reading in the debugging state. because each reset factor is masked in the debugging state, this register does not detect the reset factor either. ? rstrr : address 0480 h ( access : byte , h alf - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irrst erst wdg1 wdg0 reserved scrt srst initial value * * * * - - * * attribute r,wx r,wx r,wx r,wx rx,wx rx,wx r,wx r,wx * due to a reset factor. [b it7 ] irrst (irregular reset) : irregular reset this bit indicate s that any of power - on reset, internal low - voltage detection, reset timeout , or simultaneous assert of rstx and nmix external pins has occurred, so that the bus access state when issuing a reset cannot be guaranteed. when this bit is "0" after the reset, n o bus access was executed at the previous reset, which guarantees that memory contents have not been destroyed by the reset. when this bit is "1" after the reset, it is possible that a bus access was executed at the previous reset, which does not guarantee that memory contents have not been destroyed by the reset. irrst irregular reset detected 0 irregular reset undetected 1 irregular reset detected this bit will be cleared when it is read out . [b it6 ] erst (external reset) : reset pin input, illegal stan dby mode transition detection, external low - voltage detection, clock supervisor reset, simultaneous assert of rstx and nmix external pins this bit indicates that there was a reset input from rstx pin input, illegal standby mode transition detection reset, external low - voltage de tection, clock supervisor rese t or simultaneous assert of rstx and nmix external pins . in case of a reset time out due to this reset factor, irrst along with this bit will be "1" . mb91590 series mn705-00009-3v0-e 269
chapter 7: reset 4 . registers fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 8 erst rstx pin reset detection, illegal standby mode transition detection, external low - voltage detection, clock supervisor reset or simultaneous assert of rstx and nmix external pins 0 undetected 1 detected this bit will be cleared when it is read out . [b it5 ] wdg1 (watchdog reset 1) : watchdog reset 1 this bit indicates a reset from the watchdog timer 1. in case of a reset time out due to this reset factor, irrst along with this bit will be "1" . wdg1 watchdog timer 1 reset 0 undetected 1 detected this bit will be cleared when it is read out . the cpua r register also has a flag that indicates a reset factor generation by the watchdog reset 1. the bit will not be cleared when the cpuar register is read. [b it4 ] wdg0 (watchdog reset 0) : watchdog reset 0 this bit indicates a reset from the watchdog timer 0 . in case of a reset time out due to this reset factor, irrst along with this bit will be "1" . wdg0 watchdog timer 0 reset 0 undetected 1 detected this bit will be cleared when it is read out . [b it1 ] scrt (flash security violation) : flash security violation reset this bit indicates that a flash memory security violation reset has occurred. in case of a reset time out due to this reset factor, irrst along with this bit will be "1" . scrt flash security violation reset 0 undetected 1 detected this bit w ill be cleared when it is read out . [b it0] srst (software reset) : software reset this bit indicates a reset by writing "1" to the rstcr:srst bit. in case of a reset time out due to this reset factor, irrst along with this bit will be "1" . srst software r e s e t 0 undetected 1 detected this bit will be cleared when it is read out . mb91590 series mn705-00009-3v0-e 270
chapter 7: reset 4 . r egisters fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 9 4.2. reset control register : rstcr (reset control register) the bit configuration of the reset control register is shown. this register controls various types of reset issuance . ? rstcr : address 0481 h ( access : byte , h alf - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rdly[2:0] reserved srst initial value 1 1 1 0 0 0 0 0 attribute r,w r,w r,w r / w r / w r / w r / w r,w [b it7 to bit 5] rdly[2:0] (reset delay) : reset issue delay the se bits set th e reset timeout value. a reset will be issued if all bus operations become idle or the timer has counted to the reset timeout by this bit after a reset factor has been detected. (the latter is a case of irregular reset). these bits can be written for only once after the reset. rdly[2:0] reset timeout value 000 pclk 2 cycle s 001 pclk 4 cycle s 010 pclk 8 cycle s 011 pclk 16 cycle s 100 pclk 32 cycle s 101 pclk 64 cycle s 110 pclk 128 cycle s 111 pclk 256 cycle s ( initial value ) [b it0 ] srst (software reset) : software reset you will be able to generate a software reset request by reading rstcr after writing "1" to this bit. after you have written "1" to this bit, any values written to rstcr will be ignored until a reset is ge nerated, which means that register values cannot be changed. in the rstcr reading in the debugging state, reset is not generated. srst software r e s e t 0 no output (initial value) 1 the set request is output by rstcr reading. mb91590 series mn705-00009-3v0-e 271
chapter 7: reset 4 . registers fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 10 4.3. cpu abnormal o peration regist er : cpuar (cpu abnormal operation register ) the bit configuration of the cpu a bnormal o peration register is shown. this register indicates the status and settings associated with the abnormal operation of cpu . ? cpuar : address 051a h ( access : byte , h alf - wo rd , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pstre reserved pmdf pstf hwdf initial value 0 0 0 0 * * * * attribute r/w r0,wx r0,wx r0,wx r x, wx r(rm1),w r(rm1),w r(rm1), w * : it will be initialized to "0" by rstx pin asserts (including simultane ous assert with nmix) . it will not be initialized by the other reset factors. [b it7 ] pstre (illegal pll - run to standby reset enable) : illegal standby mode transition detection reset enable this bit configures whether or not to issue a reset when a watc h mode or a stop mode transition has been detected (illegal standby mode transition) with the pll clock selected as a clock source. when enabled, a reset due to the illegal standby mode transition detection factor will be generated at a transition from the pll - run state to watch mode or stop mode. pstre description 0 reset will not be generated (initial value) 1 reset generation enabled note : when you set this bit, make sure to clear the pstf bit by writing "0" to the pstf bit before setting this bit. if you set this bit before clearing the pstf bit, a reset may be generated since the value of the pstf bit after the power - on reset is indefinite. note: when the ocd tool is connected, and the high - speed uart mode and phase modulation uart mode are selected, an illegal standby mode transition detection reset will not be generated. mb91590 series mn705-00009-3v0-e 272
chapter 7: reset 4 . registers fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 11 [b it 2] p md f (pll mode main clock down detection flag) : pll mode main oscillation determination detection flag when the clock supervisor does the main oscillation determination detection when pll output is selected as a clock source, this bit is set. moreover, the source clock is written automatically in main mode (cks= ckm=00), and reset (rst level) is generated at once. if a read - modify - write instruction is executed, "1" will be read out . p m d f read write 0 the main oscillation determination detection is not in pll mode. ( initial value ) clear this bit 1 the main oscillation determination detection is in pll mode. no effect the set factor is given to priority when a set factor and a clear factor are generated at the same time. [b it1 ] pstf (illegal pll - run to standby flag) : illegal standby mode transition detection flag this bit will be set when a watch mode or a stop mode transition has been detected (illegal standby mode tr ansition) with the pll clock selected as a clock source. moreover, the source clock is written automatically in main mode (cks=ckm=00) . when the pstre bit is "1" , reset (rst level) is generated. this bit is cleared by wr i ting "0". if a read - modify - write in struction is executed, "1" will be read out . pstf read write 0 no illegal standby mode transition has been detected clear this bit 1 illegal standby mode transition has been detected. no effect [b it0 ] hwdf (hardware watchdog flag) : hardware watchdog detection flag when a reset factor for the watchdog timer 1 (hardware watchdog) has been detected, this bit will be set. this bit is cleared by writing "0". if a read - modify - write instruction is executed, "1" will be read out . hwdf read write 0 no watchdog timer1 (hardware watchdog) reset factor has been generated. clear this bit 1 watchdog timer1 (hardware watchdog) reset factor has been generated. no effect the set factor is given to priority when a set factor and a clear factor are generated at the same time. note: there is a detection flag also in rstrr:wdg1, and the factor disappears when read once because it is read clear. because cpuar:hwdf is maintained, the factor is maintained until clearing. mb91590 series mn705-00009-3v0-e 273
chapter 7: reset 4 . registers fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 12 4.4. pmu status register : pmustr (power management unit s tatus register) the bit configuration of the pmu status register is shown. this register indicates the pmu status. ? pmustr : address 0590 h ( access : byte , h alf - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pmust reserved ponr_f rstx_f initial valu e 0 0 0 0 0 0 1 * attribute r,w r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r,w r,w * : it will be initialized to "1" by rstx pin asserts (including simultaneous assert with nmix). it will not be initialized by the other reset factors. [bit7] pmust ( power management unit s t atus ) the state immediately before shows information on whether it was a shutdown mode. pmust pmu status 0 operation return from initial state and initialization reset 1 operation return from shutdown mode th is bit is cleared by writing "0". "1" writing is invalid. [bit6 to bit2] reserved "0" is always read. please be sure to write "0". [bit1] ponr_f (power on reset flag) this bit is a power - on reset detection flag. p onr_f power - on reset 0 no detection 1 detection th is bit is cleared by writing "0". "1" writing is invalid. this bit is not initialized in reset factors other than power - on reset. [bit 0 ] rstx_f (resetx input flag) this bit is a n external reset detection flag. rstx _f rstx input reset 0 no detection 1 detection th is bit is cleared by writing "0". "1" writing is invalid. this bit is not cleared by the power - on reset. be sure to use after clear. mb91590 series mn705-00009-3v0-e 274
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 13 5. operation description this section explains each operation of the reset feature of this product. 5.1 . reset level 5.2 . reset factor 5.3 . reset acceptance 5.4 . reset issue 5.5 . reset sequence mb91590 series mn705-00009-3v0-e 275
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 14 5.1. reset level the r eset level is explained . the following two levels of resets are available with this product . note: except the registers for debug interface (ocdu), the registers initialized by the reset of both levels are the same for this product. however, there are some registers initialized by the init level instead of the rst level when the ocd tool is connected, and the high speed uart mode and phase modulation uart mode are selected . see "chapter : on chip debugger (ocd)". mb91590 series mn705-00009-3v0-e 276
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 15 5.1.1. initialize reset (init) initialize r eset (init) is explained. it initializes all register settings and the entire hardware. it terminates the cpu programs running, and the program counter will be initialized. all peripheral circuits will be initialized. a m ain oscillation circuit continues to run. if it was inactive, it starts running again. in this case a sub oscillation circuit and , pll become inactive. this reset level is applied at a reset by the following r eset factors. ? irregular reset ? watchdog reset 0, 1 only the followin g register will be initialized by this reset level. ? register of the debug interface (ocdu) there are some registers initialized by the init level instead of the rst level when the ocd too l is connected, and the high - speed uart mode and phase modulation uart mode are selected. see " chapter : on chip debugger (ocd) ". mb91590 series mn705-00009-3v0-e 277
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 16 5.1.2. reset (rst) the r eset (rst) is explained . it initializes th e entire hardware and all registers except the ones initialized only by the initialize reset (init). it terminates the cpu programs running, and the program counter will be initialized. all peripheral circuits will be initialized. when an initialize reset (init) is issued, a reset (rst) is issued at the same time. the re set in the entire document indicates this reset level unless otherwise specified. there are some registers initialized by the init level instead of the rst level when the ocd tool is connected, and the high - speed uart mode and phase modulation uart mode ar e selected. see " chapter : on chip debugger (ocd) ". mb91590 series mn705-00009-3v0-e 278
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 17 5.2. reset factor this section explains each reset factor of this product. 5.2.1 . power - on reset 5.2.2 . rstx pin input 5.2.3 . watchdog reset 0 5.2.4 . watchdog reset 1 5.2.5 . external low - voltage detection reset 5.2.6 . illegal standby mode transition detection reset 5.2.7 . in ternal low - voltage detection reset 5.2.8 . flash security violation reset 5.2.9 . software reset (rstcr:srst) 5.2.10 . recovery from standby (powe r interception) mb91590 series mn705-00009-3v0-e 279
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 18 5.2.1. power -on reset power - on r eset is shown. it is a reset factor generated when detecting the power has turned on. al l resets due to this reset factor are detected as an irregular reset and issue an initialize reset (init). mb91590 series mn705-00009-3v0-e 280
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 19 5.2.2. rstx pin input the rstx p in i nput is shown. it is a hardware reset input from the outside of the device. reset by this reset factor is detected as irregular reset only at the reset timeout or simultaneous assert of the nmix pin . other than the irregular reset dete ction, a reset (rst) will be issued . mb91590 series mn705-00009-3v0-e 281
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 20 5.2.3. watchdog reset 0 the w atchdog r eset 0 is shown. it is a hard ware reset input from the fr81s - core built - in watchdog timer 0 (software watchdog). resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. whether or not an irregular reset has been detected, an initialize reset (init) will be i ssued . mb91590 series mn705-00009-3v0-e 282
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 21 5.2.4. watchdog reset 1 the w atchdog r eset 1 is shown. it i s a hardware reset input from the fr81s - core built - in watchdog timer 1 ( h ardware watchdog). resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. whether or not an irregular reset has been detected, an initialize reset (init) will be issued . mb91590 series mn705-00009-3v0-e 283
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 22 5.2.5. external low -voltage detection res et the e xternal l ow -v oltage d etection r eset is shown. l ow - voltage detection (external voltage) is a hardware reset input from the low - voltage detection circuit located inside of the device. resets due to this reset factor will be detected as an irregular r eset only at the time of reset timeout. other than the irregular reset detection, a reset (rst) will be issued. see " chapter : low voltage detection (external low - voltage detecti on)" for details on voltage detection. mb91590 series mn705-00009-3v0-e 284
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter : reset fujitsu semiconductor confidential 23 5.2.6. illegal standby mode transition detect ion reset the i llegal s tandby m ode t ransition d etection r eset is shown. it is a hardware reset generated when a watch mode or a stop mode transition has been detected (illegal standby mode transition) with the pll clock selected as a clock source. resets d ue to this reset factor will be detected as an irregular reset only at the time of reset ti meout. other than the irregular reset detection, a reset (rst) will be issued mb91590 series mn705-00009-3v0-e 285
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 24 5.2.7. in ternal low -voltage detection reset the i n ternal l ow -v oltage d etection r eset is show n. l ow - voltage detection ( in ternal voltage) is a hardware reset input from the low - voltage detection circuit located inside of the device. the reset from this reset source is detected as irregular reset. after the detection, an initialize reset (init) will be issued. see " chapter : low voltage detection ( in ternal low - voltage detecti on)" for details on voltage detection. mb91590 series mn705-00009-3v0-e 286
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 25 5.2.8. flash security violation reset the flash s ecurity v iolation r eset is shown. it is a reset issued when a violation of flash memory securit y protection has occurred. resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. other than the irregular reset detection, a reset (rst) will be issued . mb91590 series mn705-00009-3v0-e 287
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 26 5.2.9. software reset (rstcr:srst) the s oftware r eset ( rstcr:srst) is shown. it is a software reset generated inside of the device. this reset will be issued when you read rstcr after writing "1" to the bit0: srst bit of the rstcr. resets due to this reset factor will be detected as an irregular reset only at the time of reset timeout. other than the irregular reset detection, a reset (rst) will be issued . [ example ] sample program of a software reset issue ldi #value_of_reset, r0 ; srst bit =1 ldi #_rstcr, r12 ; stb r0, @r12 ; write ldub @r12, r0 ; read (generation of a software reset request) mov r0, r0 ; dummy processing for pipeline adjustment nop ; dummy processing for pipeline adjustment mb91590 series mn705-00009-3v0-e 288
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 27 5.2.10. recovery from standby (power interception) recovery from standby (power interception) is shown. on m ajority of the block including microcontroller, the operation corresponding to the power - on reset is executed by the start from the standby. however, power - on reset factor is always at the power - on block, the d etection is not displayed in the reset source register (rstrr) . the factors are displayed in the pmu status register (pmustr), and please confirm this register, when the microcontroller reactivates. reset by this reset factor issues the initialization reset (init). mb91590 series mn705-00009-3v0-e 289
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 28 5.3. reset acceptance this section explains the acceptance processing of each reset factor. 5.3.1 . generation of reset re q uest 5.3.2 . acceptance of reset re q uest 5. 3.3 . reset issue delay counter 5.3.4 . irregular reset mb91590 series mn705-00009-3v0-e 290
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 29 5.3.1. generation of reset re quest the g eneration of a r eset req uest is shown. a reset request will be generated when at least one reset factor is retrieved. the reset request will be notified to the internal bus controller, and the following processing will be executed. ? stop the cpu programs running (same processing as sleep mode) ? acquire bus control right of the on - chip bu s ? confirm that idle request has been notified to all busses mb91590 series mn705-00009-3v0-e 291
chapter 7: reset 5 . operatio n description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 30 5.3.2. acceptance of reset re quest acceptance of a r eset req uest is shown. once all processing for the reset request completes, the component where a reset is issued accepts the reset request and issue s a reset of which level corresponds to the reset factor. if the reset issue delay counter overflows (= reset timeout occurs), the reset request is accepted without waiting for the completion of reset request processing, and an irregular reset will be issu ed. mb91590 series mn705-00009-3v0-e 292
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 31 5.3.3. reset issue delay counter the r eset issue d elay c ounter is shown. as soon as a reset request is generated, the 8 - bit reset issue delay counter starts counting. if the delay cycle specified by the bit7 to bit5: rdly[2:0] bits of the rstcr register has elapsed without a reset being issued and the counter overflows (= reset timeout occurs), an irregular reset will be issued. the rdly[2:0] bit of the rstcr will be initialized by a reset. this bit can be rewritten for once only after a reset is released. if the delay cycle is set for a short time, it is more likely to generate an irregular reset. if the delay cycle is set for a long time, it might take a long time for a reset to be issued since the generation of a reset factor. mb91590 series mn705-00009-3v0-e 293
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 32 5.3.4. irregular reset the i rregula r r eset is shown. if a reset is issued without confirming the completion of reset request processing, it will generate an irregular reset. once an irregular reset is generated, the following processing will be executed. ? regardless of the type of reset fact or, initialize reset (init) will be issued. ? set the bit7: irrst bit of rstrr register to "1". when an irregular reset occurs, there is no guarantee that memory contents were not destroyed by the reset since a bus access may have been executed at the time of inputting the reset. the irregular reset does not necessarily mean that the memory contents were destroyed, but how the bus access was executed cannot be identified. mb91590 series mn705-00009-3v0-e 294
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 33 5.4. reset issue a reset will be issued after a reset request has been accepted. this section explains each type of reset issue. 5.4.1 . power - on reset (sinit) 5.4.2 . initialize reset (init) 5.4.3 . reset (rst) mb91590 series mn705-00009-3v0-e 295
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 34 5.4.1. power -on reset (sinit) the power - on reset (sinit) is shown . the power - on reset (sinit) will be issued first for power - on reset , internal low - voltage detection, or simultaneous assert of rstx and nmix . this reset is exclusiv ely used for initializing the indefinite state of division circuits and so on . while this reset is being issued, all clocks become inactive. when this reset is issued, an initialize reset (init) and a reset (rst) will be always issued at the same time. thi s reset initializes the clock control register. this reset involves the wait time of main clock oscillation to be stabilized. along with the control register initialization, the oscillation stabilization wait time is 2 15 m ain clock cycle. table 5-1 oscillation stabilization wait time (sinit) type main clock oscillation stabilization wait time power - on reset 2 15 main clock cycle internal low - voltage detection 2 15 main clock cycle s imultaneous assert of rstx and nmix 2 15 main clock cycle note: the oscillation stabilization wait time shown in the above table does not include the regulator stabilization wait time and flash stabilization wait time associated with the power - on and voltage restore. these stabilization wait tim e (150s to 1850s and maximum 80s) are needed at power - on reset. figure 5-1 oscillation stabilization wait time for power - on reset o scillation stabilization wait time step - down circuit 150 to1850s (pclk (1046+3) cycles) max.80s circu it stabilization wait time stabilization wait time ocdu chip reset s equence cpu operation c lk vcc 2 15 main clock period flash s tep - down mb91590 series mn705-00009-3v0-e 296
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 35 the following describes each reset issue sequence after reset factors of this reset have been released. figure 5-2 power - on reset (sinit) sequence init factor rst oscillation stabilization wait time + (pclk 4 cycles) *: pclk (1026+3) cycles pclk 16 cycles ocdu chip reset sequence* because the clo ck settings register is initializ ed by reset, the per iod of the pe r iphe ral clock (pclk) is 8 times the per iod of the main clo ck (mclk). mb91590 series mn705-00009-3v0-e 297
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 36 5.4.2. initialize reset (init) initialize r eset (init) is shown. if a reset factor of t he initialize reset (init) level occurs, an initialize reset (init) and a reset (rst) will be issued at the same time. this reset is exclusively used for initializing the registers that cannot be initialized by a reset (rst). while this reset is being issu ed, all clocks become active. when this reset is issued, a reset (rst) will be always issued at the same time. although this reset initializes the clock control register, the oscillation of the clock does not change while the main clock (mclk) is oscillati ng. if the main clock is inactive such as in a stop mode, it takes the main clock oscillation stabilization wait time. since the register of the clock control part will be initialized by a reset, the oscillation stabilization wait time is the default value of this product ( 2 15 m ain clock cycle). table 5-2 oscillation stabilization wait time (init) is main clock oscillation inactive before inputting a reset? main clock oscillation stabilization wait time no none yes 2 15 main clock cycle the following describes each reset issue sequence after reset factors of this reset have been released. figure 5-3 initialize reset (init) sequence init factor rst pclk 16 cycles additional oscillation stabilization wait time in the event that main clock oscillation stabilization w ait time is required pclk 4 cycles *: pclk (1026+3) cycles ocdu chip reset sequence* because the clo c k settings register is initiali z ed b y reset, the pe r iod of the pe r iphe r al clo ck (pclk) is 8 times the pe r iod of the main clo c k (mclk) . mb91590 series mn705-00009-3v0-e 298
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 37 5.4.3. reset (rst) the r eset (rst) is shown. if a reset factor that is not the ini tialize reset (init) level occurs, only a reset (rst) will be issued. this reset is used for initializing the entire hardware except some registers (see " 5.1.1 . initialize reset (init) "). while this re set is being issued, all clocks become active. if the main clock is inactive such as in a stop mode before the reset, it takes the main clock oscillation stabilization wait time. since the register of the clock control part will be initialized by a reset, the oscillation stabilization wait time is the default value of this product ( 2 15 m ain clock cycle). table 5-3 oscillation stabilization wait time (rst) is main clock oscillation inactive before inputting a reset ? main clock oscillation stabilization wait time no none yes 2 15 main clock cycle the following describes each reset issue sequence after reset factors of this reset have been released. figure 5-4 reset (rst ) sequence l init factor rst pclk 16 cycles pclk 4 cycles additional oscillation stabilization wait time in the event that main clock oscillation stabilization w ait time is required because the clo c k settings register is initiali z ed b y reset, the pe r iod of the pe r iphe r al clo ck (pclk) is 8 times the pe r iod of the main clo c k (mclk) . mb91590 series mn705-00009-3v0-e 299
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 38 5.5. reset sequence the r eset s equence is shown. this product transits from the initial state to start running the programs and hardware by disappearance of reset factors. a series of operations from this reset to the start of operation is called a reset sequence. this section explains the reset sequence. figure 5-5 reset sequence notes: - if (i) occurs after (vii) or during (v) or (vi), the sequence restarts from (i). - if (i) occurs after (b), the sequence restarts from (i). refer to " figure 2 -1 diagram of device state transitions " in chapter of "clock reset state transitions" for details. - the main clock oscillation stabilization wait time is taken during (iv ). - the main clock oscillation stabilization wait time is taken during (vii), (viii), or (ix) if necessary (cmonr:mcrdy=0). - refer to chapter of "fixedvector function" for details on (x). - at illegal standby mode transition detection reset, the status is a bus idle status after generating reset source, so the status move to (i x). - power - on reset is issued at the recovery from standby (power shutdown) (a). however, because of preventing a reset to following block, the reset without a power - on reset to this block will be masked (b) during the reset period . (1) rtc (only watch mode) (2) e x ternal interrupt block (3) power management unit (4) clock gener a tion block (only sub - clock select ion register) generate reset source (i) power - on reset internal low - voltage detection reset external reset + nmix assert genera te reset source (ii) watchdog reset 1 (hw) watchdog reset 0 (sw) generate reset source (iii) external reset external low - voltage detection reset illegal standby mode transition detection reset software reset flash security violation reset clock supervisor reset generate reset source ( a) recovery reset from standby (power shutdown) mask reset (b) wait for bus idle (vi) wait for bus idle (v) issue power - on reset (iv) issue initialize reset (vii) issue reset (viii) (chip reset sequence) transition of bus control fetch reset vector(x) start the program issue reset (ix) issue initialize reset (d) issue reset (e) (chip reset sequence) release mask of reset (f) reset time out b us idl e reset time out b us idl e release only asynchronous reset relea se synchronous reset mb91590 series mn705-00009-3v0-e 300
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 39 5.5.1. reset cycle the r eset c ycle is shown. after the release of reset factors, the reset request is extended during the 4 p eripheral clock (pclk) cycle. after that, a reset cycle will be maintained by the period of peripheral clock (pclk) 1 6 cycles for each reset level. thus, the minimu m number of issue cycles for each reset is 20 cycles. if it requires the main clock oscillation stabilization wait time, the cycle will be extended for the time required. mb91590 series mn705-00009-3v0-e 301
chapter 7: reset 5 . operation descri ption fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 40 5.5.2. reset release the r eset r elease is shown. once a reset cycle has completed, each reset will be released and each hardware starts running. right after the reset release, the mode control circuit functions as a bus master of on - chip bus . mb91590 series mn705-00009-3v0-e 302
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 41 5.5.3. operating mode fix operating m ode f ix is shown. the mode control circuit as a bus master will notify t he operating mode, which was determined based on the mode setting value acquired, to each hardware component. the n , it will release the bus control of on - chip bus. mb91590 series mn705-00009-3v0-e 303
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 42 5.5.4. transition of bus control transition of b us c ontrol is shown. after the mode control circu it releases the bus control of on - chip bus, the cpu acquires the bus control and starts running bus operations by the cpu . mb91590 series mn705-00009-3v0-e 304
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 43 5.5.5. reset vector fetch reset v ector f etch is shown. after the reset release, the cpu starts fetching the reset vector (at 0x000ffffc). after cpu acquires the bus control, the cpu accesses the reset vector through on - chip bus and retrieves the acquired reset vector to the pc to start running programs. mb91590 series mn705-00009-3v0-e 305
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 44 5.5.6. reset and forced break reset and f orced b reak are shown. if a forced break has occurred during the reset release, it accepts the forced break upon completion of the reset vector fetch. thus, the pc value by the reset vector acquired will be saved at the emulator space side (stored at the e_bpchr,e_bpclr register). mb91590 series mn705-00009-3v0-e 306
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 45 5.6. notes notes are shown. dur ing return form standby watch mode (power shut - down) and standby stop mode (power shut - down), an internal reset is issued. therefore any reset source without power - on reset, internal low - voltage detection reset, reset by simultaneous assert of rstx and nmi x will not be accepted. mb91590 series mn705-00009-3v0-e 307
chapter 7: reset 5 . operation description fujitsu semiconductor limited chapter: reset fujitsu semiconductor confidential 46 mb91590 series mn705-00009-3v0-e 308
chapter 8: dma controller (dmac) 1 . overview fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 1 c hapter : dma controller (dmac) this chapter explains the dma controller (dmac). 1. overview 2. features 3. configuration 4. registers 5. operation 6. dma usage examples code : 08_mb91590_hm_e_dmac_00 5 _201111 27 mb91590 series mn705-00009-3v0-e 309
chapter 8: dma controller (dmac) 1 . overview fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 2 1. overview this section explains the overview of the dma controller (dmac). dmac is the module which performs the dma (direct memory access) transfer. dma transfer controlled by this module enables the high speed transfer of variety of data without any interventions of a cpu, thus increases the system performance. mb91590 series mn705-00009-3v0-e 310
chapter 8: dma controller (dmac) 2 . features fujitsu semiconductor limited chapter : dma controller (dm ac) fujitsu semiconductor confidential 3 2. features this section explains the features of the dma controller (dmac). ? channels : 16 channels ? address space : 32- bit address space (4 gb) ? transfer mode : block/burst transfer ? address update : increment/decrement/fixed (address increment/decrement range : 1, 2, 4) ? transfer size : 8- bit s , 16 - bit s , 32 - bit s ? block size : 1 to 16 ? transfer count : 1 to 65535 ? transfer request : ? software transfer requests ? t ransfer requests by peripheral interrupt (for the transfer request by peripheral interru pt, you should select interrupt by channels. see "chapter : generation and clearing of dma transfer requests".) ? transfer stop request : transfer stop request by interrupts ? reload function : all channels can be specified for reload ? transfer source address r eload ? transfer destination address reload ? transfer count reload ? priority : ? fixed (ch.0 > ch.1 > ch.2 > ch.3 > ch.4 > ch.5 > ch.6 > ch.7 > ch.8 > ch.9 > ch.10 > ch.11 > ch.12 > ch.13 > ch.14 > ch.15 ) ? round robin ? interrupt request : normal completion interru pt requests, abnormal completion interrupt requests, and transfer suspend interrupt requests by transfer stop requests can be generated mb91590 series mn705-00009-3v0-e 311
chapter 8: dma controller (dmac) 3 . configuration fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 4 3. configuration this section explains the block configuration of the dma controller (dmac). figure 3-1 block diagram master interface slave interface data buffer register control read engine and transfer destination write transfer destination determining priorities ? ? ? register ?? ? ?? ? ?? ? ?? ? accept transfer r equest ?? J ??K ?? J ??K ?? J ??K ?? J ??K transfer acceptance/ transfer termination dmac generation and clear circuit of dma transfer request caused by interrupt peripheral interrupt controller interrupt request interrupt clear request cpu flash ram peripheral bus bridge on - chip bus peripheral on - chip bus mb91590 series mn705-00009-3v0-e 312
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 5 4. registers this section explains registers of the dma controller (dmac). table 4-1 register s map address registers register function +0 +1 +2 + 3 0x0c00 dccr0 dma channel control register 0 0x0c04 dcsr0 dtcr0 dma channel status register 0 dma transfer count register 0 0x0c08 dsar0 dma transfer source address register 0 0x0c0c ddar0 dma transfer destination address register 0 0x0c10 dccr1 dma channel control register 1 0x0c14 dcsr1 dtcr1 dma channel status register 1 dma transfer count register 1 0x0c18 dsar1 dma transfer source address register 1 0x0c1c ddar1 dma transfer destination address register 1 0x0c20 dccr2 dma channel control reg ister 2 0x0c24 dcsr2 dtcr2 dma channel status register 2 dma transfer count register 2 0x0c28 dsar2 dma transfer source address register 2 0x0c2c ddar2 dma transfer destination address register 2 0x0c30 dccr3 dma channel control register 3 0x0c34 dcsr 3 dtcr3 dma channel status register 3 dma transfer count register 3 0x0c38 dsar3 dma transfer source address register 3 0x0c3c ddar3 dma transfer destination address register 3 0x0c40 dccr4 dma channel control register 4 0x0c44 dcsr4 dtcr4 dma channel status register 4 dma transfer count register 4 0x0c48 dsar4 dma transfer source address register 4 0x0c4c ddar4 dma transfer destination address register 4 0x0c50 dccr5 dma channel control register 5 0x0c54 dcsr5 dtcr5 dma channel status register 5 dm a transfer count register 5 0x0c58 dsar5 dma transfer source address register 5 mb91590 series mn705-00009-3v0-e 313
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 6 address registers register function +0 +1 +2 + 3 0x0c5c ddar5 dma transfer destination address register 5 0x0c60 dccr6 dma channel control register 6 0x0c64 dcsr6 dtcr6 dma channel status register 6 dma transfer count reg ister 6 0x0c68 dsar6 dma transfer source address register 6 0x0c6c ddar6 dma transfer destination address register 6 0x0c70 dccr7 dma channel control register 7 0x0c74 dcsr7 dtcr7 dma channel status register 7 dma transfer count register 7 0x0c78 dsar 7 dma transfer source address register 7 0x0c7c ddar7 dma transfer destination address register 7 0x0c 8 0 dccr 8 dma channel control register 8 0x0c 84 dcsr 8 dtcr 8 dma channel status register 8 dma transfer count register 8 0x0c 8 8 dsar 8 dma transfer sourc e address register 8 0x0c 8 c ddar 8 dma transfer destination address register 8 0x0c 9 0 dccr 9 dma channel control register 9 0x0c 94 dcsr 9 dtcr 9 dma channel status register 9 dma transfer count register 9 0x0c 9 8 dsar 9 dma transfer source address register 9 0x0c 9 c ddar 9 dma transfer destination address register 9 0x0c a 0 dccr 10 dma channel control register 10 0x0c a4 dcsr 10 dtcr 10 dma channel status register 10 dma transfer count register 10 0x0c a 8 dsar 10 dma transfer source address register 10 0x0c a c dda r 10 dma transfer destination address register 10 0x0c b 0 dccr 11 dma channel control register 11 0x0c b4 dcsr 11 dtcr 11 dma channel status register 11 dma transfer count register 11 0x0c b 8 dsar 11 dma transfer source address register 11 0x0c b c ddar 11 dma tr ansfer destination address register 11 0x0c c 0 dccr 12 dma channel control register 12 mb91590 series mn705-00009-3v0-e 314
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 7 address registers register function +0 +1 +2 + 3 0x0c c4 dcsr 12 dtcr 12 dma channel status register 12 dma transfer count register 12 0x0c c 8 dsar 12 dma transfer source address register 12 0x0c c c ddar 12 dma transfer des tination address register 12 0x0c d 0 dccr 13 dma channel control register 13 0x0c d4 dcsr 13 dtcr 13 dma channel status register 13 dma transfer count register 13 0x0c d 8 dsar 13 dma transfer source address register 13 0x0c d c ddar 13 dma transfer destination a ddress register 13 0x0c e 0 dccr 14 dma channel control register 14 0x0c e4 dcsr 14 dtcr 14 dma channel status register 14 dma transfer count register 14 0x0c e 8 dsar 14 dma transfer source address register 14 0x0c e c ddar 14 dma transfer destination address reg ister 14 0x0c f 0 dccr 15 dma channel control register 15 0x0c f4 dcsr 15 dtcr 15 dma channel status register 15 dma transfer count register 15 0x0c f 8 dsar 15 dma transfer source address register 15 0x0c f c ddar 15 dma transfer destination address register 15 0x0df4 reserved reserved dnmir d i lv r dma transfer suppression nmi flag register dma transfer suppression interrupt level register 0x0df8 dmacr dma control register 0x0df c reserved reserved mb91590 series mn705-00009-3v0-e 315
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 8 4.1. dma control register: dmacr (dma control register) this sectio n explains the dma control register (dmacr). the dma control register is a 32 - bit register to control the entire dmac (all channels). this register must be accessed as a 32 - bit data. ? dmacr : address 0df8 h ( access : word ) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 dme reserved initial value 0 0 0 0 0 0 0 0 attribute r/w r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 reserved initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w 0 r0,w0 r0,w0 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 at reserved initial value 0 0 0 0 0 0 0 0 attribute r/w r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 reserved initial value 0 0 0 0 0 0 0 0 att ribute r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 mb91590 series mn705-00009-3v0-e 316
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dm ac) fujitsu semiconductor confidential 9 [ bit31 ] dme (dma enable) : dma o peration enabled this bit controls the operation of the entire dmac. when this bit is "0", a dma transfer will not be performed even if operation of each channel is en abled. when this bit is "1", operat ions according to the settings for each channel are performed . if "0" is written while a dma transfer is in progress, the transfer is stopped in blocks specified in dccr n :blk. dme dma operation enable 0 dma operation dis abled (initial value) 1 dma operation enable d [b it30 to bit 16 ] reserved always write "0" to these bits. the read value is "0". [b it15 ] at (arbitration type) : priority setting this bit configures how to determine priority for each channel. if the priority is set to "fixed" (at = 0), ascending order, ch.0 > ch.1 > ch.2 > ch.3, is taken. if the priority is set to "round robin" (at = 1), dmac makes the priority of the channel which started the transfer the lowest and raises the priority of following channel s one by one. the decision o n priority is made on each transfer of a block unit specified in dccr n :blk regardless of the priority setting. at priority setting 0 fixed (initial value) 1 round robin [b it1 4 to bit 0] reserved always write "0" to these bits . the read value is "0". mb91590 series mn705-00009-3v0-e 317
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 10 4.2. dma channel control register 0 to 15: dccr0 to 15 (dma channel control register 0 to 15) this section explains the bit configuration for dma channel control register 0 to 15 (dccr0 to 15). dma channel control registers are 32 - bit registers to control the operation of dmac channels, which exists independently for each channel. this register must be accessed as a 32 - bit data. ? dccr0 to 15 : address base + 0000 h ( access : word ) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 ce rese rved aie sie nie initial value 0 0 0 0 0 0 0 0 attribute r,w r0,w0 r0,w0 r0,w0 r0,w0 r/w r/w r/w bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 reserved rs[1:0] reserved tm[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r0,w0 r/w r/w r0,w0 r 0,w0 r/w r/w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 st sar sac[1:0] dt dar dac[1:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 tcr reserved ts[1:0] blk[3:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r0,w0 r/w r/w r/w r/w r/w r/w mb91590 series mn705-00009-3v0-e 318
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 11 [b it31 ] ce (channel enable) : channel operation enabled this bit controls the operation of the channels. if the request source is set to "software", writing "1" to this bit starts a dma transfer according to the configuration. in this case, the ce bit is automatically cleared when the transfer according to the transfer request completed. if the request source is other than software, writing "1" to this bit makes channel operation enabled. after enabling operation, a dma transfer starts when the corresponding transfer request is detected. in case of a request other than software, the ce bit will not be automatically cleared if transfer count reload (dccr n: tcr) is specified. when transfer co unt reload is disabled, the ce bit will be cleared when all transfers are finished. if "0" is written while the operation is going on rega rdless of the request source, stop transfer in blocks specified in dccr n: blk. when writing "1" again and detecting a new transfer request, the operation restarts. ce channel operation enabled 0 disabled (initial value) 1 enabled [b it30 to bit 27 ] reserved always write "0" to th ese bit s. the read value is "0". [b it26 ] aie (abnormal c ompletion interrupt enable) : abnorma l completion interrupt enabled this bit controls the generation of interrupts when setting the prohibited values to the dma channel control register (dccr). the items not allowed to set to registers are listed below. ? transfer mode : dccr n: tm = 10 b ? transf er s ource address count : dccr n: sac = 10 b ? transfer d estination address count : dccr n: dac = 10 b ? transfer size : dccr n: ts = 11 b ? demand transfer mode by software request : dccr n: rs = 00 b and dccr n: tm = 11 b as f or the interrupt factor, refer to the st atus register (dcsr n ). aie abnormal completion interrupt enabled 0 disabled (initial value) 1 enabled [b it25 ] sie (stop interrupt enable) : transfer suspend interrupt enabled by transfer stop requests this bit controls the generation of interrupts when a dma transfer is suspended by a transfer stop request from the transfer request source. as f or the interrupt factor, refer to the status register (dcsr n ). sie transfer suspend interrupt enabled 0 disabled (initial value) 1 enabled mb91590 series mn705-00009-3v0-e 319
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (d mac) fujitsu semiconductor confidential 12 [b it24 ] nie (norm al c ompletion interrupt enable) : normal completion interrupt enabled this bit controls the generation of interrupts when completing dma transfers successfully. after completing transfers as many times as set by transfer count (dtcr n: dtc) or when writing " 1" to the corresponding channel's dccr n: ce bit at the time the transfer count is "0", the operation will complete normally. as f or the interrupt factor, see the status register (dcsr n ). nie normal completion interrupt enabled 0 disabled (initial value) 1 enabled [b it23 , bit 22] reserved always write "0" to these bit s. the read value is "0". [b it21 , bit 20] rs [1:0] (request source) : dma transfer request source these bits select the transfer request source for the channel. rs[1:0] dma transfer request so urce 00 software (initial value) 01 interrupts 10 reserved ( setting is prohibited ) 11 reserved ( setting is prohibited ) [b it19 , bit 18] reserved always write "0" to these bits. the read value is "0". [b it17 , bit 16 ] tm [1:0] (transfer mode) : transfer mo de these bits specify the dma transfer mode . tm[1:0] transfer mode 00 block transfer (initial value) 01 burst transfer 10 reserved ( setting is prohibited ) 11 reserved ( setting is prohibited ) [b it15 ] st (source type) : transfer source type the setting values are different depending on the combinations of dma transfer request source (dccr : rs[1:0]), transfer source address (dsar), and transfer destination address (ddar). as f or the setting, see " ? setting the st b it (transfer sou rce type) and dt b it (transfer destination type) ". st transfer source type 0 see " ? setting the st b it (transfer source type) and dt b it (transfer destination type) ". 1 mb91590 series mn705-00009-3v0-e 320
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 13 [b it14 ] sar (source address reload) : transfer source address reload this bit specifies the transfer source address register reload. when specifying a reload, the transfer source address register value is returned to the initial value at the end of the transfer. when disabling a reload, the transfer source ad dress register will point to the next access address t o the last address at the end of the transfer. sar transfer source address reload specified 0 reload disabled (initial value) 1 reload [b it13 , bit 12] sac [1:0] (source address count) : transfer source address count these bits specify the address update once for each transfer of the transfer source address. the update values when specifying "increment/decrement" will be one of the values, 1, 2, 4 depending on the transfer size (dccr n: ts). sac[1:0] tran sfer source address count 00 address increment (initial value) 01 address decrement 10 reserved ( setting is prohibited ) 11 address fixed [b it11 ] dt (destination type) : transfer destination type the setting values are different depending on the combinations of dma transfer request source (dccr . rs[1:0]), transfer source address (dsar), and transfer destination address (ddar). as f or the setting, see " ? setting the st b it (transfer source type) and dt b it (transfer destination t ype) ". dt transfer destination type 0 see " ? setting the st b it (transfer source type) and dt b it (transfer destination type) ". 1 [b it10 ] dar (destination address reload) : transfer destination address reload this bit specif ies the transfer destination address register reload. when specifying a reload, the transfer destination address register value is returned to the initial value at the end of the transfer. when disabling a reload, the transfer destination address register will point to the next access address t o the last address at the end of the transfer. dar transfer destination address reload specified 0 reload disabled (initial value) 1 reload mb91590 series mn705-00009-3v0-e 321
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 14 [b it9 , bit 8] dac [1:0] (destination address count) : transfer destination address count these bits specify the address update once for each transfer of the transfer destination address. the update values when specifying "increment/decrement" will be one of the values, 1, 2, 4 depending on the transfer size (dccr n: ts). dac[1:0] transfer destination address count 00 address increment (initial value) 01 address decrement 10 reserved ( setting is prohibited ) 11 address fixed [b it7 ] tcr (transfer count reload) : transfer count reload this bit specifies the transfer count registe r reload. when specifying a reload, the transfer count register value is returned to the initial value at the end of the transfer. if the transfer request source is set other than "software", dccr n: ce bit will not be cleared at the end of the transfer and the operation will go into the transfer request wait state. when disabling a reload, the transfer count register value at the end of the transfer will point to "0". in this case, dccr n: ce bit will be cleared at the end of the transfer regardless of the transfer request source. tcr transfer count reload 0 reload disabled (initial value) 1 reload [b it6 ] reserved always write "0" to this bit. the read value is "0". [b it5 , bit 4] ts [1:0] (transfer size) : transfer size these bits specify the transfer size. dma transfers will be performed once with the bit width specified here. ts[1:0] transfer size 00 8 - bit :byte (initial value) 01 16 - bit :halfword 10 32 - bit :word 11 reserved ( setting is prohibited ) set values to dsar n and ddar n registers so as not to ca use a misalignment for the transfer size specified in these bits. mb91590 series mn705-00009-3v0-e 322
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 15 [b it3 to bit 0] blk [3:0] (block size) : block size these bits specify the block size. 1 block transfer will be repeated for the number of blocks of the transfer size specified with dccr n: ts bit. blk[3:0] block size 0000 once (initial value) 0001 twice 0010 3 times 0011 4 times 0100 5 times 0101 6 times 0110 7 times 0111 8 times 1000 9 times 1001 10 times 1010 11 times 1011 12 times 1100 13 times 1101 14 times 1110 15 times 1 111 16 times mb91590 series mn705-00009-3v0-e 323
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 16 4.3. dma channel status register 0 to 15 : dcsr0 to 15: (dma channel status register 0 to 15 ) this section explains the bit configuration for dma channel status register 0 to 15 (dc s r0 to 15) . these registers are 16 - bit registers to indicate the status for each dmac channel, which exist independently for each channel. these registers must be accessed as a 16 - bit data. ? dcsr0 to 15 : address base + 0004 h ( access : half - word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ca reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 reserved ac sp nc initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r0,w0 r0,w0 r0,w0 r0,w0 r,w r,w r,w [b it15 ] ca (channel active) : c hannel active this bit indicates the operation of the channels. writing "1" to the corresponding dccr n: ce bit for the channel makes it in the operating state. completing transfers for as many times as set transfer count or writing "0" to dccr n: ce makes the operation stop. writing this bit is ignored . ca channel operating state 0 stop state (initial value) 1 channel operating [bit14 to bit 3] reserved always write "0" to these bits. the read value is "0". [b it2 ] ac (abnormal completion) : abnormal completion state this bit indicates that a prohibited value has been set to the dma channel control register (dccr). the items not allowed to set to registers are listed below. ? transfer mode : dccr n: tm = 10 b ? transfer source address count : dccr n: sac = 10 b ? tran sfer destination address count : dccr n: dac = 10 b ? transfer size : dccr n: ts = 11 b ? demand transfer mode by software request : dccr n: rs = 00 b and dccr n: tm = 11 b mb91590 series mn705-00009-3v0-e 324
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 17 when having allowed the abnormal completion interrupt (dccr n: aie), writing "0" to this bit clears the interrupt. writing "1" to this bit is ignored . make sure to clear this bit before enabling dma operation. this bit will not be cleared automatically. ac abnormal completion state 0 abnormal completion undetected (initial value) 1 abnormal com pletion [b it1 ] sp (stop) : transfer suspen sion state by the transfer stop request this bit indicates that a dma transfer has been suspended by a transfer stop request from the transfer request source. when having allowed the transfer suspen sion interrupt (dccr n: sie), writing "0" to this bit clears the interrupt. writing "1" to this bit is ignored . make sure to clear this bit before enabling dma operation. this bit will not be cleared automatically. sp transfer suspend state 0 transfer suspend undetected (initial value) 1 transfer suspend [b it0 ] nc (normal completion) : normal completion state this bit indicates that dma transfer has been completed successfully. after completing transfers as many times as set by transfer count or when writing "1" to the corresponding channel's "dccr n: ce" bit at the time the transfer count is "0", the operation will complete normally. when having allowed the normal completion interrupt (dccr n: nie), writing "0" to this bit clears the interrupt. writing "1" to this bit is i gnored . make sure to clear this bit before enabling dma operation. this bit will not be cleared automatically. nc normal completion state 0 normal completion undetected (initial value) 1 normal completion mb91590 series mn705-00009-3v0-e 325
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 18 4.4. dma transfer count register 0 to 15 : dtcr0 to 15: (dma transfer count register 0 to 15 ) this section explains the bit configuration for dma transfer count register 0 to 15 (d t cr0 to 15) . these registers are 16 - bit registers to indicate the transfer count for each dmac channel, which exist independent ly f or each channel. these registers must be accessed as a 16 - bit data. ? dtcr0 to 15 : address base + 0006 h ( access : half - word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dtc[15:8] initial value 0 0 0 0 0 0 0 0 attribute r,w r,w r,w r,w r,w r,w r,w r,w bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 dtc[7:0] initial value 0 0 0 0 0 0 0 0 attribute r,w r,w r,w r,w r,w r,w r,w r,w [b it15 to bit 0] dtc (dma transfer count) : dma transfer count these registers indicate the number of transfer times. dmac decreases a transefer count at the end of each block transfer and stops the transfer when the transfer count becomes "0". if "0" is set for transfer count, transfer will not be performed. also, the dedicated reload register is provided. if dccr n: tcr is "1 ", the value is returned to the initial value after data transfer. mb91590 series mn705-00009-3v0-e 326
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 19 4.5. dma transfer source register 0 to 15 : dsar0 to 15 : (dma source address register 0 to 15 ) this section explains the bit configuration for dma transfer source register 0 to 15 (d sa r0 to 15) . these registers are 32 - bit registers to indicate the transfer source address of each dmac channel, and each channel has these registers separately. this register must be accessed as a 32 - bit data. ? dsar0 to 15 : address base + 0008 h ( access : word) bit 31 b it 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 dsa[31:24] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 dsa[23:16] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dsa[15:8] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 dsa[7:0] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w [b it31 to bit 0] dsa [31:0] (dma source address) : dma transfer source address these registers indicate the transfer source address. if an increment or a decrement is set by dccr n: sac, the address is updated according to the transfer size (dccr n: ts). also, the dedicated reload register is provided. if dccr n: sar is "1", the value is returned to the initial value after data transfer. set a value in these registers not to cause a misalignment against the transfer size to be set by dccr n: ts . if the dma transfer request source has a peripheral interrupt (dccr : rs[1:0]=01), at least either the transfer source address (dsar) or the transfer destination address (ddar) must be within the address range of peripheral under control of 16 - bit peripher al bus or 32 - bit peripheral bus. for details, see " ? setting the st mb91590 series mn705-00009-3v0-e 327
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 20 b it (transfer source type) and dt b it (transfer destination type) ". mb91590 series mn705-00009-3v0-e 328
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma control ler (dmac) fujitsu semiconductor confidential 21 4.6. dma transfer destination register 0 to 15 : ddar0 to 15 (dma destination address register 0 to 15) this section explains the bit configuration for dma transfer destination register 0 to 15 (d da r0 to 15) . these registers are 32 - bit registers to indicate the transfer destination address of each dmac channel, and each channel has these registers sepa rately. these registers must be accessed as a 32 - bit data. ? ddar0 to 15 : address base + 000c h ( access : word) bit 31 bit 30 bit 29 bit 28 bit 27 bit 26 bit 25 bit 24 dda[31:24] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w bit 23 bi t 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 dda[23:16] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 dda[15:8] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 dda[7:0] initial value x x x x x x x x attribute r,w r,w r,w r,w r,w r,w r,w r,w [b it 31 to bit 0] dda [31:0] (dma destination address) : dma transfer destination address these registers indicate the transfer destination address. if an increment or a decrement is set by dccr n: dac, the address is updated according to the transfer size (dccr n: ts). also, the dedicated reload register is provided. if dccr n: dar is "1", the value is returned to the initial v alue after data transfer. set a value in these registers not to cause a misalignment against the transfer size to be set by dccr n: ts. if the dma transfer request source has a peripheral interrupt (dccr n: rs[1:0]=01), at least either the transfer source address (dsar) or the transfer destination address (ddar) must be within the address range of peripheral under control of 16 - bit peripheral bus or 32 - bit peripheral bus. for details, see " ? setting the st mb91590 series mn705-00009-3v0-e 329
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 22 b it (transfer source type) and dt b it (transfer destination type) ". mb91590 series mn705-00009-3v0-e 330
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 23 4.7. dma transfer suppression nmi flag register : dnmir (dma -halt by nmi register) this section explains the bit configuration for dma transfer suppression nmi flag register ( dnmir ). this register is 8 - bit register to sup press dma transfer by the user nmi. this register must be accessed as a 8- bit data. ? dnmir : address 0df6 h ( access : byte) bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 nmih reserved nmihd initial value 0 0 0 0 0 0 0 0 attribute r,w r0,w0 r0,w0 r0,w0 r0,w0 r0 ,w0 r0,w0 r/w [b it7 ] nmih (nmi halt) : dma suppression flag (by nmi factor) if the nmihd bit is "0", this flag shows an occurrence of the user nmi request. the "h" level of nmi is detected, and this bit is set to "1". to restart dma transfer, set this bit to "0". writing "1" to this bit is ignored . nmih dma suppression flag 0 dma transfer is not suppressed. (initial value) 1 the dma transfer has been stopped by user nmi. [b it6 to bit 1] reserved always write "0" to th ese bit s. the read value is "0". [b it0 ] n mih d (nmi halt disable ) : dma s uppression control (by nmi factor) the control bit that stops dma transfer if a user nmi request is generated. if an nmi occurs when this bit is "0", the dmac does not restart a new dma transfer. during dma transfer, th e controller stops the current dma transfer when a block unit transfer has completed. nmihd dma suppress ion control 0 stops the dma transfer by the user nmi. (initial value) 1 does not stop the dma transfer by the user nmi. mb91590 series mn705-00009-3v0-e 331
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma contr oller (dmac) fujitsu semiconductor confidential 24 4.8. dma transfer suppression lev el register : dilvr (dma - halt by interrupt level register) this section explains the bit configuration for dma transfer suppress ion level register (d ilvr ). this register is 8 - bit register to control the dma transfer suppression by peripheral interrupts. t his register must be accessed as a 8 - bit data. ? dilvr : address 0df7 h ( access : byte) bit7 bit6 bit5 bit4 bit3 bit2 bit 1 bit0 reserved lvl4 lvl[3:0] initial value 0 0 0 1 1 1 1 1 attribute r0,w0 r0,w0 r0,w0 r1,wx r/w r/w r/w r/w [b it7 to bit 5] reserve d always write "0" to th ese bit s. the read value is "0". [b it4 to bit 0] lvl [4:0] (level) : dma suppress ion interrupt level these bits set an interrupt level for suppression of dma transfer. if a peripheral interrupt having an interrupt level higher than th e one specified by this register occurs, the dma transfer is suppressed. lv l4 is fixed to "1", but lvl[3:0] can be set to any level. lvl[4:0] dma suppress ion control 11111 suppresses the dma transfer when any peripheral interrupt request is issued. (initi al value) 11110 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 e h is issued. 11101 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 d h is issued. 11100 suppresses th e dma transfer when a peripheral interrupt request having a level higher than 1 c h is issued. 11011 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 b h is issued. 11010 suppresses the dma transfer when a peripher al interrupt request having a level higher than 1 a h is issued. 11001 suppresses the dma transfer when a peripheral interrupt request having a level higher than 19 h is issued. 11000 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 8 h is issued. 10111 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 7 h is issued. 10110 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 6 h is issue d. mb91590 series mn705-00009-3v0-e 332
chapter 8: dma controller (dmac) 4 . registers fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 25 lvl[4:0] dma suppress ion control 10101 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 5 h is issued. 10100 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 4 h is issued. 10011 suppresses the dm a transfer when a peripheral interrupt request having a level higher than 1 3 h is issued. 10010 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 2 h is issued. 10001 suppresses the dma transfer when a peripheral i nterrupt request having a level higher than 1 1 h is issued. 10000 does not suppress the dma transfer when a peripheral interrupt request is issued. mb91590 series mn705-00009-3v0-e 333
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 26 5. operation this section explains the o peration of the dma controller (dmac) . ? configuration the following explains the setting items common to all channels and the items to be set separately for each channel. ? common items for all channels ? 5.1 dma o peration e nable ? explains the register settings for the enti re dmac control. mb91590 series mn705-00009-3v0-e 334
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma con troller (dmac) fujitsu semiconductor confidential 27 5.1. dma o peration e nable this section explains the dma operation enable of the dma controller (dmac) . the entire dmac operation can be controlled using the dmacr : dme . ? dma operation disabled (dmacr : dme = 0) ? dma operation enabled (dmacr : dme = 1) ? channel p riority a channel priority can be set by the dmacr : at . ? fixed priority (dmacr : at = 0) ? round robin (dmacr : at = 1) ? dma t ransfer s uppression s etting for i nterrupt o ccurrence the dma transfer suppression control during user nmi occurrence can be set b y the dnmir : nmihd . ? stops dma transfer by the user nmi. (dnmir : nmihd = 0) ? does not stop dma transfer by the user nmi. (dnmir : nmihd = 1) also, an interrupt level, which precedes the dma transfer when an interrupt occurs, can be set by dilvr:lvl. allowed int errupt levels are 0x1f to 0x10. mb91590 series mn705-00009-3v0-e 335
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 28 5.2. separate items for each channel this section explains the separate items for each channel of the dma controller (dmac) . the following explains both the items to be set separately for each channel and the register setup proce dure. ? register s etup p rocedure the channel registers must be set in the following procedure. when you set the dccr n: ce bit to "1", be sure to set the dtcr n to 1 or a higher value. 1. clear the dccr n: ce bit to disable the channel operation. 2. clear each bit of d csr n register to initialize the channel status flag. 3. set the transfer source address (to be used when the transfer starts) in the dsar n register. 4. set the transfer destination address (to be used when the transfer starts) in the ddar n register. 5. set the tran sfer count in the dtcr n register. this count must be 1 or a larger value. 6. if transfer is started by a peripheral interrupt, the occurrence of each peripheral interrupt must be enabled and the icsel and iorr registers must be set. ( see the " chapter : generat ion and clearing of dma transfer requests" about the icsel and iorr registers.) 7. set the dccr n register. during this time, the channel operation is enabled when the dccr n: ce bit is set. figure 5-1 channel register setup procedure 6. settings for activation by interrupt end settings start settings 1. clear dccrn:ce bit 3. set dsarn 4. set ddarn 5. set dtcrn 7. set dccrn 2. clear dcsrn to the initial state mb91590 series mn705-00009-3v0-e 336
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 29 ? transfer s ource a ddress and the t ransfer d estination a ddress s etting set the transfer source address (to be used when the transfer starts) using the dsar n: dsa . set the tran sfer destination address (to be used when the transfer starts) using the ddar n: dda . align the transfer source and destination addresses based on the transfer size (ddcr n :ts), and ignore the lower 1 bit or lower 2 bits for 16 - bit or 32 - bit transfer size res pectively. ? transfer c ount s etting set the number of times of block transfer (repeated to the end of transfer) using the dtcr n .dtc . the transfer count can be 1 to 65535 times. the dmac transfers data (1 block data), whose length in bytes is set by the trans fer size and block size (see " ? transfer s ize and b lock s ize s etting ") for the specified number of times. ? channel o peration e nable set the channel operation control using the dccr n: ce . ? disable the channel operation (dccr n: ce = 0) ? enable the channel operation (dccr n: ce = 1) when the software is selected at the transfer request source and when the dccr n: ce bit is set, the channel operation is enabled and data transfer is started. ? interrupt p ermission s etting enable an interrupt during abnormal completion, using the dccr n: aie . ? disable an abnormal completion interrupt (dccr n: aie = 0) ? enable an abnormal completion interrupt (dccr n: aie = 1) using the dccr n: sie, enable an interrupt to occur if data transfer is suspended by a transfer stop request. ? disable a transfer suspend interrupt during detection of transfer stop request (dccr n: sie = 0) ? enable a transfer suspend interrupt during detection of transfer stop request (dccr n: sie = 1) enable an interrupt during normal completion, using the dccr n: nie . ? disable a normal completion interrupt (dccr n: nie = 0) ? enable a normal completion interrupt (dccr n: nie = 1) ? transfer r equest so urce setting set the transfer request source to accept a transfer request using the dccr n: rs . ? request by software (dcc rn: rs = 00) ? request by an interrupt (dccr n: rs = 01) ? transfer m ode s etting set the dma transfer mode using the dccr n: tm . ? block transfer (dccr n: tm = 00) ? burst transfer (dccr n: tm = 01) mb91590 series mn705-00009-3v0-e 337
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma c ontroller (dmac) fujitsu semiconductor confidential 30 ? setting the st b it (transfer source type) and dt b it (transfer destinatio n type) set them by following the table definition below. the dma transfer is not supported in combination (5). table 5-1 st bit (transfer source type) and dt bit (transfer destination type) setting combination of transfer request source, transfer source, and transfer destination dma transfer support st and dt bit setting transfer request source (dccr n: rs[1:0]) transfer source (dsar) transfer destination (ddar) (1) request by software (dccr n : rs [1:0] = 00) an y combination supported st= 0 , dt= 0 ( 2 ) peripheral interrupt (dccr n: rs [1:0] = 01) supported st= 1 , dt= 0 ( 3 ) supported st= 0 , dt= 1 ( 4 ) supported st= 0 , dt= 1 (5) not supported - : address range of the peripheral under control of 16 - bit peripheral bus or 32 - bit peripheral bus : other address range if the st and dt bits are set in a combination other than above, the interrupt may not be cleared automatically after occurrence of the dma transfer request. ? transfer a ddress r eload s etting using the dccr n: sar, set the reload control of transfer source address at the end of transfer. ? the transfer source address is not reloaded after the transfer. (the next access address after the last address is shown.) (dccr n: sar=0) ? the transfer source address is returned to the initial value at the end of transfer. (dccr n: sar=1) using the dccr n: dar, set the reload control of transfer destination address at the end of transfer. ? the transfer destination address is not reloaded after the transfer. (the next access address after the last address is shown.) (dccr n: dar=0) ? the transfer destination address is returned to the initial value at the end of transfer. (dccr n: dar=1) ? transfer a ddress u pdate s etting using the dccr n: sac, set the updating of transfer source address for dma transfer. ? address is increased. (dccr n: sac = 00) ? address is decreased. (dccr n: sac = 01) ? address is fixed. (dccr n: sac = 11) using the dccr n. dac, set the updating of transfer destination address for dma transfer. ? address is increased. (dccr n: dac = 00) ? address is decreased. (dccr n: dac = 01) ? address is fixed. (dccr n:d ac = 11) mb91590 series mn705-00009-3v0-e 338
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 31 ? transfer c ount r eload s etting using the dccr n: tcr, set the reload control of transfer count at the end of transfer. ? the transfer count is not reloaded after the transfer. (after the normal completion of transfer, the transfer count is set to 0.) (dccr n: tcr=0) ? the transfer count is returned to the initial value at the end of transfer. (dccr n: tcr=1) ? transfer s ize and b lock s ize s etting to set a transfer unit for d ma transfer (the byte count to be transferred as 1 block), set the transfer size and block size. using the dccr n .ts , set the size of data to be sent by a single dma transfer (8 - bit / 16- bit / 32- bit). ? 8- bit (dccr n: ts = 00) ? 16- bit (dccr n: ts = 01) ? 32- bit (dccr n: ts = 10) using the dccr n: blk, set the dma transfer count for 1 - block data transfer. the block size can be 1 to 16 times. in the 1 - block transfer, data having the bit width being set by the transfer size (dccr n: ts), is transferred for the number of times being set by the block size. mb91590 series mn705-00009-3v0-e 339
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 32 5.3. operations this section explain s dmac operations . this se ction explains the dmac operations as follows. (1) channel status check (2) data transfer ? (1) channel s tatus c heck each dmac channel status can be checked using the dcsr n register. ? when the channel operation is enabled (the channel is active), the dcsr n:c a bit is "1". when the channel is stopped, its status is shown as "0". ? if data transfer terminates abnormally, the dcsr n: ac bit is set to "1". ? if data transfer is suspended by the transfer stop request, the dcsr n: sp bit is set to "1". ? when data transfer te rminates normally, the dcsr n: nc bit is set to "1". data writing to the dcsr n: ca bit is ignored . the dcsr n: ac, dcsr n: sp, a nd dcs r n: nc bits must be cleared before the dma transfer is allowed because these bits are not cleared automatically. ? (2) data t ransfe r the dmac starts dma transfer when the transfer source address and transfer destination address are set. by receiving a transfer source read instruction, this controller reads the data, having the bit width (8 - bit / 16- bit / 32- bit) being set by dccr n: ts, fro m the transfer source address, and temporarily stores it in the data buffer inside of the dmac. by receiving a transfer destination write instruction, the controller writes the data temporarily stored in the dmac into the transfer destination address. ? tran sfer m ode the transfer mode has block transfer mode or burst transfer mode. ? block t ransfer m ode 1- time transfer request causes the 1 block transfer. when a transfer request is detected after the block transfer, the next 1 - block transfer occurs. these operations are repeated until the end of data transfer. during 1- block data transfer, the data having the size specified by the dccr n: ts bit is transferred for the number of times being set by the block size. mb91590 series mn705-00009-3v0-e 340
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 33 figure 5-2 each transfer mode ( block transfer ) ? burst transfer mode 1- time transfer request causes the continuous data transfer until the end of transfer. (data having the size set by the dccr n: ts bit is transferre d continuously for the block size number of transfer times.) start set dmacr, dnmir, dilvr , dsar, ddar, dcsr, dtcr , dccr transfer request? transfer request wait no yes priority? priority wait no yes no transfer source access transfer destination access no blk count? transfer end dtc count? yes yes mb91590 series mn705-00009-3v0-e 341
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 34 figure 5-3 each transfer mode ( burst transfer ) ? transfer request the transfer request has a request by software or a requ est by interrupt. the following explains the relationship between the transfer request detect ion conditions and the transfer mode. ? request by software if the dccr n: ce bit is set to "1", a transfer request is detected. when the dm a operation is e nabled (dma cr : dme=1), the priority is determined and the data transfer is started immediately. when the data transfer by the transfer request has terminated, the dccr n: ce bit is cleared automatically. ? request by interrupt if the channel operation is enabled (dccr n: ce =1), a transfer request is awaited. if a peripheral interrupt, being set by the interrupt controller, has occurred, its transfer request is detected. when the dm a operation is enabled (dmacr : dme=1), the priority is determined and the data transfer is started immediately. when a transfer stop request is asserted from the peripheral, a transfer request is not detected. also, an interrupt vector to be used for transfer request must be set for each channel. see the section " chapter : generation and clearing of d ma transfer requests". * : as the interrupt request from peripherals is detected by an edge, the transfer request cannot be detected even if the ce bit is reset from "0" to "1" while the interrupt request is enabled. the interrupt of the peripheral function should be enabled after the ce bit is set to "1" . blk count ? start set dmacr, dnmir, dilvr , dsar, ddar, dcsr, dtcr , dccr transfer request? transfer request wait yes no priority? no priority wait yes transfer sourc e access transfer destination access dtc c ount ? no yes yes no transfer end mb91590 series mn705-00009-3v0-e 342
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 35 table 5-2 relationship between transfer request detect ion conditions and transfer mode block transfer burst transfer - request by software set the dccr n: ce bit to "1". set the dccr n : ce bit to "1" . - request by interrupt edge detection edg e detection - also, the relationship between the detected transfer request and the dmacr : dme and dccr n: ce bits is given on table 5-3 . if the dme bit or ce bit is cleared during transfer, the block transfer is stopped. table 5-3 relationship between transfer requests and dme/ce bits dme bit ce bit dme/ce clear the already detected transfer request is not cleared. the already detected transfer request is cleared. dme/ce setting after the transfer interru pt block transfer when a new transfer request is detected, the data transfer is restarted based on the priority. when a new transfer request is detected, the data transfer is restarted based on the priority. burst transfer when the dme bit is set, the da ta transfer is restarted immediately based on the priority. ? standby recovery request by dma transfer request if the mcu receives a transfer request in the standby mode, the dmac requests the mcu to recover from the standby mode. if data transfer is enabled and if a transfer request is asserted by the transfer request source, a standby recovery is requested. ? channel priority if multiple transfer requests are issued, the dmac starts data transfer on the channel having the highest priority. the channel prior ity can be fixed or can be set by round robin. the priority is determined for each block transfer or when data transfer ends. ? fixed priority (dmacr : at = 0 ) the channel priority is fixed in the sequenc e of "ch.0 > ch.1 > ch.2 > ch.3". the following gives an example. example 1 : if transfer requests are issued on ch . 0, ch. 1 and ch. 3 simultaneously, data transfer starts from ch . 0. when data transfer ends on ch . 0, the next data transfer starts on ch . 1. after data transfer on ch . 1, the next data transfer start s on ch . 3. the following gives transfer examples. dotted lines in the figure show the block delimiters. transfer request : requests are issued for ch0, ch. 1 and ch. 3 simultaneously. setting : ch . 0, ch. 1 and ch. 3 are set to the burst transfer mode, and data transfer occurs 3 times. mb91590 series mn705-00009-3v0-e 343
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : d ma controller (dmac) fujitsu semiconductor confidential 36 figure 5-4 data transfer example 1 if channel priority is fixed example 2: if transfer requests are issued simultaneously for ch . 1 and ch . 3 and if a tr ansfer request on ch . 0 is issued during data transfer on ch . 1, the data transfer on ch . 1 is temporarily stopped and data transfer on ch . 0 is started. during this time, the channel transition occurs in units of blocks. when the requested data transfer ends on ch . 0, the data transfer is started on ch . 1. dotted lines in the figure show the block delimiters. transfer request : requests are issued for ch . 1 and ch. 3 simultaneously. when data is transferred on ch . 1, another request for transfer on ch . 0 is issued. setting : ch . 0, ch. 1 and ch. 3 are set to the burst transfer mode, and data transfer occurs 3 times. figure 5-5 data transfer example 2 if channel priority is fixed ? round robin (d macr : at = 1 ) when data transfer is started on a channel, its priority is set to the lowest level. a channel priority below this level is raised by one level. in the round robin, data transfer starts on a channel having the highest priority when a transfer request is issued. the priority of the channel where data transfer has started is dropped to the lowest level. the priority is determined for each of block data transfer, and data transfer is started on the channel having the highest priority. the followin g gives a transfer example. dotted lines in the figure show the block delimiters. example : t ransfer request : requests are issued for ch . 0, ch. 1 and ch. 3 simultaneously. setting : ch . 0, ch. 1 and ch. 3 are set to the burst transfer mode; and data transfer occurs 3 times. transfer request is generated on ch.0, ch.1, ch.3 ch.0 transfer end ch. 1 transfer end ch. 3 transfer end ch.0 ch.1 ch.3 transfer request is generated on ch.1, ch.3 transfer request is generated on ch.0 ch.0 transfer end ch. 1 transfer end ch. 3 transfer end ch.0 ch.1 ch.3 mb91590 series mn705-00009-3v0-e 344
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 37 figure 5-6 data transfer example if channel priority is set by round robin ? updating of transfer address the transfer source address and transfer destination address are updated each time data which size has been s et by the dccr n: ts is transferred. the address updating can be increasing, decreasing, or fixed. when increasing or decreasing, its address amount is determined by the transfer size (dccr n: ts). if fixed, the address value does not change. table 5 - 4 shows t he address increasing or decreasing width during address updating. if an overflow occurs due to address updating, the relevant bit is discarded. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) transfer request is g enerated on ch.0, ch.1, ch. 3 ch.0 transfer end ch. 1 transfer end c h. 3 transfer end ch.0 ch.1 ch.3 channel priority for each block (1) ch.0 > ch.1 > ch.2 > ch.3 (2) ch.1 > ch.2 > ch.3 > ch.0 (3) ch.2 > ch.3 > ch.0 > ch.1 (4) ch.2 > ch.0 > ch.1 > ch.3 (5) ch.2 > ch.1 > ch.3 > ch.0 (6) ch.2 > ch.3 > ch.0 > ch.1 (7 ) ch.2 > ch.0 > ch.1 > ch.3 (8) ch.2 > ch.1 > ch.3 > ch.0 (9) ch.2 > ch.3 > ch.0 > ch.1 (10) ch.2 > ch.0 > ch.1 > ch.3 mb91590 series mn705-00009-3v0-e 345
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 38 table 5-4 updating of transfer source address a nd transfer destination address address setting transfer size (ts) address updating for each data transfer transfer source (sac) transfer destination (dac) transfer source (dsa) transfer destination (dda) increments ("00") increments ("00") 8 - bit ("00") increments by 1 increments by 1 16 - bit ("01") increments by 2 increments by 2 32 - bit ("10") increments by 4 increments by 4 decrements ("01") 8 - bit ("00") increments by 1 decrement s by 1 16 - bit ("01") increments by 2 decrements by 2 32 - bit ("10") increments by 4 decrements by 4 fixed ("11") 8 - bit ("00") increments by 1 not updated 16 - bit ("01") increments by 2 32 - bit ("10") increments by 4 decrements ("01") incremen ts ("00") 8 - bit ("00") decrements by 1 increments by 1 16 - bit ("01") decrements by 2 increments by 2 32 - bit ("10") decrements by 4 increments by 4 decrements ("01") 8 - bit ("00") decrements by 1 decrements by 1 16 - bit ("01") decrements by 2 decre ments by 2 32 - bit ("10") decrements by 4 decrements by 4 fixed ("11") 8 - bit ("00") decrements by 1 not updated 16 - bit ("01") decrements by 2 32 - bit ("10") decrements by 4 fixed ("11") increments ("00") 8 - bit ("00") not updated increments by 1 16 - bit ("01") increments by 2 32 - bit ("10") increments by 4 decrements ("01") 8 - bit ("00") decrements by 1 16 - bit ("01") decrements by 2 32 - bit ("10") decrements by 4 fixed ("11") 8 - bit ("00") not updated 16 - bit ("01") 32 - bit ("10") mb91590 series mn705-00009-3v0-e 346
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 39 ? reloading of transfer address the dmac can reload the transfer address after the specified number of data transfer has completed. ? reloading of transfer source address if the reloading of transfer source address has been set, the dsar n: dsa bit is returned to the initial value after the data transfer. if the reloading of transfer source address is disabled, the dsar n: dsa bit indicates the next access address of the last address after the current data transfer. if the specified number of times of tr ansfer is suspended or abnormally terminated, the dsar n: dsa bit indicates the next access address (after the terminated address) regardless of the reload setting of the transfer source address. figure 5-7 reloading of transfer source address register register settings (register write) transfer source address register transfer source address reload register reload after the transfer update register ? reloading of transfer destination address register if the reloading of the transfer destination address has been set, the ddar n: dda bit is returned to the initial value after the data transfer. if the reloading of the transfer destination address is disabled, the ddar n: dda bit indicates the next access address of the last address after the current data transfer. if the specified number of times of transfer is suspended or abnormally te rminated, the ddar n: dda bit indicates the next access address (after the terminated address) regardless of the reload setting of the transfer destination address. figure 5-8 reloading of transfer destination address register register settings (register write) transfer destination address register transfer destination address reload register reload after the transfer update register ? reloading of transfer count if the reloading of the transfer count has been set, the dtcr n: dtc bit is returned to the initial value after the data transfer. if reloading of the transfer count is disabled, the dtcr n: dtc bit is set to "0" after the data transfer. if the specified number of times of transfer is suspended or abnormally terminated, the dtcr n: dtc bit indicates the remaining transfer count regardless of the reload setti ng of the transfer count. mb91590 series mn705-00009-3v0-e 347
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 40 figure 5-9 reloading of transfer count address register the dccr n: ce bit status varies after the data transfer, depending on the reload setting of the transfer count. the following explains the relation between th e transfer count reload setting and the transfer request source. table 5-5 dccrn: ce bit at the end of transfer software request non - software request if the reloading of transfer count is set the dccr n: ce bit is cleared the dccr n: ce bit is not cleared if the reloading of transfer count is disabled the dccr n: ce bit is cleared the dccr n: ce bit is cleared ? transfer suspen sion the dmac suspends the dma transfer due to the following causes. ? a suspen sion as the dmacr :d me bit is cleared ? a suspen sion as the dccr n: ce bit is cleared ? a suspen sion caused by the transfer stop request by the transfer request source peripheral data transfer is suspended in units of blocks. if data transfer is suspended, the next transfer is not started. data transfer is stopped. the settings to restart data transfer vary depending on the suspen sion cause. ? a suspen sion as the dmacr : dme bit is cleared if the dmacr : dme bit is cleared, all channels are stopped from operating. after a block of data has been transferred on the current channel, the data transfer is suspended. to restart data transfer, set the dmacr : dme bit. ? a suspen sion as the dccr n: ce bit is cleared if the dccr n: ce bit is cleared, the channel is stopped from operating. after a block of data has been transferred, the data transfer is suspended. also, as the dccr n: ce bit is cleared, the already detected transfer request is cleared. to restart data transfer, set the dccr n: ce bit for the stopped channel and issue a new transfer request. ? a transfer stop request from the transfer request source peripheral the following peripherals can issue a transfer stop request under certain conditions. (a) multi - function serial interface if a pe, fre, or ore flag is set register settings (register write) transfer count register transfer count reload register reload after the transfer update regi ster ( - 1) mb91590 series mn705-00009-3v0-e 348
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 41 (b) l in - uart if a pe, fre, or ore flag is set if a transfer stop request is issued, the transfer is suspended after one block of the current data has been transferred. if the data transfer is suspended, the following occur. ? the sp bit of dma channel status registers (dcsr n ) is set to "1". ? the ce bit of dma channel control registers (dccr n ) is set to "0". ? the already detected transfer request is cleared. while a transfer stop request being issued, a new transfer request is rejected. restart the dma transfer in the following procedure. 1. clea r the flags described in paragraphs (a) and (b) to make the transfer stop request invalid. 2. set the sp bit of dma channel status registers (dcsr n ) of the corresponding channel to "0". 3. set the ce bit of dma channel control registers (dccr n ) to "1". 4. issue a n ew transfer request. table 5-6 settings to restart the suspended data transfer dme clear ce clear if a transfer stop request from transfer request source peripheral is detected setting to restart transfer (1) set the dme bit (1) set the ce bit (2) issue a tra nsfer request (1) the transfer request is negated (2) the sp bit is cleared (3) the ce bit is set (4) issue a transfer request ? transfer termination data transfer can terminate normally or abnormally. ? normal termination the transfer terminates normally at the time when the transfers for the number of times set by the transfer count (dtcr n :dtc) end. when terminated normally, the dcsr n :nc bit of the corresponding channel is set. also, the dccr n :ce bit is cleared and data transfer is stopped. however, if the r eloading of the transfer count has been set by non - software transfer request source, the dccr n :ce bit of th e channel is not cleared. i f the transfer count (dtcr n :dtc ) is "0" and if the dccr n :ce bit of the corresponding channel is set to "1", the dcsr n :nc bit is set in the similar way as for the normal termination. before setting the dccr n :ce bit to "1", be sure to set the dtcr n :dtc bit to "1" or a larger value. ? abnormal termination if an inhibited value is set in the register, data transfer terminates abnormally. when terminated abnormally, the dcsr n :ac bit of the corresponding channel is set. also, the dccr n :ce bit is cleared and data transfer is stopped. the items not allowed to set to registers are listed below. ? transfer mode : d ccr n: tm = 10 ? transfer source address count : dccr n: sac = 10 ? transfer destination address count : dccr n: dac = 10 ? transfer size : dccr n: ts = 11 ? demand transfer mode by software request : dccr n: rs = 00 and dccr n: tm = 11 mb91590 series mn705-00009-3v0-e 349
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 42 ? interrupt request the dmac can issue an int errupt request at normal termination of data transfer, at abnormal termination of data transfer, or at transfer suspen sion by a transfer stop request. when issuing an interrupt request, set the interrupt controller as well. use the dma channel status regis ter (dcsr n ) to check the interrupt request cause or to clear the interrupt request. ? interrupt request at normal termination if the normal termination interrupt of a channel is enabled (dccr n :nie=1), the dmac issues the interrupt request at the normal termi nation . however, the dcsr n :nc bit of the corresponding channel must be set regardless of the normal termination interrupt setting (dccr n :nie). clear the interrupt request by clearing the dcsr n :nc bit of the corresponding channel. ? interrupt request at abno rmal termination if the abnormal termination interrupt of a channel is enabled (dccr n :aie=1), the dmac issues the interrupt request at the abnormal termination . however, the dcsr n :ac bit of the corresponding channel is set regardless of the abnormal termin ation interrupt (dccr n :aie) setting. clear the interrupt request by clearing the dcsr n :ac bit of the corresponding channel. ? a transfer suspen sion interrupt request by a transfer stop request if the transfer suspen sion interrupt of a channel is enabled (dc crn :aie=1), the dmac issues the interrupt request if data transfer is suspended by a transfer stop request. however, the dcsr n :sp bit of the corresponding channel is set regardless of the transfer suspen sion interrupt (dccr n :sie) settings. clear the interrupt request by clearing the dcsr n :sp bit of the corresponding channel. ? dma transfer suppressing the dma transfer is suppressed due to the following causes. ? a dma transfer suppress request from dsu/ocd (for debugging) ? nmi ? peripheral interrupt the dma trans fer is suppressed in units of blocks. if data transfer is suppressed, new data transfer does not start. data transfer is stopped. the settings to restart data transfer vary depending on the dma transfer suppress cause s. ? dma transfer suppress ing request from dsu/ocd (for debugging) when the dma transfer suppressing request by dsu/ocd is asserted, a new transfer does not start and a current trasfer stops with the block unit. the acknowledge is not returned to the dma transfer suppressing from dsu/ ocd. ? dma transfer suppress ing by nmi if the nmih bit is set to "0", dmac sets nmih flag when user nmi occurs and suppresses dma transfer after the block unit transfer is done. w rite "0" in the nmih flag when you restart transfer . ? dma transfer suppressing by peripheral interrupt if an interrupt having the level higher than the one specified in the dilvr register occurs, the dma transfer is suppressed after the current block has been transferred. when the interrupt request is cleared and the interrupt le vel drops to lvl[4:0] or lower level, the dma transfer restarts. mb91590 series mn705-00009-3v0-e 350
chapter 8: dma controller (dmac) 5 . operation fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 43 table 5-7 lvl[4:0] settings to suppress dma transfer lvl[4:0] dma suppress control 11111 suppresses the dma transfer when any peripheral interrupt request is issued. (initial value) 11110 suppresses the dma transfer when a peripheral inter rupt request having a level higher than 1 e h is issued. 11101 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 d h is issued. 11100 suppresses the dma transfer when a peripheral interrupt request having a level hi gher than 1 c h is issued. 11011 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 b h is issued. 11010 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 a h is issued. 1100 1 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 9 h is issued. 11000 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 8 h is issued. 10111 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 7 h is issued. 10110 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 6 h is issued. 10101 suppresses the dma transfer when a peripheral interrupt re quest having a level higher than 1 5 h is issued. 10100 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 4 h is issued. 10011 suppresses the dma transfer when a peripheral interrupt request having a level higher th an 1 3 h is issued. 10010 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 2 h is issued. 10001 suppresses the dma transfer when a peripheral interrupt request having a level higher than 1 1 h is issued. 10000 does not suppress the dma transfer when a peripheral interrupt request is issued. mb91590 series mn705-00009-3v0-e 351
chapter 8: dma controller (dmac) 6 . dma usage examples fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 44 6. dma usage examples dma u sage e xamples are shown. the following gives an example of memcpy instruction in every 64 - byte data using the dma. this is the simplest dma transfer exa mple. figure 6-1 m emcpy example using the dma (ch.3 i s used) configure dma ? configure dma transfer settings from software. (dccr3) burst transfer; transfer size: word; block size: 16 times ? configure the dma transfer source address. (dsar3) ? configure the dma transfer destination address. (dsar3) ? configure the number of transfers. (dtcr3) number of transfers: amount of data to transfer (in bytes)/64 ? permit and issue dma request from software. ( dmacr, d cc r 3) wait for dma to finish ? the progress can be checked by reading the dsar3, ddar3, dtcr3 registers. ? transfer complete can be checked by reading the dcsr3 register. issue interrupt request (ddar3) mb91590 series mn705-00009-3v0-e 352
chapter 8: dma controller (dmac) 6 . dma usage examples fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 45 this is a communication example via the multi - function serial interface that uses the dma. in this example, an interrupt of the multi - function serial interfa ce is occupied by the dma transfer request.therefore, the cpu polls the status registers to check for an error occurrence. figure 6-2 communication example via the multi - function serial interface that uses dma multi-function serial interf ace fifo uart exte r nal d evice cpu dm ac settings (dma t r ans f er conditions) settings (protocol, etc.) settings (fifo inter r upt conditions) settings (dma disa b le) settings (com m unication disa b le) s et tings (clear each item) settings (reset) che ck f or e xistence of error che ck f or e xistence of error dma request b y inter r upt data t r ans f er data data dma request b y inter r upt data t r ans f er mb91590 series mn705-00009-3v0-e 353
chapter 8: dma controller (dmac) 6 . dma usage examples fujitsu semiconductor limited chapter : dma controller (dmac) fujitsu semiconductor confidential 46 mb91590 series mn705-00009-3v0-e 354
chapter 9: generation and clearing of dma transfer requests 1 . overview fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 1 chapter : generation and clearing of dma transfer requests this chapter explains the generation and clearing of dma transfer requests. 1. overview 2. features 3. configuration 4. registers 5. operation code : 09_mb91590_hm_e_dmareq_00 6 _2011112 7 mb91590 series mn705-00009-3v0-e 355
chapter 9: generation and clearing of dma transfer requests 1 . overview fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 2 1. overview this section explains the overview of the generation and clearing of dma transfer requests. this series can activate dma transfer using interrupt requests from peripheral functions. registers used to select interrupt requests that activate dma transfer are provided for each dma controller (dmac) channel. if multiple interrupt requests are assigned to one interrupt vector number, it is also necessary to specify what interrupt request flag is to be cleared by the dma controller (dmac). dma controller (dmac) registers allow dma transfer reques t generation factors (transfer request sources) to be set on interrupt requests from peripheral functions. the interrupt requests to be used can be selected by specifying the value corresponding to the interrupt vector number. mb91590 series mn705-00009-3v0-e 356
chapter 9: generation and clearing of dma transfer requests 2 . features fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 3 2. features this section explain s features of the generation and clearing of dma transfer requests. ? transfer request generation setting for each 16- channel dma transfer request, you need to specify what interrupt from interrupt vector numbers 0x10 (16 in decimal notation) to 0x3f (63 in decimal notation) is used to generate the dma transfer request. ? interrupt clearing setting after the dma transfer ends, the interrupt source peripheral that has issued the interrupt request to be cleared is identified if the transfer request source is a ve ctor number to which multiple interrupt source peripherals belong. mb91590 series mn705-00009-3v0-e 357
chapter 9: generation and clearing of dma transfer requests 3 . configuration fujitsu semiconductor limited chapter : generation and clearing of dma t ransfer requests fujitsu semiconductor confiden tial 4 3. configuration this section explains the configuration of the generation and clearing of dma transfer requests. figure 3-1 block diagram ch.15 ch. 1 interrupt requests vector number 16 to 63 ios ioe dma c ch. 0 to ch.15 transfer requests ch. 0 dm a c transfer completion ch. 0 to ch.15 reverse the interrupt vector number of which dma transfer completed. reverse peripheral icsel iorr inter r upt clea r ing requests to each pe r iphe r als mb91590 series mn705-00009-3v0-e 358
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 5 4. registers this section explains registers of the generation and clearing of dma transfer requests. table 4-1 register s map address register s register function +0 +1 +2 +3 0x0400 icsel0 icse l1 icsel2 icsel3 dma clear request register 0 (for vector number #16) dma clear request register 1 (for vector number #17) dma clear request register 2 (for vector number #18) dma clear request register 3 (for vector number #19) 0x0404 icsel4 icsel5 icsel 6 icsel7 dma clear request register 4 ( for vector number # 38 ) dma clear request register 5 ( for vector number # 39) dma clear request register 6 ( for vector number #4 0) dma clear request register 7 ( for vector number #4 1 ) 0x0408 icsel8 icsel9 icsel10 icsel 11 dma clear request register 8 ( for vector number #4 2 ) dma clear request register 9 ( for vector number #4 3) dma clear request register 10 ( for vector number # 44 ) dma clear request register 11 ( for vector number # 46 ) 0x040c icsel12 icsel13 icsel14 icsel15 dma clear request register 12 ( for vector number # 47 ) dma clear request register 13 ( for vector number # 52) dma clear request register 14 ( for vector number # 53) dma clear request register 1 5 ( reserved ) 0x0410 icsel16 icsel17 icsel18 icsel1 9 dma clear re quest register 1 6 ( reserved ) dma clear request register 17 ( reserved ) dma clear request register 18 ( reserved ) dma clear request register 19 ( for vector number # 58 ) 0x0414 icsel 20 icsel 21 icsel 22 reserved dma clear request register 20 ( for vector number # 59 ) dma clear request register 21 ( for vector number # 60 ) dma clear request register 22 ( for vector number # 61) 0x0490 iorr0 iorr1 iorr2 iorr3 io transfer request register 0 io transfer request register 1 io transfer request register 2 io transfer request register 3 0x0494 iorr4 iorr5 iorr6 iorr7 io transfer request register 4 io transfer request register 5 io transfer request register 6 io transfer request register 7 mb91590 series mn705-00009-3v0-e 359
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation a nd clearing of dma transfer requests fujitsu semiconductor confiden tial 6 address register s register function +0 +1 +2 +3 0x049 8 iorr 8 iorr 9 iorr 10 iorr 11 io transfer request register 8 io transfer request reg ister 9 io transfer request register 10 io transfer request register 11 0x049 c iorr 12 iorr 13 iorr 14 iorr 15 io transfer request register 12 io transfer request register 13 io transfer request register 14 io transfer request register 15 mb91590 series mn705-00009-3v0-e 360
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 7 4.1. dma request clear register 0 : icsel0 (interrupt clear select register 0) t he b it configuration of dma request clear register 0 is shown below . ? icsel0 : address 0400 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved eisel[2:0] initial v alue 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w r/w [b it2 to bit 0] eisel[2:0] (external interrupt request selection) : interrupt clear selection bits for external interrupts 0 to 7 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #1 6). eisel[2:0] clear target 000 external interrupt 0 001 external interrupt 1 010 external interrupt 2 011 external interrupt 3 100 external interrupt 4 101 external inte rrupt 5 110 external interrupt 6 111 external interrupt 7 mb91590 series mn705-00009-3v0-e 361
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited ch apter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 8 4.2. dma request clear register 1 : icsel1 (interrupt clear select register 1) t he b it configuration of dma request clear register 1 is shown below . ? icsel1 : address 0401 h ( access : byte , half - word, w ord) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved eisel[2:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w r/w [b it2 to bit 0] eisel[2:0] (external interrupt request selection) : interrupt clear selection bit s fo r external interrupts 8 to 15 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #17). eisel[2:0] clear target 000 external interrupt 8 001 external interrupt 9 010 external i nterrupt 10 011 external interrupt 11 100 external interrupt 12 101 external interrupt 13 110 external interrupt 14 111 external interrupt 15 mb91590 series mn705-00009-3v0-e 362
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 9 4.3. dma request clear register 2 : icsel2 (interrupt clear select register 2) t he b it configuration of dma requ est clear register 2 is shown below . ? icsel2 : address 0402 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved rtsel 0 initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w [b it0 ] rtsel 0 (reload timer selection) : interrupt clear selection bit for reload timer 0/1 t his bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #18). rtsel 0 clear target 0 reload timer 0 1 relo ad timer 1 mb91590 series mn705-00009-3v0-e 363
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 10 4.4. dma request clear register 3 : icsel3 (interrupt clear select register 3) t he b it configuration of dma request clear register 3 is shown below . ? icsel3 : address 0403 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r eserved rtsel 1 initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w [b it0 ] rtsel 1 (reload timer selection) : interrupt clear selection bit for reload timer 2/3 th is bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #19). rtsel 1 clear target 0 reload timer 2 1 reload timer 3 mb91590 series mn705-00009-3v0-e 364
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 11 4.5. dma request clear register 4 : icsel4 (interrupt clear select register 4) t he b it configuration of dma request clear registe r 4 is shown below . ? icsel4 : address 0404 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sg_rx_sel0 initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w [b it0 ] sg_rx_sel 0 ( sg_rx se lection 0 ) : interrupt clear selection bit for sound generator ch. 0 / lin - uart ch. 7 reception completion th is bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 38). sg_rx_ sel 0 clear tar get 0 sound generator ch. 0 1 lin - uart ch.7 reception completion mb91590 series mn705-00009-3v0-e 365
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 12 4.6. dma request clear register 5 : icsel5 (interrupt clear select register 5 ) t he b it configuration of dma request clear register 5 is shown below . ? icsel 5 : address 040 5 h ( access : byte, half -w ord, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sg_rx_sel1 initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w [b it0 ] sg_rx_sel 1 ( sg_rx selection 1) : interrupt clear selection bit for sound generator ch . 1 / lin - uart ch. 7 transmission completion th is bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 39). sg_rx_ sel 1 clear target 0 sound generator ch. 1 1 lin - uart ch. 7 transmission com pletion mb91590 series mn705-00009-3v0-e 366
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 13 4.7. dma request clear register 6 : icsel6 (interrupt clear select register 6 ) t he b it configuration of dma request clear register 6 is shown below . ? icsel 6 : address 040 6 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res erved ppgsel 0[2:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w r/w [b it 2 to bit 0] ppgsel 0[2:0] (ppg selection 0) : interrupt clear selection bit s for ppg0, 1, 10, 11, 20, 21 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #4 0 ). ppgsel 0[2:0] clear target 0 00 ppg0 00 1 ppg1 010 ppg1 0 011 ppg1 1 100 ppg 20 101 ppg 2 1 110 reserved (does not clear any) 111 reserved (does not clear any) note: setting ppgsel0[2:0]= "3'b110","3'b111" is prohibited. during this setting, no interrupt clear will be selected. mb91590 series mn705-00009-3v0-e 367
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 14 4.8. dma request clear register 7 : icsel7 (interrupt clear select register 7 ) t he b it configuration of dma request clear register 7 is shown below . ? icsel 7 : address 040 7 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppgsel 1[2:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w r/w [b it 2 to bit 0] ppgsel 1[2:0] (ppg selection 1 ) : interrupt clear selection bit s for ppg2, 3, 12, 13, 22, 23 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #4 1 ). ppgsel 1[2:0] clear target 0 00 ppg2 00 1 ppg3 010 ppg1 2 011 ppg1 3 100 ppg 22 101 ppg 23 110 reserved (does not clear any) 111 reserved (does not clear any) note: setting ppgsel1[2:0]= "3'b110","3'b111" is prohibited. during this setting, no interrupt clear will be selected. mb91590 series mn705-00009-3v0-e 368
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 15 4.9. dma request clear register 8 : icsel8 (interrupt clear select register 8 ) t he b it configuration of dma request clear register 8 is shown below . ? icsel 8 : address 040 8 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppgsel 2[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it 1 , bit 0] ppgsel 2[1:0] (ppg selection 2 ) : interrupt clear selection bit s for ppg4, 5, 14, 15 these bits are used to select the peripheral that has generated the interrupt to be cleared (assig ned to interrupt vector number #4 2 ). ppgsel 2[1:0] clear target 0 0 ppg4 0 1 ppg5 10 ppg14 11 ppg15 mb91590 series mn705-00009-3v0-e 369
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 16 4.10. dma request clear register 9 : icsel9 (interrupt clear select register 9 ) t he b it configuration of dma request clear register 9 is shown below . ? icsel 9 : a ddress 040 9 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppgsel 3[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it 1 , bit 0] ppgsel 3[1:0] (ppg selection 3) : interrupt clear selection bit s for ppg6, 7, 16, 17 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #4 3 ). ppgsel 3[1:0] clear target 0 0 ppg6 0 1 ppg7 10 ppg16 11 ppg17 mb91590 series mn705-00009-3v0-e 370
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 17 4.11. dma request clear register 10 : icsel10 (interrupt clear select register 10 ) t he b it configuration of dma request clear register 10 is shown below . ? icsel 10 : address 040 a h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppgsel 4[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it 1 , bit 0] ppgsel 4[1:0] (ppg selection 4 ) : interrupt clear selection bit s for ppg8, 9, 18, 19 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 44). ppgsel 4[1:0] clear target 0 0 ppg8 0 1 ppg9 10 ppg18 11 ppg19 mb91590 series mn705-00009-3v0-e 371
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 18 4.12. dma request clear register 11 : icsel 11 (interrupt clear select register 11 ) t he b it configuration of dma request clear register 11 is shown below . ? icsel 11 : address 040 b h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved pmstsel[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it1 , bit 0] pmstsel [1:0] (pll, main, sub timer selection) : interrupt clear selection for main timer / sub timer / pll timer these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 46). pmstsel[1:0] clear ta rget 00 main timer 01 sub timer 10 pll timer 11 setting is prohibited mb91590 series mn705-00009-3v0-e 372
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited c hapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 19 4.13. dma request clear register 12 : icsel12 (interrupt clear select register 12 ) t he b it configuration of dma request clear register 12 is shown below . ? icsel1 2 : address 040 c h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sg_rx_ sel[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it 1 , bit 0] sg_rx_sel[1:0] (sg_rx selection) : interrupt clear sel ection fo r sg4 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 47). sg_rx_ sel [1:0] clear target 0 0 reserved (does not clear any) 0 1 sound generator ch. 4 10 setting is prohibited 1 1 reserved (does not clear any) note: clock calibration (sub) is not covered as it is an interrupt which does not support the iioc. setting sg_rx_sel[1:0]= "2'b11" is prohibited . during this setting, no interrupt clear will be selected. mb91590 series mn705-00009-3v0-e 373
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 20 4.14. dma request clear register 13 : icsel13 (interrupt clear select register 13 ) t he b it configuration of dma request clear register 13 is shown below . ? icsel1 3 : address 040 d h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved icusel0 initia l value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r / w [ bit0 ] icusel0 : interrupt clear selection for icu ch.0, ch. 6 th is b it is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #5 2 ). icusel0 clear target 0 icu ch. 0 1 icu ch. 6 mb91590 series mn705-00009-3v0-e 374
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 21 4.15. dma request clear register 14 : icsel14 (interrupt clear select register 14 ) t he b it configuration of dma request clear register 14 is shown below . ? icsel1 4 : address 040 e h ( access : byte, h alf - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved icusel1 initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r / w [ bit0 ] icusel1 : interrupt clear selection for icu ch.1 , ch. 7 th is bit is used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #5 3 ). icusel1 clear target 0 icu ch. 1 1 icu ch. 7 mb91590 series mn705-00009-3v0-e 375
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 22 4.16. dma request clear register 1 5 to 18 : icsel15 to 18 (interrupt clear select register 15 to 18 ) t he b it c onfiguration of dma request clear register 15 to 18 is shown below . ? icsel1 5 : address 040 f h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,w x r0,wx r0,wx r 0, w 0 ? icsel1 6 : address 0410 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r 0, w 0 ? icsel1 7 : address 0411 h ( ac cess : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r 0, w 0 ? icsel1 8 : address 0412 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 b it 4 bit 3 bit 2 bit 1 bit 0 reserved reserved initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r 0, w 0 [b it0 ] reserved this is a reserved bit. always write "0" to this bit. mb91590 series mn705-00009-3v0-e 376
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 23 4.17. dma request clear register 19 : icsel19 (interrupt clear select register 19 ) t he b it configuration of dma request clear register 19 is shown below . ? icsel1 9 : address 0413 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ocusel0 [2:0] initial value 0 0 0 0 0 0 0 0 at tribute r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w r/w [b it 2 to bit 0] ocusel0 [2:0] (ocu selection 0 ) : interrupt clear selection bit s for ocu0, 1 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number #5 8 ). ocusel0 [2:0] clear target 0 00 ocu0 00 1 ocu1 010 setting is prohibited 011 setting is prohibited 100 setting is prohibited 101 setting is prohibited 110 reserved (does not clear any) 111 reserved (does not clear any) note: sett ing ocusel0[2:0]= "3'b110","3'b111" is prohibited . during this setting, no interrupt clear will be selected. mb91590 series mn705-00009-3v0-e 377
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 24 4.18. dma request clear register 20 : icsel20 (interrupt clear select register 20 ) t he b it configuration of dma request clear register 20 is shown belo w. ? icsel 20 : address 0414 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ocusel1 [2:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w r/w [b it 2 to bit 0] ocusel1 [2:0] (ocu selection 1 ) : interrupt clear selection bit s for ocu2, 3 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 59). ocusel1 [2:0] clear target 000 ocu2 001 ocu3 010 setting is prohibited 01 1 setting is prohibited 100 setting is prohibited 101 setting is prohibited 110 reserved (does not clear any) 111 reserved (does not clear any) note : setting ocusel1[2:0]= "3'b110","3'b111" is prohibited . during this setting, no interrupt clear will b e selected. mb91590 series mn705-00009-3v0-e 378
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 25 4.19. dma request clear register 21 : icsel21 (interrupt clear select register 21 ) t he b it configuration of dma request clear register 21 is shown below . ? icsel 21 : address 0415 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bi t 0 reserved bt_sg_sel 0[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it1 , bit 0] bt_sg_sel 0[1:0] ( bt_sg selection 0 ) : interrupt clear selection bit s for base timer0 irq0, irq1/ sg2 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 60). bt _sg_ sel 0[1:0] clear target 0 0 base timer 0 irq0 0 1 base timer 0 irq1 10 sound generator ch. 2 11 reserved (does not clear any) note : setting bt_sg_sel0[1:0]="2'b11" is prohibited . during this setting, no interrupt clear will be selected. mb91590 series mn705-00009-3v0-e 379
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma tran sfer requests fujitsu semiconductor confiden tial 26 4.20. dma request clear register 22 : icsel22 (interrupt clear select register 2 2) t he b it configuration of dma request clear register 22 is shown below . ? icsel 22 : address 0416 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bt_sg_sel 1[1:0] initial value 0 0 0 0 0 0 0 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx r/w r/w [b it1 , bit 0] bt_sg_sel [1:0] ( bt_sg_ selection1) : in terrupt clear selection bit s for base timer1 irq0, irq1/ sg3 these bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to interrupt vector number # 61). bt _sg_ sel1 [1:0] clear target 0 0 base timer 1 irq0 0 1 base t imer 1 irq1 10 sound generator ch. 3 11 reserved (does not clear any) note: interrupts for xbs ram single - bit error occurrence and backup ram single - bit error occurrence shall not be covered as they do not support the iioc. setting bt_sg_sel1[1:0]= "2'b11" is prohibited . during this setting, no interrupt clear will be selected. mb91590 series mn705-00009-3v0-e 380
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 27 4.21. io transfer request setting register 0 to 15 : iorr0 to 15 (io triggered dma request register for ch. 0 to 15) t he b it configuration of io transfer re quest setting register 0 to 1 5 is shown below . if the dma transfer request generation factor is specified as a peripheral interrupt request, these registers are used to identify the vector number of the interrupt request that has generated the dma transfer request. an instance of these registers is provided for each dma controller (dmac) channel. ? iorr0 to 15 : address 0490 h to 049 f h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ioe ios[5:0] initial value 0 0 0 0 0 0 0 0 attribute r0,w 0 r/w r/w r/w r/w r/w r/w r/w [b it 7] reserved always write "0" to this bit. the read value is always "0". [b it6 ] ioe (io enabled) : transfer request enable bit when an interrupt request specified by the ios5 to ios0 bits has been generated, this bit is used to notify the dma controller (dmac) for the pertinent channel whether to output the dma transfer request. ioe function 0 no dma transfer request output -- the interrupt request generated by the peripheral is not used as a dma transfer request (initial value). 1 d ma transfer request output [b it5 to bit 0] ios [5:0] (io triggered dma transfer request select) : transfer request selection bit s these registers are used to identify the interrupt request of the vector number that is used as the transfer request source by the dma controller (dmac) for the channel corresponding to these registers. ios[5:0] interrupt vector number (hexadecimal) 000000 0x10 ( initial value ) 000001 0x11 000010 0x12 000011 0x13 000100 0x14 000101 0x15 : : 101100 0x3c 101101 0x3d 101110 0x3e 101111 0x3f mb91590 series mn705-00009-3v0-e 381
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 28 ios[5:0] interrupt vector number (hexadecimal) 11xxxx reserved mb91590 series mn705-00009-3v0-e 382
chapter 9: generation and clearing of dma transfer requests 4 . registers fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 29 note: you cannot configure setting that causes interrupt requests with the same interrupt vector number to be transfer requests from multiple dma channels (example:simultaneous setting of iorr0 = 0x42 and iorr1 = 0x42). mb91590 series mn705-00009-3v0-e 383
chapter 9: generation and clearing of dma transfer requests 5 . operat ion fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 30 5. operation this section explains the operation of the generation and clearing of dma transfer requests. 5.1 . configuration 5.2 . notes mb91590 series mn705-00009-3v0-e 384
chapter 9: generation and clearing of dma transfer requests 5 . operation fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 31 5.1. configuration this section explains the configuration of the generation and clearing of dma transfer requests. the operating sequence is as follows: 1. on the iorr, set the interrupt vector number of the transfer request source peripheral and the ioe bit. 2. set icsel if m ultiple peripherals is assigned to the vector number selected in step 1. 3. set the interrupt configuration - related registers for the peripheral. 4. configure the dmac. mb91590 series mn705-00009-3v0-e 385
chapter 9: generation and clearing of dma transfer requests 5 . operation fujitsu semiconductor limited chapter : generation and clearing of dma transfer requests fujitsu semiconductor confiden tial 32 5.2. notes this section explains notes of the generation and clearing of dma transfer requests. ? do not change the iorr and icsel registers when the dmac enables dma transfer requests issued by peripherals. ? peripherals to which resource numbers (rn) are not assigned ( see " appendix " ) cannot use the feature for clearing interrupts after the completion of dma transfer. it should therefore be noted that once such a peripheral has requested dma transfer, the interrupt will not be cleared after the completion of the requested dma transfer. ? interrupt requests used as transfer requests are considered as interrupt requests addressed to the cpu. therefore, configure the interrupt controller to disable interrupts. (icr register) mb91590 series mn705-00009-3v0-e 386
chapter 10: fixedvector function 1 . overview fujitsu semiconductor limited chapter: fixedvector function fujitsu semiconductor confidential 1 chapter : fixedvector function this chapter explains the f ixed v ector function. 1. overview 2. operation explanation code : 10_mb91590_hm_e_fixedvector_00 3 _201111 27 mb91590 series mn705-00009-3v0-e 387
chapter 10: fixedvector function 1 . overview fujitsu semiconductor limited chapter: fixedvector function fujitsu semiconductor confidential 2 1. o verview this section explains the overview of the f ixed v ector function . the fixedvector function is a function for returning the start addres s of flash memory + 0x0024 instead of the content of flash memory at the address (0xf_fffc) corresponding to the interrupt vector on reset. ? features ? interrupt vector on reset returned by the fixedvector function ? 0x0007 _0024 ? configuration see "figure 3 -2" in " chapter : flash memory " for the configuration diagram. ? registers none. mb91590 series mn705-00009-3v0-e 388
chapter 10: fixedvector function 2 . opera tion explanation fujitsu semiconductor limited chapter: fixedvector function fujitsu semiconductor confidential 3 2. opera tion explanation this section explain s the operation of the f ixed v ector function. ? operation after reset released in the following flow , the start address of flash memory + 0x0024 is returned instead of the content of 0xf_fffc in flash memory when the res et is released. figure 2-1 operation flow after r eset ? usage after the reset is released, this series executes from the start address of flash memory + 0x0024 instead of the value written at address 0x000f_fffc . ? note s during rea ds from addresses 0x000f_fffc to 0x000f_ffff other than reset vector fetch (example: the call destination when int #00h is executed while tbr is its initial value (= 0x000f_fc00 )), the content of flash memory at the addresses 0x000f_fffc to 0x000f_ffff is r eturned. reset released the cpu fetches the reset vector (address 0xf_fffc). the flash memory interface returns the start address of flash memory + 0x0024 instead of the content of flash memory at address 0xf_fffc. execute f rom the start address of flash memory + 0x0024. mb91590 series mn705-00009-3v0-e 389
chapter 10: fixedvector function 2 . operation explanation fujitsu semiconductor limited chapter: fixedvector function fujitsu semiconductor confidential 4 mb91590 series mn705-00009-3v0-e 390
chapter 1 1: i/o ports 1 . overview fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 1 chapter : i/o ports this chapter explains the i/o ports. 1. overview 2. features 3. configuration 4. registers 5. operation code : 11_mb91590_hm_e_ioport_00 8 _2011112 7 mb91590 series mn705-00009-3v0-e 391
chapter 1 1: i/o ports 1 . overview fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 2 1. overview this section explains the overview of the i/o ports. this section explains the setti ng for assigning to the external pins (peripherals and external bus) and using external pins as the i/o port. mb91590 series mn705-00009-3v0-e 392
chapter 1 1: i/o ports 2 . features fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 3 2. features this section explains features of the i/o ports. ? i/o multiplexing if the i/o of multiple peripherals is assigned to one external pin, one of these peripheral s is selected to be used. ? i/o relocation if one pin for one peripheral can serve multiple external pins for i/o, one of these external pins is selected to be used. ? port function external pins can be used for general - purpose i/o: if they are used for output, their values can be set and if they are used for input, input values assigned to them can be read. figure 2-1 diagram of i/o multiplexing , i/o relocation a peripheral i/o multiplexing peripheral a peripheral b peripheral c i/o relocation mb91590 series mn705-00009-3v0-e 393
chapter 1 1: i/o ports 3 . configuration fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the i/o ports. no configuration diagram is provided. mb91590 series mn705-00009-3v0-e 394
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 5 4. registers this section explains registers of the i/o ports. address registers register function +0 +1 +2 +3 0x0000 pdr00 pdr01 pdr02 pdr03 port data register 0 0 to 13 port data register a to h 0x0004 pdr04 pdr05 pdr06 pdr07 0x0008 pdr08 pdr09 pdr10 pdr11 0x000c pdr12 pdr13 reserved reserved 0x 0010 pdr a pdr b pdr c pdr d 0x0014 pdr e pdrf pdrg pdrh 0x0e00 ddr00 ddr01 ddr02 ddr03 data direction register 00 to 13 data direction register a to h 0x0e04 ddr04 ddr05 ddr06 ddr07 0x0e08 ddr08 ddr09 ddr10 ddr11 0x0e0c ddr12 ddr13 reserved reserved 0x0e10 ddr a ddr b ddr c ddr d 0x0e14 ddr e ddr f ddr g ddr h 0x0e20 pfr00 pfr01 pfr02 pfr03 port function register 00 to 13 port function register a to h 0x0e24 pfr04 pfr05 pfr06 pfr07 0x0e28 pfr08 pfr09 pfr10 pfr11 0x0e2c pfr12 pfr13 reserved reserved 0x0e30 pfr a pfr b pfr c pfr d 0x0e34 pfr e pfr f pfr g pfr h 0x0e40 pddr00 pddr01 pddr02 pddr03 input data direct read register 00 to 13 input data direct read register a to h 0x0e44 pddr04 pddr05 pddr06 pddr07 0x0e48 pddr08 pddr09 pddr10 pddr11 0x0e4c pddr12 pddr13 reserved reserved 0x0e50 pddr a pddr b pddr c pddr d 0x0e54 pddr e pddr f pddr g pddr h 0x0e60 epfr00 epfr01 epfr02 epfr03 e xtended port function register 00 to 55 0x0e64 epfr04 epfr05 epfr06 epfr07 0x0e68 epfr08 epfr09 epfr10 epfr11 mb91590 series mn705-00009-3v0-e 395
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 6 address registers register function +0 +1 +2 +3 0x0e6c epfr12 epfr13 epfr14 epfr15 e xtended port function register 00 to 55 0x0e70 epfr16 epfr17 epfr18 epfr19 0x0e74 epfr20 epfr21 epfr22 epfr23 0x0e78 epfr24 epfr25 epfr26 epfr27 0x0e7c epfr28 epfr29 epfr30 epfr31 0x0e80 epfr32 epfr33 epfr34 epfr35 0x0e8 4 epfr3 6 epfr37 epfr38 epfr39 0x0e8 8 epfr 40 epfr41 epfr42 epfr43 0x0e8 c epfr 44 epfr45 epfr46 epfr47 0x0e 90 epfr 48 epfr49 epfr50 epfr51 0x0e 94 epfr 52 epfr53 epfr54 epfr55 0x0ea0 ppcr00 ppcr01 ppcr02 ppcr03 p ort pull - up/down control r egister 00 to 13 p ort pull - up/down control register a to h 0x0ea4 ppcr04 ppcr05 ppcr06 ppcr07 0x0ea8 ppcr08 ppcr09 ppcr10 ppcr11 0x0eac ppcr12 ppcr13 reserved reserved 0x0eb0 ppcr a ppcr b ppcr c ppcr d 0x0eb4 ppcr e ppcr f ppcr g ppcr h 0x0ec0 pper00 p per01 pper02 pper03 p ort pull - up/down enable register 0 0 to 13 p ort pull - up/down enable register a to h 0x0ec4 pper04 pper05 pper06 pper07 0x0ec8 pper08 pper09 pper10 pper11 0x0ecc pper12 pper13 reserved reserved 0x0ed0 pper a pper b pper c pper d 0x0 ed4 pper e pper f pper g pper h 0x0ee0 pilr00 pilr01 pilr02 pilr03 p ort input level selection register 00 to 13 p ort input level selection register a to h 0x0ee4 pilr04 pilr05 pilr06 pilr07 0x0ee8 pilr08 pilr09 pilr10 pilr11 0x0eec pilr12 pilr13 reserve d reserved 0x0ef0 pilr a pilr b pilr c pilr d 0x0ef4 pilr e pilr f pilr g pilr h mb91590 series mn705-00009-3v0-e 396
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 7 address registers register function +0 +1 +2 +3 0x0f00 reserved reserved reserved reserved e xtended port input level selection register 06 to 13 0x0f04 reserved reserved epilr06 epilr07 0x0f08 epilr08 epilr09 epilr1 0 epilr11 0x0f0c epilr12 epilr13 reserved reserved 0x0f20 reserved reserved reserved reserved p ort output drive register 06 to 13 0x0f24 reserved reserved podr06 podr07 0x0f28 podr08 podr09 podr10 podr11 0x0f2c podr12 podr13 reserved reserved 0 x0f 38 epodr06 epodr0 7 epodr0 8 reserved e xtended port output drive register 06 to 08 0x0f 3c epodr gd epodrg f reserved reserved e xtended port output drive register (gdc interface, graphics flash interface) 0x0f40 porten reserved reserved reserved port input enable register mb91590 series mn705-00009-3v0-e 397
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 8 4.1. port data register 00 to 13, a to h : pdr00 to pdr13, pdra to pdrh (port data register 00-13,a-h) the bit configuration of p ort d ata r egister 00 to 13, a to h is shown below. these registers hold the output levels of the pins corresponding to individual ports that are in output mode. ? pdr 00 to pdr12, pdrg : address 0000 h to 000c h , 0016 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value x x x x x x x x attribute r,rm/w r,rm/w r,rm/w r,rm/w r, rm/w r,rm/w r,rm/w r,rm/w ? pdr 13 : address 00 0d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value x x x x x x x x attribute r,rm/w r,rm/w r x ,w x r,rm/w r,rm/w r,rm/w r,rm/w r,rm/w ? pdr a to p drf : address 00 10 h to 00 15 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 2] reserved initial value x x x x x x 1 1 attribute r,rm/w r,rm/w r,rm/w r,rm/w r,rm/w r,rm/w r 1 ,w x r 1 ,w x ? pdr h : address 0017 h ( access : byte , h alf - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p3 reserved initial value 1 1 1 1 x 1 1 1 attribute r 1 ,w x r 1 ,w x r 1 ,w x r 1 ,w x r,rm/w r 1 ,w x r 1 ,w x r 1 ,w x mb91590 series mn705-00009-3v0-e 398
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 9 [ bit7 to bit0 ] p (port) : port data setting bits these bits set the output level o f external pins p000, p001, ..., when the ports are in output mode. pdr 00: p[7:0] is for external pins p007 to p000 pdr 01: p[7:0] is for external pins p017 to p010 pdr 02: p[7:0] is for external pins p027 to p020 (a similar process continues) the assignment is as shown above. p[n] operation 0 output of "0" 1 output of "1" the value read by a read - modify instruction is determined based on the combination with the data direction register (ddr). ddr reading by read - modify instruction pdr reading value 1 no t he pdr value can be read. 1 yes the pdr value can be read. 0 no the pin value can be read. 0 yes the pdr value can be read. pdr13[7:6] is reserved because the built - in sub clock products (dual clock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 399
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 10 4.2. data direct ion register 00 to 13, a to h : ddr00 to ddr13, ddra to ddrh (data direction register 00-13,a-h) the bit configuration of d ata d irection r egister 00 to 13, a to h is shown below. . these registers set the i/o directions of the pins when they function as po rts. if a pin is to be used for input for a peripheral, the corresponding bit must be set for input. ? ddr 00 to ddr1 2 , ddrg : address 0e00 h to 0e0c h , 0e 16 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? ddr13 : address 0e0 d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r0,w0 r/w r/w r/w r/w r/w ? ddr a to ddrf : address 0e 10 h to 0e 15 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 2] reserved initial value 0 0 0 0 0 0 1 1 attribute r/w r/w r/w r/w r/w r/w r 1, w x r 1, w x ? ddr h : address 0e 17 h ( access : byte , half - wo rd , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p3 reserved initial value 1 1 1 1 0 1 1 1 attribute r 1 , w x r 1 ,wx r 1, w x r 1 , w x r/w r 1 , w x r 1 , w x r 1 , w x mb91590 series mn705-00009-3v0-e 400
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i /o ports fujitsu semiconductor confidential 11 [b it7 to bit 0] p (port) : d ata direction selection bits these bits set the i/o direction o f external pins p000, p001, ..., when the ports are in output mode. ddr 00: p[7:0] is for external pins p007 to p000 ddr 01: p[7:0] is for external pins p017 to p010 ddr 02: p[7:0] is for external pins p027 to p020 (a similar process continues) the assignment i s as shown above. p[n] operation 0 input ( initial value ) 1 output ddr13[7:6] is reserved because the built - in sub clock products (dual clock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 401
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 12 4.3. port function register 00 to 13, a to h : pfr 00 to pfr13, pfra to pfrh (port function register 00-13,a-h) the bit configuration of p ort f unction r egister 00 to 13 , a to h is shown below. . these registers specify whether or not the pins are used to function as ports. if a pin is to be used as a peripheral's input pin, the c orresponding bit register must be set for the port function. ? pfr 00 to pfr04, pfr06 to pfr08, pfr10, pfr11 : address 0e20 h , to 0e24 h , 0e2 6 h t o 0e 28 h , 0e2 a h , 0e2 b h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial v alue 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? pfr 05 : address 0e2 5 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p[6:0] initial value 0 0 0 0 0 0 0 0 attribute r 0 , w 0 r/w r/w r/w r/w r/w r/w r/w ? pfr 09, pfr12 : address 0e2 9 h , 0e2 c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7] reserved p[5:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r 0, w 0 r/w r/w r/w r/w r/w r/w ? pfr 13 : address 0e2 d h ( access : byte , half -w ord , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p[4:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r/w r/w r/w r/w r/w mb91590 series mn705-00009-3v0-e 402
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 13 ? pfr a to pfrc : address 0e 30 h to 0e 32 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved initial value 0 0 0 0 0 0 1 1 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 1, w x r 1, w x ? pfr d to pfrf : address 0e 33 h to 0e 35 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:2] reserved initial va lue 0 0 0 0 0 0 1 1 attribute r / w r / w r / w r / w r / w r / w r 1, w x r 1, w x ? pfr g : address 0e 36 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:3] reserved initial value 0 0 0 0 0 0 0 0 attribute r / w r / w r / w r / w r / w r 0, w 0 r 0, w 0 r 0, w 0 ? pfr h : address 0e37 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved initial value 1 1 1 1 0 1 1 1 attribute r 1 , w x r 1 , w x r 1, w x r 1 , w x r 0, w 0 r 1 , w x r 1 , w x r 1 , w x [b it7 to bit 0] p (port) : port function selection bits these bits are used to set the port function. pfr 00: p[7:0] is for external pins p007 , p006 to p000 pfr 01: p[7:0] is for external pins p017 , p016 to p010 pfr 02: p[7:0] is for external pins p027 , p026 to p020 (a similar process continues) the assignment is as shown above. p[n] operation 0 port function or peripheral input pin ( initial value ) 1 peripheral i/o (bidirectional) pin, peripheral output pin, or external bus pin (set by epfr ) mb91590 series mn705-00009-3v0-e 403
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 14 4.4. input data direct register 00 to 13, a to h : pddr00 to pddr13, p ddra to pddrh (port data direct register 00-13,a-h) t he bit configuration of input d ata d irect r egister 00 to 13, a to h is shown below. these registers can always show the voltage levels of individual external pins. these registers can always be read with out condition . ? pddr 00 to pddr12, pddrg : address 0e40 h to 0e4 c h , 0e56 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value x x x x x x x x attribute r , w x r , w x r , w x r , w x r , w x r , w x r , w x r , w x ? pddr 13 : address 0e4 d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value x x 0 x x x x x attribute r , w x r , w x r 0 , w x r , w x r , w x r , w x r , w x r , w x ? pddr a to pddrf : address 0e 50 h to 0e55 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 2] reserved initial value x x x x x x 1 1 attribute r , w x r , w x r , w x r , w x r , w x r , w x r 1, w x r 1, w x ? pddrh : address 0e57 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rese rved p3 reserved initial value 1 1 1 1 x 1 1 1 attribute r 1, w x r 1, w x r 1, w x r 1, w x r , w x r 1, w x r 1, w x r 1, w x mb91590 series mn705-00009-3v0-e 404
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 15 [b it7 to bit 0 ] p (port) : read bits the value at the external pin can be read. pddr 00: p[7:0] is for external pins p007 to p000 pddr 01: p[7:0] is for external pins p017 to p010 pddr 02: p[7:0] is for external pins p027 to p020 (a similar process continues) the assignment is as shown above. p[n] operation 0 low level 1 high level pd d r13[7:6] is reserved because the built - in sub clock products (dual c lock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 405
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 16 4.5. port pull - up/down control register 00 to 13, a to h : ppcr 00 to ppcr13, ppcra to ppcrh (port pull - up/down control register 00-13,a-h) the bit configuration of p ort p ull - up/down c ontrol r egister 00 to 13, a to h is shown below. these registers are used to select pull - up or pull - down for each port . these registers are functioned for input condition pins only . these registers are combined with the pull - up/down enable register (pper) for this setting. ? ppcr 00 to ppcr12, pcrg : address 0ea0 h to 0e ac h , 0e b6 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 1 1 1 1 1 1 1 1 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? ppcr 13 : address 0e ad h ( access : byte , half - word , w ord ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value 1 1 1 1 1 1 1 1 attribute r/w r/w r / w r/w r/w r/w r/w r/w ? ppcr a to ppcrf : address 0e b0 h to 0e b5 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 2] reserved initial value 1 1 1 1 1 1 1 1 attribute r/w r/w r/w r/w r/w r/w r 1, w x r 1, w x ? ppcr h : address 0e b7 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p3 reserved initial value 1 1 1 1 1 1 1 1 a ttribute r 1 , w x r 1 , w x r 1, w x r 1 , w x r/w r 1 , w x r 1 , w x r 1 , w x mb91590 series mn705-00009-3v0-e 406
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 17 [b it7 to bit 0] p (port) : pull - up/down control selection bits ppcr 00: p[7:0] is for external pins p007 to p000 ppcr 01: p[7:0] is for external pins p017 to p010 ppcr 02: p[7:0] is for external pins p027 to p020 (a similar process continues) the assignment is as shown above. p[n] operation 0 pull - down 1 pull - up ( initial value ) see "9. list of pin functions" and "11. i/o circuit types" of "chapter : overview" for the presence of pull - up/pull - down. ppc r13: bit 5 is a reserved bit. writing and reading are not effective. ppc r13:p[7:6] is a reserv ed bit in dual clock products. writing and reading are not effective. mb91590 series mn705-00009-3v0-e 407
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 18 4.6. port pull -up/down enable register 00 to 13, a to h : pper 00 to pper13, ppera to pper h (port pull -up/down enable register 00-13,a-h) the bit configuration of p ort p ull - up/down e nable r egister 00 to 13, a to h is shown below. these registers are used to enable pull - up or pull - down each port. these registers are functioned for input conditi on pins only. these registers are combined with the pull - up/down control register (ppcr) for this setting. ? pper 00 to pper12, pperg : address 0ec0 h , 0ec1 h to 0e cc h , 0e d6 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? pper 13 address 0ec d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/ w r/w r/w r/w ? pper a to pperf : address 0e d0 h to 0e d5 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 2] reserved initial value 0 0 0 0 0 0 1 1 attribute r/w r/w r/w r/w r/w r/w r 1, w x r 1, w x ? pper h : address 0e d7 h ( acces s : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p3 reserved initial value 1 1 1 1 0 1 1 1 attribute r 1 , w x r 1 , w x r 1, w x r 1 , w x r/w r 1 , w x r 1 , w x r 1 , w x mb91590 series mn705-00009-3v0-e 408
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 19 [ bit 7 to bit 0] p ( port) : pull - up/down enable selection bits pper 00: p[7:0] is for external pins p007 to p000 pper 01: p[7:0] is for external pins p017 to p010 pper 02: p[7:0] is for external pins p027 to p020 (a similar process continues) the assignment is as shown above. p[n] operation 0 pull - up/down disabled ( initial valu e) 1 pull - up/down enabled see "9. list of pin functions" and "11. i/o circuit types" of "chapter : overview" for the presence of pull - up/pull - down of each port . the attribute of pper13[5] is r/w. write does no t cause any effect. p pe r13[7:6] is reserved b ecause the built - in sub clock products ( dual clock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 409
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 20 4.7. port input level selection register 00 to 13, a to h : pilr 00 to pilr13, pilra to pilrh (port input level register 00- 13, a -h) the bit configuration of p ort i nput l evel selection r egister 00 to 13, a to h is shown below. these registers are used to set input levels for individual ports. glitch input may occur at a pin. therefore, if the pin is used to supply external input clock or trigger to a peripheral, the peri pheral must be disabled. these registers, when used, are paired with the extended port input level selection register (epilr) . ? pilr 00 to pilr12, pilrg : address 0ee0 h to 0e ec h , 0e f6 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 1 1 1 1 1 1 1 1 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? pilr 13 : address 0ee d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value 1 1 1 1 1 1 1 1 attribute r/w r/w r 1, w 1 r/w r/w r/w r/w r/w ? pilr a to pilrf : address 0e f0 h to 0e f5 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 2] reserved initial value 1 1 1 1 1 1 1 1 attribute r/w r/w r/w r/w r/w r/w r 1, w x r 1, w x ? pilr h : addre ss 0e f7 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved p3 reserved initial value 1 1 1 1 1 1 1 1 attribute r 1 , w x r 1 , w x r 1, w x r 1 , w x r/w r 1 , w x r 1 , w x r 1 , w x mb91590 series mn705-00009-3v0-e 410
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 21 [b it7 to bit 0] p (port) : port input level selection bits pilr 00: p[7:0] is for external pins p007 to p000 pilr 01: p[7:0] is for external pins p017 to p010 pilr 02: p[7:0] is for external pins p027 to p020 (a similar process continues) the assignment is as shown above. ( port setting in 5v interface ) p06x,p07x,p08x,p09x,p10x,p11x,p12x,p13x pilr :p[n] epilr :p[n] input level remarks 0 0 cmos schmitt v il =0.3vcc v ih =0.7vcc 0 1 ttl v il =0.8[v] v ih =2. 0[v] 1 0 automotive v il =0.5vcc v ih =0.8vcc initial value 1 1 cmos v il =0. 3v cc v ih =0. 7v cc ( port setting in 3.3v in terface ) p00x,p01x,p02x,p03x,p04x,p05x,pax,pbx,pcx,pdx, pex,pfx,pgx,phx pilr :p[n] input level remarks 0 ttl v il =0.8[v] v ih =2. 0[v] 1 cmos schmitt v il =0. 3v cc v ih =0. 7v cc initial value pilr 13[7:6] is reserved because the bui lt- in sub clock products (dual clock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 411
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 22 4.8. extended port input level selection register 06 to 13 : epilr 06 to epilr13 (extended port input level register 06-13) the bit configuration of e xtended p ort i nput l evel selectio n r egister 06 to 13 is shown below. these registers, when used, are paired with the port input level selection register (pilr). see ? 4.7. port input level selection register 00 to 13, a to h: pilr00 to pilr13, pilra to pilrh (port input level register 00 -1 3,a - h) ?. ? epilr 06 to epilr12 : address 0f0 6 h to 0f0c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? epilr 13 : address 0f0 d h ( access : byte , hal f- word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w [b it7 to bit 0] p (port) : extended port input level selection bits epilr0 6: p[7:0] is for external p ins p0 67 to p0 60 epilr 07: p[7:0] is for external pins p0 77 to p0 70 epilr 08: p[7:0] is for external pins p0 87 to p0 80 (a similar process continues) the assignment is as shown above. for settings, see the section of pilr. the attribute of epilr 13[5] is r/w. w rite does no t cause any effect. epilr13 [7:6] is reserved because the built - in sub clock products (dual clock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 412
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 23 4.9. port output drive register 06 to 13 : podr 06 to podr13 (port output drive register 06-13) the bit configur ation of p ort output drive r egister 06 to 13 is shown below. these registers are used to set drive levels for individual ports. ? podr 06 to podr12 : address 0f2 6 h to 0f2c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? podr 13 : address 0f2 d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7: 6] reserved p[4:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/ w r/w r/w r/w [b it7 to bit 0] p (port) : port output drive selection bits podr 06: p[7:0] is for external pins p0 67 to p0 60 podr 07: p[7:0] is for external pins p0 77 to p0 70 podr 08: p[7:0] is for external pins p0 87 to p0 80 (a similar process continues) the as signment is as shown above. p[n] operation 0 1 ma 1 2 m a [only p127, p130, p132, and p133 pins] when the multi - function serial interface is selected and i 2 c has been selected by the operational mode of the multi - function serial interface, it becomes 3 m a. in other cases, the setting in the above table needs to be followed. the drive level of a pin that doubles as the output pin for a stepping motor controller can be set to be 1 ma/ 2 ma/30 ma by the combination with a extended port output drive register (epodr) setting. if a pin is specified as the output pin for a stepping motor controller, the drive level at the pin must be 30ma regardless of the podr register setting. podr:p[n] epodr:p[n] operation remarks 0 0 1 ma initial value 1 0 2 m a 0 1 30 m a 1 1 2 ma mb91590 series mn705-00009-3v0-e 413
chapter 1 1: i/o ports 4 . registe rs fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 24 the attribute of pod r 13[5] is r/w. write does no t cause any effect. pod r13 [7:6] is reserved bec a use the built - in sub clock products ( dual clock products ) do not have the assigned pins. mb91590 series mn705-00009-3v0-e 414
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 25 4.10. extended port output drive register 06 to 08 : e podr 06 t o epodr08 ( extended port output drive register 06-08) the bit configuration of e xtended p ort output drive r egister 06 to 08 is shown below. these registers are used to set drive levels for smc ports. ? e podr 06 to epodr08 : address 0f 38 h to 0f 3a h ( access : by te , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p[7:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w see " 4.9 . port output drive register 06 to 13 : podr 06 to podr13 (port output drive register 06- 13) " for the setting. mb91590 series mn705-00009-3v0-e 415
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 26 4.11. extended port output drive register for graphic digital interface : e podr gd the bit configuration of the e xtended p ort output drive r egister gdc interface is shown below. th is register is used to set drive levels (2ma/5ma/10ma/20ma) for graphic digital i/f in each group . ? e podr gd: address 0f3c h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gdi1[1:0] gdi0[1:0] initial value 1 1 1 1 1 0 1 0 attribute r 1 ,w x r 1 ,w x r 1 ,w x r 1 ,w x r/w r/w r/w r/w [b it 3, bit2] gdi1[1:0] gdc interface port output drive select ion bits 1 these bits select following port output drive. pg[4] gdi1[1:0] operation 00 2 ma 01 5 ma 10 10 ma ( initial value ) 11 20 ma [b it 1, bit1] gdi0[1:0] gdc interface port output drive select ion bits 0 these bits select following port output drive. pa[7:2] , pb[7:2] , pc[7:2] , pd[7:2] , pe[7:2] , pf[7:2] , pg[7:5] , pg[3:0] , ph[3] gdi0[1:0] operation 00 2 ma 01 5 ma 10 10 ma ( initial value ) 11 20 ma mb91590 series mn705-00009-3v0-e 416
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 27 4.12. ex tended port output drive register for graphic flash interface : epodrgf the bit configuration of the e xtended p ort output drive r egister for the graphic flash interface is shown below . th is register is used to set drive levels (2ma/5ma/10ma/20ma) for graphi c flash interface in each group . ? e podr gf: address 0f3d h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gfi2[1:0] gfi 1 [1:0] gfi 0 [1:0] initial value 1 1 1 0 1 0 1 0 attribute r 1 ,w x r 1 ,w x r/w r/w r/w r/w r/w r/w [b it 5 , bit 4 ] gfi2[1:0] graphic flash interface port output drive select ion bits 2 these bits select following port output drive. p05[6:3] gfi2[1:0] operation 00 2 ma 01 5 ma 10 10 ma ( initial value ) 11 20 ma [b it 3, bit2] gfi1[1:0] graphic flash interface port output drive select ion bits 1 these bits select following port output drive. p03[7], p04[7:0] gfi1[1:0] operation 00 2 ma 01 5 ma 10 10 ma ( initial value ) 11 20 ma mb91590 series mn705-00009-3v0-e 417
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o p orts fujitsu semiconductor confidential 28 [b it 1, bit0 ] gfi0[1:0] graphic flash interface port output drive select ion bit s 0 these bits select following port output drive. p 00 [7: 0] , p 01 [7: 0] , p 02 [7: 0] , p 03 [6:0] , p 05 [7] , p 05 [2:0] gf i0[1:0] operation 00 2 ma 01 5 ma 10 10 ma ( initial value ) 11 20 ma mb91590 series mn705-00009-3v0-e 418
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 29 4.13. extended port function register 00 to 55 : epfr00 to epfr55 (extended port function register 00 -55) the bit configuration of extended p ort function r egister 00 to 55 is shown below. these registers control switching between the peripheral and the external bus, i/o relocation and i/o multi - plexing. unlike other port registers, these registers have an enable bit for each peripheral, rather than for each pin. when i/o relocation is executed, glitch occurs by switching and operation may happen by recognition as a signal change. therefore, execute i/o relocation for input neglecting inputs from peripheral resource. the external interrupt flag must be cleared before the interrupt is enabled. pin assignment to peripheral resources is made by the registers of pfr and epfr. however, since all registers cannot be changed at one time, i/ o relocation for outputs must be executed in the port setting state ( pfrn :p[n]=0). mb91590 series mn705-00009-3v0-e 419
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 30 4.13.1. extended port function register 00, 0 1 : epfr00 , epfr 01 (extended port function register 00 , 01) the bit configuration of e xtended p ort function r egister 00, 01 is shown be low. these registers are used to select input pins for input capture. (i/o relocation) ? epfr00 : address 0e60 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icu3e[1:0] icu2e[1:0] icu1e[1:0] icu0e[1:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? epfr01 : address 0e61 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved icu5e[1:0] icu4e[1:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r/w r/w r /w r/w [ bit7 to bit4 ] reserved bits th ese bit s must be written to "0". icu0e[1:0] input capture ch .0 input pin selection icu1e[1:0] input capture ch .1 input pin selection icu2e[1:0] input capture ch .2 input pin selection icu3e[1:0] input capture ch.3 input pin selection icu4e[1:0] input capture ch .4 input pin selection icu5e[1:0] input capture ch .5 input pin selection icune[1:0] (n=0 to 5 ) operation 00 input from the icun pin 01 input from the icun_1 pin 10 input from the icun_2 pin 11 reserv ed ( input from the icun_2 pin ) mb91590 series mn705-00009-3v0-e 420
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 31 4.13.2. extended port function register 02 to 05 : epfr02 to epfr 05 (extended port function register 02-05) the bit configuration of e xtended p ort function r egister 02 to 05 is shown below. these registers are used to enable reload timer output and to select output/input pins. (i/o relocation and i/o multiplexing) ? epfr02 : address 0e62 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tot0e[2:0] tin0e[1:0] initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr03 : address 0e63 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tot1e[2:0] tin1e[1:0] initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr 04 : address 0e64 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tot2e[2:0] tin2e[1:0] initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr05 : address 0e65 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tot3e[2:0] tin3e[1:0] initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w tot0e[2:0] reload timer ch . 0 tot output pin selection tin0e[1:0] reload timer ch . 0 tin in pu t pin selection tot1e[2:0] reload timer ch . 1 tot output pin selection tin1e[1:0] reload timer ch . 1 tin in put pin selection tot2e[2:0] reload timer ch . 2 tot output pin selection tin2e[1:0] reload timer ch . 2 tin in put pin selection tot3e[2:0] reload timer ch . 3 tot output pin selection tin3e[1:0] reload timer ch . 3 tin in put pin selection mb91590 series mn705-00009-3v0-e 421
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 32 totne[2:0] (n=0 to 3) operation 000 no output xx1 output from the totn pin x1x output from the totn_1 pin 1xx output from the totn_2 pin tinne[1:0] (n=0 to 3) operation 00 input from the tinn pin 01 input from the tinn_1 pin 10 input from the tinn_2 pin 11 reserved ( input from the tinn_2 pin ) mb91590 series mn705-00009-3v0-e 422
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 33 4.13.3. extended port function register 06 to 09 , 33, 34 : epfr06 to epfr 09, epfr33, epfr34 (extended port function register 06 -09,33,34) the bit configuration of e xtended p ort function r egister 06 to 09, 33, 34 is shown below. these registers are used to enable lin - uart output and to select output/input pins. (i/o relocation and i/o multiplexing) no te: please set sc k/sot/sin of lin -u art to the same group (sckn/sotn/sinn or sckn_1/sotn_1/ sinn_1). it is a prohibition to do relocations as disjointedly as the following examples. prohibition example sckn/sotn_1/sinn ? epfr06 : address 0e66 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot2e[1:0] sck2e[1:0] sin2e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr07 : address 0e67 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot3e[1:0] sck3e[1:0] sin3e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr08 : address 0e68 h ( access : byt e , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot4e[1:0] sck4e[1:0] sin4e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr09 : address 0e69 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 reserved sot5e[1:0] sck5e[1:0] sin5e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w mb91590 series mn705-00009-3v0-e 423
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 34 ? epfr 33 : address 0e 81 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot 6 e[1:0] sck 6 e[1:0] sin 6e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr 34 : address 0e 82 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot 7 e[1:0] sck 7 e[1:0] sin 7e initial valu e 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w sot2e[1:0] l in - uart ch . 2 sot output pin selection sck2e[1:0] l in - uart ch . 2 sck output/ in put pin selection sin2e lin - uart ch . 2 sin in put pin selection sot3e[1:0] l in - uart ch . 3 sot output pin selection sck3e[1:0] l in - uart ch . 3 sck output/ in put pin selection sin3e lin - uart ch . 3 sin in put pin selection sot4e[1:0] l in - uart ch . 4 sot output pin selection sck4e[1:0] l in - uart ch . 4 sck output/ in put pin selection sin4e lin - uart ch . 4 sin in put pin selection sot5e[1:0] l in - uart ch . 5 sot output pin selection sck5e[1:0] lin - uart ch . 5 sck output/ in put pin selection sin5e l in - uart ch . 5 sin in put pin selection sotne[1:0] (n= 2 to 5 ) operation 00 no output 01 output from the sotn pin 1x output from th e sotn_1 pin sckne[1:0] (n= 2 to 5 ) operation 00 non input/output from the sckn 01 input from the sckn / output from the sckn 10 input from the sckn_1 / output from the sckn_1 11 reserved ( input from the sckn_1 / output from the sckn_1) sinne (n= 2 to 5 ) operation 0 input from the sinn pin 1 input from the sinn_1 pin mb91590 series mn705-00009-3v0-e 424
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 35 sot 6 e[1:0] l in - uart ch .6 sot output pin selection sck 6 e[1:0] l in - uart ch .6 sck output / in put pin selection sin 6e l in - uart ch .6 sin in put pin selection sotne[1:0] (n= 6 ) operation 0 0 no output 01 o utput from the sotn pin 1x setting is prohibited sckne[1:0] (n= 6 ) operation 00 no input / output from the sckn pin 01 in put from the sckn / output from the sckn 10 setting is prohibited 11 setting is prohibited sinne (n= 6 ) opera tion 0 input from the sinn pin 1 setting is prohibited sot 7 e[1:0] l in - uart ch .7 sot output pin selection sck 7 e[1:0] l in - uart ch .7 sck output/ in put pin selection sin 7e l in - uart ch .7 sin in put pin selection sotne[1:0] (n= 7 ) operation 00 no output 01 setting is prohibited 1x output from the sotn_1 pin sckne[1:0] (n= 7 ) operation 00 no input/output from the sckn 01 setting is prohibited 10 input from the sckn_1 / output from the sckn_1 11 reserved ( input from the sckn_1 / output from the sckn_1) sinne (n= 7 ) operation 0 setting is prohibited 1 input from the sinn_1 mb91590 series mn705-00009-3v0-e 425
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 36 4.13.4. extended port function register 10 to 15 , 45, 46 : epfr10 to epfr 15, epfr45, epfr46 (extended port function register 10 -15,45,46) the bit configuration of e xtended p ort function re gister 10 to 15, 45, 46 is shown below. these registers are used to enable ppg output and to select output pins. (i/o relocation and i/o multiplexing) ? epfr10 : address 0e6a h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 res erved ppg1e[ 3 :0] ppg0e[2:0] initial value 1 0 0 0 0 0 0 0 attribute r1,wx r/w r/w r/w r/w r/w r/w r/w ? epfr11 : address 0e6b h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppg3e[2:0] ppg2e[2:0] initial value 1 1 0 0 0 0 0 0 attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w ? epfr12 : address 0e6c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppg5e[2:0] ppg4e[2:0] initial value 1 1 0 0 0 0 0 0 attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w ? epfr13 : address 0e6d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppg7e[2:0] ppg6e[2:0] initial value 1 1 0 0 0 0 0 0 attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w ? epfr14 : address 0e6e h ( access : b yte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppg9e[2:0] ppg8e[2:0] initial value 1 1 0 0 0 0 0 0 attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w mb91590 series mn705-00009-3v0-e 426
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 37 ? epfr15 : address 0e6f h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bi t 3 bit 2 bit 1 bit 0 reserved ppg12e[1:0] ppg11e[1:0] ppg10e[2:0] initial value 1 0 0 0 0 0 0 0 attribute r1,wx r/w r/w r/w r/w r/w r/w r/w ? epfr 45 : address 0e 8d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppg17e ppg16e ppg15e[1:0] ppg14e[1:0] ppg1 3 e[ 1 :0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? epfr 46 : address 0e 8e h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ppg 23 e ppg 22 e ppg 21 e ppg 20 e ppg1 9e ppg1 8e initial value 1 1 0 0 0 0 0 0 attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w ppg0e[2:0] ppg ch . 0 output pin selection ppg2e[2:0] ppg ch . 2 output pin selection ppg3e[2:0] ppg ch . 3 output pin selection ppg4e[2:0] ppg ch . 4 output pin selection p pg5e[2:0] ppg ch . 5 output pin selection ppg6e[2:0] ppg ch . 6 output pin selection ppg7e[2:0] ppg ch . 7 output pin selection ppg8e[2:0] ppg ch . 8 output pin selection ppg9e[2:0] ppg ch . 9 output pin selection ppg10e[2:0] ppg ch . 10 output pin selection pp gne[2:0] (n=0 ,2 to 10) operation 000 no output xx1 output from the ppgn pin x1x output from the ppgn_1 pin 1xx output from the ppgn_2 pin mb91590 series mn705-00009-3v0-e 427
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 38 ppg1e[ 3 :0] ppg ch . 1 output pin selection ppgne[ 3 :0] (n= 1 ) operation 000 0 no output x xx1 output from the pp gn pin x x1x output from the ppgn_1 pin x 1xx output from the ppgn_2 pin 1xxx output from the ppgn_ 3 pin ppg 11 e[ 1 :0] ppg ch .11 output pin selection ppg1 2 e[ 1 :0] ppg ch .12 output pin selection ppg 13 e[ 1 :0] ppg ch .13 output pin selection ppg1 4 e[ 1 :0] ppg ch .14 output pin selection ppg1 5 e[ 1 :0] ppg ch .15 output pin selection ppgne[ 1 :0] (n= 11 to 1 5 ) operation 0 x no output 1x output from the ppgn_1 pin ppg 16 e ppg ch .16 output pin selection ppg1 7 e ppg ch .17 output pin selection ppg 18 e ppg ch .18 output pin selection ppg1 9 e ppg ch .19 output pin selection ppg 20 e ppg ch .20 output pin selection ppg 21 e ppg ch .21 output pin selection ppg 22 e ppg ch .22 output pin selection ppg 23 e ppg ch .23 output pin selection ppgne (n= 16 to 23 ) operation 0 no output 1 output from the ppgn pin mb91590 series mn705-00009-3v0-e 428
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 39 4.13.5. extended port function register 21 to 23 : epfr21 to epfr 23 (extended port function register 21-23) the bit configuration of e xtended p ort function r egister 21 to 23 is shown below. these registers are used to enable stepping mot or controller output. (i/o multiplexing) ? epfr21 : address 0e75 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm2m1e pwm2p1e pwm1m1e pwm1p1e pwm2m0e pwm2p0e pwm1m0e pwm1p0e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/ w r/w r/w r/w r/w r/w ? epfr22 : address 0e76 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm2m3e pwm2p3e pwm1m3e pwm1p3e pwm2m2e pwm2p2e pwm1m2e pwm1p2e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? epfr23 : address 0e77 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pwm2m5e pwm2p5e pwm1m5e pwm1p5e pwm2m4e pwm2p4e pwm1m4e pwm1p4e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w pwm2mne (n=0 to 5) smc ch annel n pwm control (m2) output enable pwm2pne (n=0 to 5) smc ch annel n pwm control (p2) output enable pwm1mne (n=0 to 5) smc ch annel n pwm control (m1) output enable pwm1pne (n=0 to 5) smc ch annel n pwm control (p1) output enable pwm2mne (n=0 to 5) operation 0 smc channel n pwm m2 output disabled ( initial value ) 1 smc channel n pwm m2 output enabled pwm2pne , pwm1mne and pwm1pne (n=0 to 5) are also similar to pwm2mne . mb91590 series mn705-00009-3v0-e 429
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 40 4.13.6. extended port function register 24 : epfr24 (extended port function r egister 24) the bit configuration of e xtended p ort function r egister 24 is shown below. th is register is used to enable can output. (i/o multiplexing) ? epfr24 : address 0e78 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rese rved tx2e tx1e tx0e initial value 1 1 1 1 1 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w r/w txne (n=0 to 2) : can ch annel n transmission data output enabled txne (n=0 to 2) operation 0 can c h annel n output disabled ( initial value ) 1 can c h annel n output enabled mb91590 series mn705-00009-3v0-e 430
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited ch apter: i/o ports fujitsu semiconductor confidential 41 4.13.7. extended port function register 25 : epfr25 (extended port function register 25) the bit configuration of e xtended p ort function r egister 25 is shown below. this register is a reserved register. ? epfr25 : address 0e79 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr25d[2:0] initial value 1 1 1 1 1 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r / w0 r / w0 r / w0 epfr25d[2:0] : reserved bits "0" must be written to th ese bit s. mb91590 series mn705-00009-3v0-e 431
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 42 4.13.8. extended port function register 26 : epfr26 (extended port function register 26) the bit configuration of e xtended p ort function r egister 26 is shown below. th is register is used to enable base timer output. (i/o multiplexing) ? epfr26 : address 0e7a h ( access : byte , hal f- word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tib1e tib0e tia1e tia0e initial value 1 1 1 1 0 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r/w r/w r/w r/w tibne (n=0 , 1) reserved bits setting to these bits does not affect on the operati on. tiane (n=0 , 1 ) base timer tioan output enable tiane (n=0 , 1) operation 0 base timer tioan output disabled ( initial value ) 1 base timer tioan output enabled mb91590 series mn705-00009-3v0-e 432
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 43 4.13.9. extended port function register 27, 30 : epfr27 , epfr30 (extended port function register 27 ,30) the bit configuration of e xtended p ort function r egister 27, 30 is shown below. these registers are used to enable the real - time clock and sound generator output. (i/o multiplexing and i/o relocation ) ? epfr27 : address 0e7b h ( access : byte , half - word , wo rd ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved wote sgo1e sga1e sgo0e sga0e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr 30 : address 0e7 e h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sgo 4e [1:0] sga 4e [1:0] sgo 3e sga 3e sgo 2e sga 2e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w sgane (n=0 to 3) sound generator channel n sga output enable sgone (n=0 to 3) sound generator channel n sgo output enable wote real time clock overflow output enable sgane (n=0 to 3 ) operation 0 sound generator channel n sga output disabled ( initial value ) 1 sound generator channel n sga output enabled sgone (n=0 to 3) and wote are also similar to the above. sga 4 e [1:0] sound generator channel 4 sga output enable sgo 4 e [1:0] sound generator channel 4 sgo output enable sga 4 e [1:0] operation 0 0 sound generator channel 4 sga output disabled ( initial value ) 0 1 setting prohibited 10 output from the sg4_1 11 setting is p rohibited sgo 4e [1:0] are also similar to the above. mb91590 series mn705-00009-3v0-e 433
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 44 4.13.10. extended port function register 28 : epfr28 (extended port function register 28) the bit configuration of e xtended p ort function r egister 28 is shown below. th is register is used to enable free - run timer clock in put. (i/o multiplexing ) ? epfr28 : address 0e7c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved frck1e frck0e initial value 1 1 1 1 0 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r 0, w 0 r 0, w 0 r/w r/w [bit2, bit3] reserved "0" must always be written to these bits. [bit1] frck1e : free - run timer ch.1 clock input selection enable [ bit0 ] frck 0e : free - run timer ch .0 clock input selection enable frckn e (n=0, 1) operation 0 input from the frckn ( ini tial value ) 1 setting is prohibited mb91590 series mn705-00009-3v0-e 434
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 45 4.13.11. extended port function register 29 : epfr29 (extended port function register 29) t he bit configuration of e xtended p ort f unction r egister 29 is shown below. th is register is used to enable output compare out put. (i/o multiplexing and i/o r elocation ) ? epfr29 : address 0e7d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocu3e[1:0] ocu2e[1:0] ocu1e[1:0] ocu0e[1:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w oc une[1:0] (n=0 to 3 ) output compare channel n output enabled ocune [1:0] (n=0 to 3) operation 0 0 output compare channel n output disabled ( initial value ) 0 1 o u tput from the ocun 10 setting is prohibited 11 setting is prohibited mb91590 series mn705-00009-3v0-e 435
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 46 4.13.12. extended port function register 35, 36 : epfr 35, epfr36 (extended port function register 35,36) t he bit configuration of e xtended p ort f unction r egister 35, 36 is shown below. these registers are used to enable multi - function serial interface output . (i/o multiplexing and i/o r elocation ) ? epfr 35 : address 0e 83 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot 0 e[1:0] sck 0 e[1:0] sin 0e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr 36 : address 0e 84 h ( ac cess : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sot 1 e[1:0] sck 1 e[1:0] sin 1e initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w sot0e [1:0] : multi - function serial interface ch . 0 sot output/input pin selection sck0e [1:0] : multi - function serial interface ch . 0 sck output/input pin selection s in 0e : multi - function serial interface ch . 0 s in input pin selection sot 1 e [1:0] : multi - function serial interface ch .1 sot output/inpu t pin selectio n sck 1 e [1:0] : multi - function serial interface ch .1 sck output/input pin selection s in1 e : multi - function serial interface ch .1 s in input pin selection s otne[1:0] (n=0,1) operation 0 0 no output 0 1 input from the sotn pin / o u tput from the sotn pin 1 x setting is prohibited s ckne[1:0] (n=0,1) operation 0 0 no input/output from the sckn 0 1 input from the sckn / o u tput from the sckn 1 0 setting is prohibited 1 1 setting is prohibited mb91590 series mn705-00009-3v0-e 436
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 47 s inne (n=0,1) operation 0 input from the sinn pin 1 setting is prohibited mb91590 series mn705-00009-3v0-e 437
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 48 4.13.13. extended port function register 48 to 50 : epfr 48 to epfr50 (extended port function register48- 50 ) t he bit configuration of e xtended p ort f unction r egister 48 to 50 is shown below. these registers are used to set enable/disable for display rgb signal output. ? epfr 48 : address 0e 90 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rout7e rout6e rout5e rout4e rout3e rout2e rout1e rout0e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? epfr 49 : address 0e 91 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gout7e gout6e gout5e gout4e gout3e gout2e gout1e gout0e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w ? epfr 50 : address 0e 92 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bout7e bout6e bout5e bout4e bout3e bout2e bout1e bout0e initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w routne (n= 0 to 7) display r[n] output enabled routne (n= 0 to 7) operation 0 display rgb(r[n]) output disabled ( initial value ) 1 display rgb(r[n]) output enabled goutne (n= 0 to 7) display g[n] output enabled goutne (n= 0 to 7) operation 0 display rgb(g[n]) output disabled ( initial value ) 1 display rgb(g [n]) output enabled mb91590 series mn705-00009-3v0-e 438
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 49 boutne (n= 0 to 7) display b[n] output enabled boutne (n= 0 to 7) operation 0 display rgb(b[n]) output disabled ( initial value ) 1 display rgb(b[n]) output enabled mb91590 series mn705-00009-3v0-e 439
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 50 4.13.14. extended port function register 51, 52 : epfr 51, epfr52 (extended port function register 51,52) t he bit configuration of e xtended p ort f unction r egister 51, 52 is shown below. these registers are used to set enable/disable for display control signal output and spi flash signal output . ? epfr 51 : address 0e 93 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved csoute hsoute vsoute dckoute deoute initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w r/w r/w r/w ? epfr 52 : address 0e 94 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved spisck spixcs spido initial value 1 1 1 1 1 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w r/w [ bit0 ] deoute : display effective term output enable [ bit1 ] dckoute : display output standard clock output e nable [ bit2 ] vsoute : display vertical sync signal output enable [ bit3 ] hsoute : display horizontal sync signal output enable [ bit4 ] csoute : display composite sync signal / graphics / video switch output enable deoute operation 0 display effective term output disabled ( initial value ) 1 display effective term output enabled dckoute, vsoute, hsoute and csoute are similar to the above. [ bit0 ] spido : spi flash data output enabled [ bit1 ] spixcs : spi flash chip select ion output enable [ bit2 ] spisck : spi f lash clock output enable spido operation 0 spi flash data output disabled ( initial value ) 1 spi flash data output enabled spixcs and spisck are similar to the above. . mb91590 series mn705-00009-3v0-e 440
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 51 4.13.15. extended port function register 55 : epfr 55 (extended port function register 55) t he bit configuration of e xtended p ort f unction r egister 55 is shown below. this register is used to set enable/disable for the external bus function. ? epfr 55 : address 0e 97 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved extbus1e extbus0e initial value 1 1 1 1 1 1 0 1 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w [ bit0 ] extbus 0e : external bus output enable 0 [ bit1 ] extbus 1e : external bus output enable 1 extbus1e extbus0e operation 0 0 external bus output di sabled regardless of pfr's setting 0 1 gdc external bus output enabled ( initial value ) 1 0 setting is prohibited 1 1 gdc external bus output enabled mb91590 series mn705-00009-3v0-e 441
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 52 4.13.16. extended port function register 16 to 20, 31, 32, 37 to 44 , 47, 53, 54 : epfr 16 to epfr20, epfr31, epfr 32, epfr37 to epfr44, epfr 47, epfr53, epfr54 (extended port function register 16-20, 31, 32, 37-44, 47, 53, 54) t he bit configuration of e xtended p ort f unction r egister 16 to 20, 31, 32, 37 to 44 ,47,53,54 is shown below. these are reserved registers. these must not be used. ? epfr16 : address 0e70 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr 16d[ 7 :0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr17 : address 0e71 h ( access : by te , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr 17d[ 7 :0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr18 : address 0e72 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 epfr 18d[ 7 :0] initial value 1 0 0 0 0 0 0 0 attribute r 1 , w 1 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr19 : address 0e73 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr 19d[ 7 :0] initial value 1 1 1 1 1 1 1 1 attribute r 1 , w 1 r1,w1 r1,w1 r1,w1 r1,w1 r1,w1 r1,w1 r1,w1 ? epfr20 : address 0e74 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr 20d[ 6 :0] initial value 1 1 1 1 1 1 1 1 attribute r / w 1 r 1 , w 1 r 1 , w 1 r 1 , w 1 r 1 , w 1 r 1 , w 1 r 1 , w 1 r 1 , w 1 mb91590 series mn705-00009-3v0-e 442
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 53 ? epfr 31 : address 0e7 f h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr 31d[ 7 :0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 32 : address 0e 80 h ( access : byt e , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr 32d[ 7 :0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 37 : address 0e 85 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bi t 1 bit 0 epfr 37d[ 7 :0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 38 : address 0e 86 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr 38d[ 4 :0] initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 39 : address 0e 87 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr 39d[ 7 :0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 40 : address 0e 88 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr 40d[ 5 :0] initial value 1 1 0 0 0 0 0 0 attribute r1,wx r1,wx r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 mb91590 series mn705-00009-3v0-e 443
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 54 ? epfr 41 : address 0e 89 h (a ccess: byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr 4 1d[ 2 :0] initial value 1 1 1 1 1 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 42 : address 0e8 a h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr 4 2d[ 1 :0] initial value 1 1 1 1 1 1 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r 0, w 0 r 0, w 0 ? epfr 43 : address 0e 8b h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr43d[7:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 44 : address 0e 8c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 epfr44d[7:0] initial value 0 0 0 0 0 0 0 0 attribute r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 ? epfr 47 : address 0e 8f h ( access : byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ep fr47d initial value 1 1 1 1 1 1 1 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r 0 ,w 0 ? epfr 53 : a ddress 0e 95 h ( access : byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr53d[4:0] initial value 1 1 1 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 mb91590 series mn705-00009-3v0-e 444
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 55 ? epfr 54 : address 0e 96 h ( access : byte, half - word, w ord ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved epfr54d[3:0] initial value 1 1 1 1 0 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r 0, w 0 r 0, w 0 r 0, w 0 r 0, w 0 mb91590 series mn705-00009-3v0-e 445
chapter 1 1: i/o ports 4 . registers fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 56 4.14. port input enable register : porte n( port enable register) t he bit configuration of the port input enable register is shown below. this register contains control - bit to enable port input. at a power - on reset, inputs to most pins are disabled in order to avoid pass - through current fluctuations before the ports are configured by software. for inform ation on pins whose inputs are disabled, see " appendix ?d: pin status in cpu status ? . after each port pin is configured for its function by software , global port e n able (gporten) bit must be set to ?1? to enable input. ? porten : address 0f40 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved gporten initial value 1 1 1 1 1 1 0 0 attribute r 1 ,wx r 1 ,wx r 1 ,wx r 1 ,wx r 1 ,wx r 1 ,wx r/w r/w [b it0 ] gporten (global port enable) : g lobal input enable gporten operation 0 most of p ins are set input - disabled to cut off pass - through current at unstable condition. see ? appendix -d : pin status in cpu status ? for the pin that is input - disabled at initial state by reset. 1 the input is enabled by this bit. mb91590 series mn705-00009-3v0-e 446
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 57 5. operation this section explai ns operation s of i/o ports. 5.1 . pin i/o assignment 5.2 . epfr setting priority 5.3 . notes on input i/o relocation setting 5. 4 . input interception by gporten 5. 5 . notes on pins with the ad converter function 5. 6 . setting when using the base timer tioa1 pin 5. 7 . operation at w ake u p from p ower s hutdown mb91590 series mn705-00009-3v0-e 447
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 58 5.1. pin i/o assignment the p in i/o a ssignment is shown below. pin i/o assignment is explained here . the i/o direction of each pin is cont rolled based on the configuration shown below. figure 5-1 configuration of pin i/o directions, output value selection, and input value retrieval as explained in the pertinent section concerning pin assignment, first change the pfr setting to enable the port f unction. since the pin then functions as a port, also set the ddr and pdr values in advance if necessary. when doing this, note that the i/o direction of the pin is once set as specified by the ddr. for a pin with the ad converter function, set the applicable bit in the analog input enable register (ader) of the ad converter to "port i/o mode". for information on the setting method, see "chapter : a/d converter". pdr epfr pfr dd r pddr epfr 1 0 1 0 see "4.1 port data registers 0 to 13, a-h : pdr0-13, a-h (port data register0 to 13, a-h) " for the details of pdr read values. peripheral output value external bus output value peripheral i/o direction control to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin external bus i/o direction control pin mb91590 series mn705-00009-3v0-e 448
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 59 5.1.1. peripheral i/o (bidirectional) p in a ssignment the p eripheral i/o (bidirectional) pin assignment is shown below. ? preparation ? since the pin once functions as a port as the result of step (1), also set the ddr and pdr values in advance if necessary . ? for a pin with the ad converter function, set the applicable bit in the analog input enable register (ade r) of the ad converter to "port i/o mode". for information on the setting method, see " chapter : a/d converter" . 1. set the pfr for the applicable pin to enable the port function. 2. disable the epfrs for all other peripherals to be used by the relevant pin. 3. if the relevant pin is also used for an external bus or the relevant peripheral is one of the targets of i/o multiplexing, set the epfr of the relevant peripheral. in addition, if the relevant peripheral has the i/o relocation function, set the epfr of the re levant peripheral. 4. set the pfr for the peripheral . figure 5-2 peripheral i/o assignment procedure pdr epfr pfr dd r pddr epfr 1 0 1 0 peripheral output value external bus output value peripheral i/o direction control external bus i/o direction control pin to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin mb91590 series mn705-00009-3v0-e 449
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 60 5.1.2. peripheral i nput a ssignment the p eripheral input assignment is shown below ? preparat ion ? since the pin will once function as a port as the result of step (1), set the ddr and pdr values in advance if necessary . ? for a pin with the ad converter function, set the applicable bit in the analog input enable register (ader) of the ad converter t o "port i/o mode". for information on the setting method, see " chapter : a/d converter" . 1. set the pfr of the applicable pin to enable the port function . 2. disable the epfrs for all other peripherals to be used by the relevant pin. 3. a n addition, if the relevant peripheral has the i/o relocation function, set the epfr of the relevant peripheral. 4. set the ddr for input. figure 5-3 peripheral input assignment procedure note: as shown in the figure above, if the pin is set for peripheral output etc., its output value is supplied to other peripheral inputs sharing the same pin. example: since int10 and ppg2_2 are assigned to the same pin (pin number 102- p111), external interrupt 10 can be generated at the ppg2 output by setting the pin for ppg2_2 peripheral output. pdr epfr pfr dd r pddr epfr 1 0 1 0 peripheral output value external bus output value peripheral i/o direction control external bus i/o direction control pin to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin mb91590 series mn705-00009-3v0-e 450
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 61 5.1.3. peripheral o utput a ssignment the p eripheral output assignment is shown below. the setting method is the same as that described in " 5.1.1. peripheral i/o (bidirectional) p in a ssignment ". ? preparation ? since the pin will once function as a port as the result of step (1), set the ddr and pdr values in advance if necessary. ? for a pin with the ad converter function, set the applicable bit in the analog input enable register (ader) of the ad c onverter to "port i/o mode". for information on the setting method, see " chapter : a /d converter". 1. set the pfr of the applicable pin to enable the port function. 2. disable the epfrs for all other peripherals to be used by the relevant pin. 3. if the relevant p in is also used for an external bus or the relevant peripheral is one of the targets of i/o multiplexing, set the epfr of the relevant peripheral. in addition, if the relevant peripheral has the i/o relocation function, set the epfr of the relevant periphe ral. 4. set the pfr for the peripheral . figure 5-4 peripheral output assignment procedure pdr epfr pfr dd r pddr epfr 1 0 1 0 peripheral output value external bus output value peripheral i/o direction control external bus i/o direction control pin to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin mb91590 series mn705-00009-3v0-e 451
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 62 5.1.4. external b us assignment the e xternal bus assignment is shown below. ? preparation ? since the pin will once function as a port as the result of step (1), set the ddr and pdr values in advance if necessary. ? for a pin with the ad converter function, set the applicable bit in the analog input enable register (ader) of the ad converter to "port i/o mode". for information on the setting method, see " chapter : a/d converter ". 1. set the pfr fo r the applicable pin to enable the port function. 2. disable the epfrs for all other peripherals that use the same pin as the external bus. 3. epfr55 is set to become " gdc external bus output enabled ". 4. set the pfr for the peripheral. figure 5-5 external bus assignment procedure pdr epfr pfr dd r pddr epfr 1 0 1 0 peripheral output value external bus output value peripheral i/o direction control external bus i/o direction control pin to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin mb91590 series mn705-00009-3v0-e 452
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 63 5.1.5. port function (input) assignment the p ort f unction ( i nput) a ssignment is shown below. ? preparation ? for a pin with the ad converter function, set the applicable bit in the analog input enable register (ader) of the ad converter to "port i/o mode". for information on the setting method, see " chapter : a/d converter". 1. set the pfr to enable the port function. 2. set the ddr for input. figure 5-6 port function (input) assignment procedure pdr epfr pfr dd r pddr epfr 1 0 1 0 peripheral output value external bus output value peripheral i/o direction control external bus i/o direction control pin to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin mb91590 series mn705-00009-3v0-e 453
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 64 5.1.6. port function ( out put) assignment the p ort f unction ( out put) a ssignment is shown below. ? preparation ? for a pin with the ad converter function, set the applica ble bit in the analog input enable register (ader) of the ad converter to "port i/o mode". for information on the setting method, see " chapter : a/d converter". 1. set the pfr to enable the port function. 2. set the ddr for output . figure 5-7 port function ( out put) assignment procedure pdr epfr pfr dd r pddr epfr 1 0 1 0 peripheral output value external bus output value peripheral i/o direction control external bus i/o direction control pin to peripheral input value to peripheral input value to input i/o relocation selection circuit input i/o relocation selection circuit to external bus input value input value of each pin mb91590 series mn705-00009-3v0-e 454
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 65 5.1.7. ad converter input assignment the ad c onverter i nput a ssignment is shown below. 1. set the analog input enable register (ader) of the ad converter to analog input mode. see " chapter : a/d converter". since the ad converter assignment is given the highest priority, no other configuration is required. mb91590 series mn705-00009-3v0-e 455
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 66 5.2. epfr setting priority the epfr s etting p riority is shown below. if the pfr is set for the peripheral and multiple epfr settings are overlapping for a single pin, the valid peripheral is determined based on the following priorities: 1. can 2. multi - function serial interface 3. lin - uart 4. ppg 5. sound generator 6. real time clock 7. base timer 8. r eload timer 9. output compare mb91590 series mn705-00009-3v0-e 456
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 67 5.3. notes on input i/o relocation setting notes on i nput i/o r elocation s etting are shown below. when switching an input pin to another pin, if there is a difference between pin levels before and after the switch, the i/o relocation change may become a trigger input to the perip heral that uses the relevant pin as a trigger. mb91590 series mn705-00009-3v0-e 457
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 68 5.4. input interception by gporten the input interception of the products equipped with gporten is shown below. the majority of pins become the input interceptions to avoid the change of the penetration current be fore the port is set with software at power - on reset. see " appendix - d: pin status in cpu status" for the pin that becomes an input interception. see " 4.14 . port input enable register : porte n( port enabl e register ) "for the method of releasing the input interception. mb91590 series mn705-00009-3v0-e 458
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 69 5.5. notes on pins with the ad converter function notes on pins with the ad converter function are shown below. when using a pin with the ad converter function to perform a different function, se t the relevant bit of the ad converter analog input enable register (ader) to "port i/o mode" in advance. for information on the setting method, see "chapter : a/d converter". if analog input is enabled, inputs from ports and from peripheral functions are fixed at "0" and outputs are fixed at hi - z regardless of the port function register (pfr0 0 to p fr 13, pfra to pfrh ) and extended port function register (epfr 00 to e pfr55 ) settings. mb91590 series mn705-00009-3v0-e 459
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 70 5.6. setting when using the base timer tioa1 pin setting when u sing the b ase t imer tioa1 pin is shown below. if the base timer tioa1 pin is to be used, it must be set for in put for base timer i/o mode 1 and set for output for all cases other than base timer i/o mode 1. if the base timer tioa1 pin is to be used, it must be set for periph eral in put for base timer i/o mode 1 (see " 5.1.2 peripheral i nput a ssignment ") and set for peripheral out put for all cases other than base timer i/o mode 1 (see " 5.1.3 peripheral o utput a ssignment "). mb91590 series mn705-00009-3v0-e 460
chapter 1 1: i/o ports 5 . ope ration fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 71 5.7. operation at wake u p from p ower s hutdown the operation at wake up from the power shutdown is shown below . w hen pmuctlr:ioctmd bit is set , i/o output level is kept during wake up sequence from the power shutdown. the maintenance of i/o output level continues until pmuctlr : ioct is set. w hen pmuctlr:ioctmd bit is cleared m aintenance is released after wake up is completed, and the register of the i/o port becomes effective though i/o is maintained at wake up from the power shutdown. on waking up from power shutdown, it has possibilities that the maintenance of i/o is not released. on waking up from power shutdown, pmuctlr.ioct bit must be written "1" for releasing the maintenance of i/o mb91590 series mn705-00009-3v0-e 461
chapter 1 1: i/o ports 5 . operation fujitsu semiconductor limited chapter: i/o ports fujitsu semiconductor confidential 72 5.8. notes on switching th e port function notes on switching the port function is shown below. w hen the port function is chang ed (general purpose port to peripheral function or peripheral function to general purpose port), it has possibilities that port outputs short spike. short spike is the same logic level as pdr value. it is happen e d in the case of switching with direction cha n ge. if this output is critical for the system, please set the certain value on pdr in prior to change port function . mb91590 series mn705-00009-3v0-e 462
chapter 12: interrupt control (interrupt controller) 1 . overview fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 1 chapter: interrupt control (interrupt controller) this chapter explains the interrupt control (interrupt controller). 1. overview 2. features 3. configuration 4. registers 5. operation code : 12_mb91590_hm_e_intcnt_00 3 _201111 27 mb91590 series mn705-00009-3v0-e 463
chapter 12: interrupt control (interrupt controller) 1 . overview fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 2 1. overview this section explains overview the of the interru pt control (interrupt controller). the interrupt controller performs arbitration of interrupt requests. mb91590 series mn705-00009-3v0-e 464
chapter 12: interrupt control (interrupt controller) 2 . features fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 3 2. features this section explains features of the interrupt control (interrupt controller). this module is composed of the following parts. ? icr register ? in terrupt priority determination circuit ? interrupt level and interrupt vector generation circuit this module has the following functions. ? detecting nmi requests and peripheral interrupt requests ? priority determination (by level and interrupt vector) ? transmi tting the interrupt level of the source with the highest priority to the cpu ? transmitting the interrupt vector number of the source with the highest priority to the cpu ? generating wakeup requests by nmi / interrupts that occur with a level other than " 1111 1" mb91590 series mn705-00009-3v0-e 465
chapter 12: interrupt control (interrupt controller) 3 . configuration fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the interrupt control (interrupt controller). figure 3-1 block diagram icr47 icr00 icr01 5 5 5 5 5 5 48 p e r iphe r al inter r upt v ector n umber inter r upt l e v el w a k eup gene r ation circuit bus access inter r upt l e v el and inter r upt v ec tor dete r mination and inter r upt * * nmi or (xbs ram double bit error generation) or (backup ram double bit error generation ) mb91590 series mn705-00009-3v0-e 466
chapter 12: interrupt control (interrupt controller) 4 . registers fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 5 4. registers this sec tion explains the registers of the interrupt control (interrupt controller). table 4-1 register s map address register s register function +0 +1 +2 +3 0x0440 icr00 icr01 icr02 icr03 interrupt control registers 00 to 47 0x0444 icr04 icr05 icr06 i cr07 0x0448 icr08 icr09 icr10 icr11 0x044c icr12 icr13 icr14 icr15 0x0450 icr16 icr17 icr18 icr19 0x0454 icr20 icr21 icr22 icr23 0x0458 icr24 icr25 icr26 icr27 0x045c icr28 icr29 icr30 icr31 0x0460 icr32 icr33 icr34 icr35 0x0464 icr36 icr37 icr38 icr39 0x0468 icr40 icr41 icr42 icr43 0x046c icr44 icr45 icr46 icr47 mb91590 series mn705-00009-3v0-e 467
chapter 12: interrupt control (interrupt controller) 4 . registers fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 6 4.1. interrupt control register s 00 to 47 : icr00 to icr47 (interrupt control register 00 to 47): this section explains the bit configuration of t he interrupt control registers 0 0 to 47 ( icr00 to icr47 ). one register is provided for each interrupt input to set the level for the corresponding interrupt request. ? icr00 to icr 47 : address 0440 h to 046f h ( access: byte , half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reser ved il[4:0] initial value 1 1 1 1 1 1 1 1 attribute r1,wx r1,wx r1,wx r1 , wx r/w r/w r/w r/w [b it4 to bit 0] il[4:0] (interrupt level control) the interrupt level setting bits specify the interrupt level for the corresponding interrupt request. an interr upt request is masked in the cpu if the interrupt level set in these registers is greater than or equal to the level mask value in the ilm register of the cpu. these bits are initialized to "5?b 11111 " on reset. the correspondence between the configurable i nterrupt level settings bits and the interrupt levels is shown below. il[4:0] interrupt level 10000 16 configurable highest level 10001 17 (high) 10010 18 | 10011 19 | 10100 20 | 10101 21 | 10110 22 | 10111 23 | 11000 24 | 11001 25 | 11010 26 | 11011 27 | 11100 28 | 11101 29 | 11110 30 (low) 11111 31 interrupts disabled il4 is fixed at " 1 " . writing has no effect . mb91590 series mn705-00009-3v0-e 468
chapter 12: interrupt control (interrupt controller) 5 . operation fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 7 5. operation this section explains the operation of the interrupt control (interrupt controller) . ? setup 1. configure the icr register of the interrupt vector number corresponding to the peripheral for which you want to generate the interrupt. 2. configure the peripheral where you want to generate the interrupt. (configure interrupt output as enabled on the peripheral.) ? starting start the configured peripheral. ? determining priorities this module selects the highest priority interrupt among interrupt factors th at occur simultaneously and outputs the interrupt level and interrupt vector number for the interrupt factors to the cpu. the criteria for determining the priority of interrupt factors are as follows. 1. nmi 2. factors that meet the following conditions ? if the v alue of the interrupt level is not 31 ( 5? b11111 ). (31 indicates interrupts disabled) ? the factors where the value of the interrupt level is the smallest. ? when the interrupt level is the same (except for 31), the factors that has the smallest interrupt vecto r number from amongst these. if no interrupt factors is selected by the above criteria, 31 ( 5? b11111 ) is output as the interrupt level. the interrupt vector number at this time is undefined. ? recovering from stop mode the function for using an interrupt r equest to recover from stop mode is performed by this module. if an interrupt request (the interrupt level is anything other than "5? b11111 " ) is generated from a peripheral (including nmi), a request is generated to the clock control unit to recover from s top mode. as the interrupt priority judgment unit restarts operation once the clock supply starts after recovery from stop mode, the cpu is able to execute instructions until the interrupt priority judgment unit produces a result. for interrupts that are n ot used as sources for recovering from stop mode, set the interrupt level of the corresponding interrupt control registers (icr00 to icr 47) to "5? b11111 " (interrupts disabled). ? recovering from st andby mode (p ower shutdown) when the interrupt level is highe r than icr=0x1f (interrupt disable) and the standby return factor is more effective in the state that the interrupt factor has been generated, the thing that changes to the state of the power supply interception cannot be done. the instruction execution is continued as it is. it returns immediately through the power supply interception return sequence though it changes to the state of the power supply interception because the interruption level does no t become a standby return factor in the state that icr=0x1f (interrupt disable) and the interrupt factor have been generated once because it is a state with the factor of the power supply interception return. (it is executed from the reset vector. ) mb91590 series mn705-00009-3v0-e 469
chapter 12: interrupt control (interrupt controller) 5 . operation fujitsu semiconductor limited chapter: interrupt control (interrupt controller) fujitsu semiconductor confidential 8 mb91590 series mn705-00009-3v0-e 470
chapter 13: external interrupt input 1 . overview fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 1 chapter : external interrupt input this chapter explains the external interrupt input. 1. overview 2. features 3. configuratio n 4. registers 5. operation 6. setting 7. q&a 8. notes code : 13_mb91590_hm_e_extint_00 4 _201111 27 mb91590 series mn705-00009-3v0-e 471
chapter 13: external interrupt input 1 . overview fujitsu semiconductor limited chapter : ext ernal interrupt input fujitsu semiconductor confidential 2 1. overview this section explains the overview of the external interrupt input. interrupt request input from external interrupt input pins (int0 to int 15) . mb91590 series mn705-00009-3v0-e 472
chapter 13: external interrupt input 2 . features fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 3 2. features this section explains features of the external interrupt input. ? 16 systems external interrupt input pins (int0 to int 15) ? interrupt detection factors: 4 types: ("l" level, "h" level, rising edge, falling edge) mb91590 series mn705-00009-3v0-e 473
chapter 13: external interrupt input 3 . configuration fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the external interrupt input. figure 3-1 block diagram intx external pin de tection circuit set eirr clear enir elvr bus access interrupt cleared by writin g zero to io port controller (when external interrupts are enabled, the intx pins prevent automatic port blocking in standby mode.) mb91590 series mn705-00009-3v0-e 474
chapter 13: external interrupt input 4 . re gisters fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 5 4. registers this section explains registers of the external interrupt input. table 4-1 register s map address register s register function +0 +1 +2 +3 0x0 550 eirr0 enir0 e lv r 0 external interrupt factor register 0 external interrupt enable register 0 external interrupt request level register 0 0x0 554 eirr1 enir1 e lv r 1 external interrupt factor register 1 external interrupt enable register 1 externa l interrupt request level register 1 mb91590 series mn705-00009-3v0-e 475
chapter 13: external interrupt input 4 . registers fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 6 4.1. external interrupt factor register 0/1 : eirr0/eirr1 (external interrupt request register 0/1) th e bit configuration of external interrupt factor register 0/1 (eirr0/eirr1) is shown below . this register holds informat ion that an external interrupt factor has been generated. ? eirr0 : address 0550 h (access: byte, half - word, word) ? eirr1 : address 0554 h (access: byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 er7 er6 er5 er4 er3 er2 er1 er0 initial value x x x x x x x x attribute r(rm1),w r(rm1),w r(rm1),w r(rm1),w r(rm1),w r(rm1),w r(rm1),w r(rm1),w [ bit7 to bit 0] er7 to er 0 (external interrupt request7 to 0) : external interrupt request bits f lag s to indicate that there is an interrupt request by in t external pin input. writing "0" will clear it. er n meaning read write 0 no external interrupt request clear 1 external interrupt request exists does not influence operation ? eirr0:er0 corresponds to int0 pin, eirr0:er1 to int1 pin, ..., eirr0:er7 to int7 pin, eirr1:er0 to int8 pin, ..., eirr1:er7 to int15 pin. ? writing "1" to these bits doesn't influence operation . ? the values read with read - modify - writ e (r m w) instr uctions will always be "1". ? when external interrupt detection condition is at "l" level o r "h" level, the corresponding bit will be set again if the external interrupt pin input is at an active level after clearing each bit in the eirr register. ? the factor bit in the interrupt factor register may be set by changing interrupt request level reg ister. initialize the interrupt factor register after changing the interrupt request le vel register. ? the value after resetting this register depends on the pin state after the reset. ? this register will be initialized by all reset factors except recovery fr om standby (power shutdown) when pmuctlr:ioctmd=1. mb91590 series mn705-00009-3v0-e 476
chapter 13: external interrupt input 4 . registers fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 7 4.2. external interrupt enable register 0/1 : enir0/enir1 (enable interrupt request register 0/1) th e bit configuration of external int errupt enable re gister 0/1 (enir0/eni r 1) is shown below . this reg ister enables external interrupt inputs. ? enir0 : address 0551 h ( access : byte, half - word, word) ? enir1 : address 0555 h ( access : byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 en7 en6 en5 en4 en3 en2 en1 en0 initial value 0 0 0 0 0 0 0 0 attribu te r/w r/w r/w r/w r/w r/w r/w r/w [ bit7 to bit 0] en7 to en 0 (interrupt enable) : external interrupt enable bits these bits perform mask controls of interr upt requests from external pin int inputs. en n operations at the detection of an external pin 0 in terrupt request mask. holds i nterrupt requests but does not output them. (initial value) 1 interrupt request enabled. enables interrupt requests. ? enir0:en0 corresponds to int0 pin, enir0:en1 to int1 pin, ..., enir0:en7 to int7 pin, enir1:en0 to int8 pin, ..., enir1:en7 to int15 pin. ? this register will be initialized by all reset factors except recovery from standby (power shutdown) when pmuctlr:ioctmd=1. mb91590 series mn705-00009-3v0-e 477
chapter 13: external interrupt input 4 . registers fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 8 4.3. external interrupt request level register 0/1 : elvr0/ elvr 1 (external interrupt level register 0/1) th e bit configuration of external interrupt request level register 0/1 (elvr0/elvr1) is shown below . this register selects detection conditions for external interrupt requests. ? elvr0 : address 0552 h ( access : byte, half - word, word) ? e lvr1 : address 0556 h ( acc ess : byte, half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 lb7 la7 lb6 la6 lb5 la5 lb4 la4 initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lb3 la3 lb2 la2 lb1 la1 lb 0 la0 initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w [ bit15 to bit 1] lb7 to lb 0 (level select b) : level select b [ bit14 to bit 0] la7 to la 0 (level select a) : level select a these bits select detection conditions for external interrupt requests. combination of 2 bits, la bit and lb bit will be used. lb n la n detection conditions 0 0 " l " level detection(initial value) 0 1 " h " level detection 1 0 rising edge detection 1 1 falling edge detection when the request input is a level (lan, lbn =00 or 01), the corresponding bit (ern) will turn back to "1" if intn pin input is still in the effective levels after setting the external interrupt request bit (ern) to "0". ? elvr0:la/lb0 corresponds to int0 pin, elvr0:la/lb1 to int1 pin, .. ., elvr0:la/lb7 to int7 pin, elvr1:la/lb0 to int8 pin, ..., elvr1:la/lb7 to int15 pin. ? the factor bit in the interrupt factor register may be set by changing the interrupt request level register. initialize the interrupt factor register after changing the interrupt request level register. ? this register will be initialized by all reset factors except recovery from standby (power shutdown) when pmuctlr:ioctmd=1. mb91590 series mn705-00009-3v0-e 478
chapter 13: external interrupt input 5 . operation fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 9 5. operation this section explains the operation of the external interrupt input. figure 5-1 operation diagram (1) extern al interrupt signal (int) input (2) detects interrupt signals (level/edge). (3) generates interrupt requests. (4) clears interrupt requests with the software. figu re 5-2 operation of external interrupt 1. operation of external interrupt this module generates the interrupt request signal to the interrupt controller when a request set in the e lv r reg ister is input in the corresponding pin after setting a request level and the enable register. the corresponding interrupt will be generated when the interrupt from this resource was found to have the highest priority in the result for examining the priority in interrupts concurrently occurred in the interrupt controller. 2. transition to standby mode channels not to be used should be moved to disable state before letting them go into the standby mode. for the enabled channel, the standby mode automatic input/ out pu t disabled feature to the external pin will also be suppressed. see " chapter : power consumption control" for the automatic input/output disabled feature. 3. setting procedure of external interrupts when setting registers which reside in the external interrupt unit, follow the steps below. int ("h") (1) (2) (2) (2) (2) (3) (4) (1) (1) (1) ("l") int ( r ising) edge/l ev el detection inter r upt request (er) (f alling) clears with the soft w are external interrupt i nterrupt controller cpu factor e lvr e irr e nir icryy icrxx il ilm resource request cmp cmp mb91590 series mn705-00009-3v0-e 479
chapter 13: external interrupt input 5 . operation fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 10 (1) disable the corresponding bit for the enable register. (2) set the corresponding bit for the request level setting register. (3) read the request level register. (4) clear the corresponding bit for the factor register. (5) enable the corresponding bit for the enable register. (note that concurrent writes of 16 - bit data are allowed in step (4) and (5) .) the enable register must be disabled before you can set the registers in this module. the factor register must be cleared before you can set the enable register to enable state. this has to be done to avoid generating erroneous interrupt factors at the time of setting register or in interrupt enable state. 4. external interrupt factor requests to the interrupt controller will continue to be active although a request input from outside is canceled, because there is an internal factor retention circuit. to cancel requests going toward the interrupt controller, the factor register should be cleared. figure 5-3 clearing the factor retention circuit and interrupt factor and interrupt request to interrupt controller in interrupt enable state clear ing the factor retention circuit inter r upt f actors and inter r upt requests to the inter r upt controller when inter r upts pe r mitted inter r upt input inter r upt input h l ev el lev el/edge detection f actor f/f (f actor retention circuit) inter r upt controller ena b le gate f actors conti n ue to be maintained unless cleared made inacti ve b y clea r ing the f actor f/f inter r upt request to inter r upt controller mb91590 series mn705-00009-3v0-e 480
chapter 13: external interrupt input 6 . setting fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 11 6. setting this section explains setting of the external interrupt input. table 6-1 necessary settings for using external interrupts settings setting register setting method detection level settings external interrupt request level setting register (elvr0 , e lv r 1 ) see " ab out detection levels and their setting procedures " in " 7 . q&a " . make external pins to use for input. see " chapter : i/o ports". see " chapter : i/o ports". external interrupt an input from the externa l pin input signal to pins int0 to int15 D mb91590 series mn705-00009-3v0-e 481
chapter 13: external interrupt input 7 . q&a fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 12 7. q&a this section explains q&a of the external interrupt input. ? about detection levels and their setting procedures four levels: ("l" level, "h" level, rising edge, falling edge) set the detection level bits as follow s : ( e lv ry: lb n , la n ) (n =0 to 7, y=0 , 1). operation modes detection level bits (lbn, lan) n=0 to 7 to perform "l" level detection set "00". to perform "h" level detection set "01" . to perform rising edge detection set "10" . to perform falling edge detec tion set "11" . ? how to make external pins to use for input see " chapter : i/o ports". ? about interrupt related registers see " chapter : interrupt control (interrupt controller) ". ? about interrupt types interrupt factors are only for external interrupts. there are no select bits. ? how to enable/disable/clear interrupts interrupt request enab le flag, interrupt request flag interrupt enable setting is done by the interrupt enable bit (enir0/ enir 1: en0 to en 7) . operation interrupt enable bit (en n ) to disable interrupt requests set "0" . to enable interrupt requests set "1" . interrupt request clear is done by the interrupt request bit (eirr0/ eirr 1: er0 to er7). operation interrupt request bit (er n ) to clear i nterrupt requests write "0" . mb91590 series mn705-00009-3v0-e 482
chapter 13: external interrupt input 8 . notes fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 13 8. notes this section explains the notes of the external interrupt input. the external interrupt input register is not initialized when returned from the standby clock mode (power shutdown) and the standby stop mode (power shut down) when pmuctlr:ioctmd=1 . to maintain the status before it returns and the status under return, set the device in the status of the i / o maintenance by setting pmuctlr : ioctmd before setting standby. and, release the i / o maintenance by setting pmuctlr : ioc t after the i / o port is set. see "chapter : power consumption control" for the details of the pmuctlr register. moreover, the internal reset is issued at the return from the standby watch mode (power shutdown) and the standby stop mode (power shutdown) when pmuctlr:ioctmd=1 . therefore, only the reset factors (power - on reset, internal low - voltage detection, and simultaneous assert of rstx and nmix) are accepted. at this time, the register of the external interrupt input is not initialized. if the reset input from rstx pin input or the external low voltage detection flag is set after the start - up, initialize the external interrupt input register before using. mb91590 series mn705-00009-3v0-e 483
chapter 13: external interrupt input 8 . notes fujitsu semiconductor limited chapter : external interrupt input fujitsu semiconductor confidential 14 mb91590 series mn705-00009-3v0-e 484
chapter 14: nmi input 1 . overview fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 1 chapter : nmi input t his chapter explains the nmi input. 1. overview 2. features 3. configuration 4. register 5. operation 6. usage example code : 14_mb91590_hm_e_nmi_00 5 _201111 27 mb91590 series mn705-00009-3v0-e 485
chapter 14: nmi input 1 . overview fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 2 1. overview t his section explains the overview of the nmi input. nmi (non m askable interrupt) is the non - maskable interrupt signal that is entered from the nmix pin. the nmi can be used as a source for recovering from stop mode. mb91590 series mn705-00009-3v0-e 486
chapter 14: nmi input 2 . features fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 3 2. features t his section explains features of the nmi input can be used in both stop mode (p ower shut - dow n is included) and watch mode (p ower shut - down is included) . mb91590 series mn705-00009-3v0-e 487
chapter 14: nmi input 3 . configuration fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 4 3. configuration t his section explains the configuration of the nmi input. figure 3-1 block diagram nmix e xternal pin falling edge det e ction set nmi flag clear nmi interrupt r equest nmi a cceptance or r eset watch / stop mode mb91590 series mn705-00009-3v0-e 488
chapter 14: nmi input 4 . register fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 5 4. register t his section explains the register of the nmi input. this function has no register. mb91590 series mn705-00009-3v0-e 489
chapter 14: nmi input 5 . operation fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 6 5. operation t his section explains the operation of the nmi input. ? nmi interrupt level the nmi has the highest level among the user interrupts and cannot be masked. as an exception, the nmi is masked after reset until the ilm is set by the cpu. ? nmi external pin in stop mode, this pin detects the l level, and at other times it detects the falling edge. ? interrupt request output the nmi request detector has an nmi flag that is set for an nmi request and is cleared only if an interrupt for the nmi itself is accepted or reset occurs. the nmi flag cannot be read or written. read irpr15h register to judge whether the nmi is caused by the nmix external pin or the other factors. for details of this register, see " interrupt request batch read ". ? recovering from stop mode when switching to stop mode, if an "l" level is input to the nmix, an nmi request is output to the interrupt controller and the cpu recovers from stop mode. if the cpu switches to sto p mode without returning the input level of the nmix pin to the "h" level after the nmi processing routine has finished in normal mode (not stop mode), the cpu recovers immediately after switching to stop mode ( see [2] in figure 5-1 ). similarly, the power shut - down will not be controlled when the status change s to the stop mode (power shut - down) without set ting the nmix pin to the "h" level. return the input level of the nmix pin to the "h" level before entering stop mode so that t he input level of the nmix pin is set to the "l" level in stop mode. figure 5-1 recovering from s top m ode * : the watch mode and the watch mode (power shut - down) are similarly control l ed. ope r ation status nmix input nmix input ope r ation status rec over y from stop at "l" l ev el after f alling edge nmi processing routine " l " l ev el detected and rec ov er from stop mode soon after ente r ing stop mode nmix input mb91590 series mn705-00009-3v0-e 490
chapter 14: nmi input 6 . usage example fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 7 6. usage example t his section explains a usage example of the nmi input. this section gives an example of using the nmi function. figure 6-1 usage e xample master chip rstx nmix uart , etc. mb9159 0 nmi usage example ? the recovery request from sleep or standby ? urgent communication request mb91590 series mn705-00009-3v0-e 491
chapter 14: nmi input 6 . us age example fujitsu semiconductor limited chapter : nmi input fujitsu semiconductor confidential 8 mb91590 series mn705-00009-3v0-e 492
chapter 15: delay interrupt 1 . overview fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 1 chapter : delay interrupt this chapter explains the delay interrupt. 1. overview 2. features 3. configuration 4. registers 5. operation 6. restrictions code : 15_mb91590_hm_e_delayint_00 4 _201111 27 mb91590 series mn705-00009-3v0-e 493
chapter 15: delay interrupt 1 . overview fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 2 1. overview this section explains the overview of the del ay interrupt. the delay interrupt is a function for generating interrupts for the os (operating system) to switch between tasks. this function allows interrupt requests to the cpu to be generated and cancelled by software. mb91590 series mn705-00009-3v0-e 494
chapter 15: delay interrupt 2 . features fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 3 2. features this section explains fe atures of the delay interrupt. the delay interrupt can be generated by writing to a register. mb91590 series mn705-00009-3v0-e 495
chapter 15: delay interrupt 3 . configuration fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the delay interrupt. figure 3-1 block diagram bus access delay interrupt interrupt request mb91590 series mn705-00009-3v0-e 496
chapter 15: delay interrupt 4 . registers fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 5 4. registers this section explains registers of the delay interrupt. address register s register function +0 +1 +2 +3 0x0044 dicr reserved reserved reserved delay interrupt control register ? delay interrupt control register : dicr (delay in terrupt control register) this register controls the delay interrupts. ? dicr : address 0044 h ( access : byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dlyi initial value 1 1 1 1 1 1 1 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w [ bit0 ] dlyi (delay interrupt enable) : delay interrupt enable bit this bit generates and clears the delay interrupt source. dlyi description write 0 clears the delay interrupt source write 1 generates the delay interrupt source mb91590 series mn705-00009-3v0-e 497
chapter 15: delay interrupt 5 . operation fujitsu semiconductor limited chapte r : delay interrupt fujitsu semiconductor confidential 6 5. operation this section e xplains the operation description of the delay interrupt. the d elay interrupts are used to generate interrupts for task switching. using this function allows interrupt requests to the cpu to be generated and cancelled by software. ? interrupt vector number the d elay interrupts are allocated to the interrupt sources with the highest interrupt vector number. in this core, delay interrupts are allocated to interrupt vector number 63 (0x3f). ? dlyi bit of the dicr register writing "1" to this bit generates a delay interrupt source. writing "0" to this bit cancels the delay interrupt source. this bit functions like a standard interrupt source flag and should be cleared in the interrupt routine at the same time as when switching a task. mb91590 series mn705-00009-3v0-e 498
chapter 15: delay interrupt 6 . restrictions fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 7 6. restrictions this section explains restrictions of the delay interrupt. do not use delay interrupts in dma transfer requests. mb91590 series mn705-00009-3v0-e 499
chapter 15: delay interrupt 6 . restrictions fujitsu semiconductor limited chapter : delay interrupt fujitsu semiconductor confidential 8 mb91590 series mn705-00009-3v0-e 500
chapter 16: interrupt request batch read 1 . overview fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 1 chapte r : interrupt re q uest batch read this chapter explains the overview, features, and configuration of the i nterrupt request batch read. 1. overview 2. features 3. configuration 4. registers 5. operation code : 16_mb91590_h m_e _irqread_00 5 _201111 27 mb91590 series mn705-00009-3v0-e 501
chapter 16: interrupt request batch read 1 . overview fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 2 1. overview this section explains the overview of the i nterrupt request batch read. this module can read multiple interrupt requests assigned to one interrupt vector number in a batch. interrupt requests that have been generated can be identified by using the bit sear ch instruction of the fr80 - family cpu. mb91590 series mn705-00009-3v0-e 502
chapter 16: interrupt request batch read 2 . features fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 3 2. features this section shows features of the i nterrupt request batch read. using this module, you can easily check whether interrupts have been generated . mb91590 series mn705-00009-3v0-e 503
chapter 16: interrupt request batch read 3 . configuration fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 4 3. configuration this section shows the configuration of the i nte rrupt request batch read. figure 3-1 block diagram : : : : from peripheral interrupt request interrupt controller interrupt request batch read bus access mb91590 series mn705-00009-3v0-e 504
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 5 4. registers this section explains the registers of the i nterrupt request batch read. table 4-1 registers map address registers register function +0 +1 +2 +3 0x0418 irpr0h irpr0l irpr1h irpr1l interrupt request batch read register 0 upper - order ( #18) interrupt request batch read register 0 lower - order ( #19) interrupt request batch read register 1 upper - order ( #20) interrupt request batch read regi ster 1 lower - order ( #22) 0x041c irpr2h irpr2l irpr3h irpr3l interrupt request batch read register 2 upper - order ( #38) interrupt request batch read register 2 lower - order ( #39) interrupt request batch read register 3 upper - order ( #40) interrupt request batch read register 3 lower - order ( #41) 0x0420 irpr4h irpr4l irpr5h irpr5l interrupt request batch read register 4 upper - order ( #42) interrupt request batch read register 4 lower - order ( #43) interrupt request batch read register 5 upper - order ( #44) interrupt request batch read register 5 lower - order ( #36) 0x0424 irpr6h irpr6l irpr7h irpr7l interrupt request batch read register 6 upper - order ( #45) interrupt request batch read register 6 lower - order ( #46) interrupt request batch read register 7 upper - order ( #47) interrupt request batch read register 7 lower - order ( #49) 0x0428 irpr8h irpr8l irpr9h irpr9l interrupt request batch read register 8 upper - order ( #50) interrupt request batch read register 8 lower - order ( #51) interrupt request batch read register 9 upper - order ( #52) interrupt request batch read register 9 lower - order ( #53) 0x042c reserved reserved reserved reserved mb91590 series mn705-00009-3v0-e 505
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 6 address registers register function +0 +1 +2 +3 0x0430 irpr 12 h irpr 12 l irpr 13 h irpr 13l interrupt request batch read register 12 upper - order ( #58) interrupt request batch read register 12 lower - order ( #59) interrupt request batch read register 13 upper - order ( #60) interrupt request batch read register 13 lower - order ( #61) 0x0434 irpr 14 h irpr 14 l irpr 15 h reserved interrupt request batch read register 14 upper - order ( #62) interrup t request batch read register 14 lower - order ( #62) interrupt request batch read register 15 upper - order ( #15) * irpr 10h/ l, irpr 11h/ l are unused . #nn : interrupt vector number (decimal) mb91590 series mn705-00009-3v0-e 506
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 7 4.1. interrupt request batch read register 0 upper - order : irpr0h (interrupt request peripheral read register 0h) the bit configuration of the i nterrupt r equest b atch r ead r egister 0 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 18 ) ? irpr0h : add ress 0418 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rtir0 rtir1 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] rtir0 ( reload timer interrupt request 0 ) : reload timer 0 interrupt request [b it6 ] rtir1 ( reload timer interrupt request 1 ) : reload timer 1 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 507
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 8 4.2. interrupt request batch read register 0 lower- order : irpr0l (interrupt request peripheral read register 0l) the bit configuration of the interrupt request batch read register 0 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. ( interrupt vector number # 19 ) ? irpr0l : address 0419 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rtir2 rtir3 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] rtir2 ( re load timer interrupt request 2 ) : reload timer 2 interrupt request [b it6 ] rtir3 ( reload timer interrupt request 3 ) : reload timer 3 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 508
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 9 4.3. interrupt request batch read r egister 1 upper - order : irpr1h (interrupt request peripheral read register 1h) the bit configuration of the interrupt request batch read register 1 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 20 ) ? irpr1h : address 041a h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxir0 isir0 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r0,wx r0,wx r 0,wx r0,wx r0,wx r0,wx [b it7 ] rxir0 ( multi - function - serial - interface rx interrupt request 0 ) : multi - function - serial - interface ch . 0 reception completion interrupt request [b it6 ] isir0 ( multi - function - serial - interface status interrupt request 0 ) : multi - function - serial - interface ch .0 status interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 509
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 10 4.4. interrupt request batch read register 1 lower- order : irpr1l (interrupt request pe ripheral read register 1l) the bit configuration of the interrupt request batch read register 1 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 22 ) ? irpr1l : address 041b h (a ccess : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rxir1 isir1 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] rxir1 ( multi - function - serial - interface rx interrupt request 1) : multi - function - serial - interface ch . 1 reception completion interrupt request [b it6 ] isir1 ( multi - function - serial - interface status interrupt request 1) : multi - function - serial - interface ch . 1 status interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 510
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 11 4.5. interrupt request batch read register 2 upper - order : irpr2h (interrupt request peripheral read register 2h) the bit configuration of the interrupt request batch read register 2 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 38 ) ? irpr2h : address 041c h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sgir 0 rx ir 7 reserve d initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] sg ir0 ( sg interrupt request 0 ) : sound generator 0 interrupt request [b it6 ] rx ir 7 ( rx interrupt request 7) : lin - uart7 reception completion interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 511
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 12 4.6. interrupt request batch read register 2 lower- order : irpr2l (interrupt request peripheral read register 2l ) the bit configuration of th e interrupt request batch read register 2 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 39 ) ? irpr2 l : address 041 d h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sgir1 tx ir 7 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r0,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] sg ir 1 ( sg interrupt request 1) : sound generator 1 interrupt request [b it6 ] tx ir 7 ( tx interrupt request 7) : lin - uart7 transmission completion interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 512
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 13 4.7. interrupt request batch read register 3 upper - order : irpr3h (interrupt request peripheral read register 3 h) the bit configuration of the interrupt request batch read register 3 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 40 ) ? irpr 3h : address 041 e h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppgir0 ppgir1 ppgir 10 ppgir1 1 ppgir 20 ppgir 21 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r,wx r,wx r0,wx r0,wx [b it7 ] ppgir0 ( ppg interrupt request 0 ) : ppg0 interr upt request [b it6 ] ppgir1 ( ppg interrupt request 1 ) : ppg1 interrupt request [b it 5] ppgir 1 0 ( ppg interrupt request 10) : ppg 10 interrupt request [b it 4] ppgir 1 1 ( ppg interrupt request 11) : ppg 11 interrupt request [b it 3] ppgir 2 0 ( ppg interrupt request 20) : ppg 20 interrupt request [b it 2] ppgir 2 1 ( ppg interrupt request 21) : ppg 21 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 513
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 14 4.8. interrupt request batch read register 3 lower- order : irpr3l (interrupt request peripheral read register 3l) the bit configuration of the interrupt request batch read register 3 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 41 ) ? irpr 3 l : address 041 f h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppgir 2 ppgir 3 ppgir 12 ppgir1 3 ppgir 22 ppgir 23 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r,wx r,wx r0,wx r0,wx [b i t7 ] ppgir2 ( ppg interrupt request 2 ) : ppg2 interrupt request [b it6 ] ppgir3 ( ppg interrupt request 3 ) : ppg3 interrupt request [b it 5] ppgir 1 2 ( ppg interrupt request 12) : ppg 12 interrupt request [b it 4] ppgir 1 3 ( ppg interrupt request 13) : ppg 13 interrupt r equest [b it 3] ppgir 2 2 ( ppg interrupt request 22) : ppg 22 interrupt request [b it 2] ppgir 2 3 ( ppg interrupt request 23) : ppg 23 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued . mb91590 series mn705-00009-3v0-e 514
chapter 16: interrupt request batch read 4 . regis ters fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 15 4.9. interrupt request batch read register 4 upper - order : irpr4h (interrupt request peripheral read register 4 h) the bit configuration of the interrupt request batch read register 4 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 42 ) ? irpr 4 h : address 0420 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppgir4 ppgir5 ppgir 14 ppgir1 5 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r, wx r,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] ppgir4 ( ppg interrupt request 4 ) : ppg4 interrupt request [b it6 ] ppgir5 ( ppg interrupt request 5 ) : ppg5 interrupt request [b it 5] ppgir 1 4 ( ppg interrupt request 14) : ppg 14 interrupt request [b it 4] ppgir 1 5 ( ppg inte rrupt request 15) : ppg 15 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 515
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 16 4.10. interrupt request batch read register 4 lower- order : irpr4 l (interrupt request peripheral read register 4l) the bit configuration of the interrupt request batch read register 4 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 43 ) ? irpr 4 l : address 0421 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppgir6 ppgir7 ppgir 16 ppgir 17 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] ppgir6 ( ppg interrupt request 6 ) : ppg6 interrupt request [b it6 ] ppgir7 ( ppg interrupt request 7 ) : ppg7 interrupt request [b it 5] ppgir 1 6 ( ppg interrupt request 16) : ppg 16 interrupt request [b it 4] ppgir 1 7 ( ppg interrupt request 17) : ppg 17 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 516
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 17 4.11. interrupt request batch read register 5 upper - order : irpr5h (interrupt request peripheral read register 5 h) the bit configuration of the interrupt request batch read register 5 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 44 ) ? irpr 5 h : address 042 2 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ppgir8 ppgir9 ppgir 18 ppgir 19 reserve d initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] ppgir8 ( ppg interrupt request 8 ) : ppg8 interrupt request [b it6 ] ppgir9 ( ppg interrupt request 9 ) : ppg9 interrupt request [b it 5] ppgir 1 8 ( ppg interrupt reques t 18) : ppg 18 interrupt request [b it 4] ppgir 1 9 ( ppg interrupt request 19) : ppg 19 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 517
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 18 4.12. interrupt request batch read register 5 lower- order : irpr5l (interrupt request peripheral read register 5l) the bit configuration of the interrupt request batch read register 5 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 36 ) ? irpr 5 l : address 042 3 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 canir2 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] canir2 ( can interrupt r equest 2) : can ch.2 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 518
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 19 4.13. interrupt request batch read register 6 upper - order : irpr6h (interrupt request peripheral read register 6 h) the bit configuration of the interrupt request batch read register 6 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 45) ? irpr 6 h : address 042 4 h ( access : byte , hal f- word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gdc gdc_alm reserved gdc_lvd reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,wx r,wx r0,wx r0,wx r0,wx [b it7 ] gdc ( gdc interrupt request ) : gdc interrupt request [b it6 ] gdc_a lm ( pll ovf interrupt request ) : pll overflow interrupt request [b it 3] gdc_lvd ( gdc low voltage detect interrupt request ) : gdc low voltage interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 519
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 20 4.14. interrupt request batch read register 6 lower- order : irpr6l (interrupt request peripheral read register 6l ) the bit configuration of the interrupt request batch read register 6 lower - order is explained . this register indicates the per ipheral that has issued the interrupt requ est. (interrupt vector number # 46 ) ? irpr 6l : address 042 5 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mtir stir ptir reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,w x r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] mtir ( main timer interrupt request ) : main t i mer interrupt request [b it6 ] stir ( sub timer interrupt request ) : sub t i mer i nterrupt request [b it5 ] ptir ( pll timer interrupt request ) : pll timer interrupt request rea d value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 520
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 21 4.15. interrupt request batch read register 7 upper - order : irpr7h (interrupt request peripheral read register 7 h) the bit configuration of the int errupt request batch read register 7 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 47 ) ? irpr 7 h : address 042 6 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved subir sgir4 reserved initial value 0 0 0 0 0 0 0 0 attribute r 0 ,wx r,wx r,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it6 ] subir ( sub interrupt request ) : clock c alibration (sub) interrupt request [b it 5] sgir4 ( sg interrupt request 4) : sound generator 4 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 521
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 22 4.16. interrupt request batch read register 7 lower- order : irpr7 l (interrupt request peripheral read registe r 7l) the bit configuration of the interrupt request batch read register 7 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 49 ) ? irpr 7 l : address 042 7 h ( access : byte , half -w ord , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved crir reserved initial value 0 0 0 0 0 0 0 0 attribute r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx r,wx r0,wx [b it1 ] crir ( cr clock calibration interrupt request ) : clock c alibration (cr) interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 522
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 23 4.17. interrupt request batch read register 8 upper - order irpr8h (interrupt request peripheral read register 8 h) the bit configuration of the interrupt request batch read register 8 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 50 ) ? irpr 8 h : address 042 8 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bi t 4 bit 3 bit 2 bit 1 bit 0 frtir0 frtir2 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] frtir0 ( frt interrupt request 0) : free - run timer ch.0 interrupt request [b it 6] frtir2 ( frt interrupt request 2) : free - run timer ch.2 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 523
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 24 4.18. interrupt request batch read register 8 lower- order : irpr8l (interrupt request peripheral read register 8l ) the bit configuration of the interrupt request batch read register 8 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 51 ) ? irpr 8l : address 042 9 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 frtir1 frtir3 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] frtir1 ( frt interrupt request 1) : free - run timer ch.1 interrupt request [b it 6] frtir3 ( frt interrupt request 3) : free - run timer ch.3 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 524
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 25 4.19. interrupt request batch read register 9 upper - order : irpr9h (interrupt request peripheral read register 9h) the bit configuration of the interrupt request batch read register 9 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 52 ) ? ir pr 9h : address 042 a h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icuir0 icuir6 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] icuir0 ( icu interrupt request 0) : inp ut capture ch.0 interrupt request [b it 6] icuir6 ( icu interrupt request 6) : in put capture ch.6 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 525
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 26 4.20. interrupt r equest batch re ad register 9 lower- order : irpr9l (interrupt request peripheral read register 9l) the bit configuration of the interrupt request batch read register 9 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est . (interrupt vector number # 53 ) ? irpr 9l : address 042 b h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icuir1 icuir7 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] icui r1 ( icu interrupt request 1) : in put capture ch.1 interrupt request [b it 6] icuir 7 ( icu interrupt request 7) : in put capture ch.7 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been is sued. mb91590 series mn705-00009-3v0-e 526
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 27 4.21. interrupt request batch read register 12 upper - order : irpr 12h (interrupt request peripheral read register 12 h) the bit configuration of the interrupt request batch read register 12 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 58 ) ? irpr 12h : address 04 30 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocuir0 ocuir1 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,w x r0,wx r0,wx r0,wx r0,wx [b it7 ] ocuir0 ( ocu interrupt request 0) : output compare ch.0 interrupt request [b it 6] ocuir1 ( ocu interrupt request 1) : output compare ch.1 interrupt request read value of each bit meaning 0 no interrupt request has been iss ued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 527
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 28 4.22. interrupt request batch read register 12 lower- order : irpr12l (interrupt request peripheral read register 12l ) the bit configuration of the interrupt request batch read register 12 lower - order is explaine d. this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 59 ) ? irpr 12l : address 04 31 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ocuir2 ocuir3 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r 0 ,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] ocuir2 ( ocu interrupt request 2) : output compare ch.2 interrupt request [b it 6] ocuir3 ( ocu interrupt request 3) : output compare ch.3 interrupt request read value of each bit mea ning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 528
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 29 4.23. interrupt request batch read register 13 upper - order : irpr 13h (interrupt request peripheral read register 13 h) the bit configuration of the interrupt request batch read register 13 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 60 ) ? irpr 13h : address 04 32 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bt0 ir0 bt0ir1 sgir2 reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r 0 ,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] bt0ir0 ( bt0 interrupt request 0) : base timer ch.0 interrupt request 0 [b it 6] bt0ir1 ( bt0 interrupt request 1) : base timer ch.0 inter rupt request 1 [b it 5] sgir2 ( sg interrupt request 2) : sound generator 2 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 529
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batc h read fujitsu semiconductor confidential 30 4.24. interrupt request batch read register 13 lower-o rder : irpr13l (interrupt request peripheral read register 13l ) the bit configuration of the interrupt request batch read register 13 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 61 ) ? irpr 13l : address 04 33 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bt1ir0 bt1ir1 sgir3 xb_ecc_se br_ecc_se reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r,wx r0,wx r0,wx r0,wx [b it7 ] bt1ir0 ( bt1 interrupt request 0) : base timer ch.1 interrupt request 0 [b it 6] bt1ir1 ( bt1 interrupt request 1) : base timer ch.1 interrupt request 1 [b it 5] sgir3 ( sg interrupt request 3) : sound generator 3 interrupt request [b it 4] xb_ecc_se : xbs ram s ingle bit error generation interrupt request [b it 3] br_ecc_se : backup ram single bit error generation i nterrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 530
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 31 4.25. interrupt request batch read register 14 upper - order : irpr 14h (interrupt request peripheral read register 14h ) the bit configuration of the interrupt request batch read register 14 upper - order is explained . this register indicates the peripheral that has issued the inte rrupt requ est. (interrupt vector number # 62 ) ? irpr 14h : address 04 34 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dmac0ir dmac1ir dmac2ir dmac3ir dmac4ir dmac5ir dmac6ir dmac7ir initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r,wx r,wx r,wx r,wx r,wx [b it7 ] dmac0ir ( dmac 0 interrupt request ) : dmac ch.0 interrupt request [b it6 ] dmac1ir ( dmac 1 interrupt request ) : dmac ch.1 interrupt request [b it5 ] dmac2ir ( dmac 2 interrupt request ) : dmac ch.2 interrupt request [b it4 ] dmac3ir ( dmac 3 interrupt request ) : dmac ch.3 interrupt request [b it3 ] dmac4ir ( dmac 4 interrupt request ) : dmac ch.4 interrupt request [b it2 ] dmac5ir ( dmac 5 interrupt request ) : dmac ch.5 interrupt request [b it1 ] dmac6ir ( dmac 6 interrupt request ) : dmac ch.6 interrupt request [b it0 ] dmac7ir ( dmac 7 interrupt request ) : dmac ch.7 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 531
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 32 4.26. interrupt request batch read register 14 lower- order : irpr14l (interrupt request peripheral read register 14l ) the bit configuration of the interrupt request batch read register 14 lower - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (int errupt vector number # 62 ) ? irpr 14l : address 04 35 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 dmac 8 ir dmac 9 ir dmac 10ir dmac 11 ir dmac 12ir dmac 13ir dmac 14ir dmac 15ir initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r, wx r,wx r,wx r,wx r,wx [b it7 ] dmac 8 ir ( dmac 8 interrupt request ) : dmac ch .8 interrupt request [b it6 ] dmac 9 ir ( dmac 9 interrupt request ) : dmac ch .9 interrupt request [b it5 ] dmac 10 ir ( dmac 10 interrupt request ) : dmac ch .10 interrupt request [b it4 ] dmac 11 ir ( dmac 11 interrupt request ) : dmac ch .11 interrupt request [b it3 ] dmac 12 ir ( dmac 12 interrupt request ) : dmac ch .12 interrupt request [b it2 ] dmac 13 ir ( dmac 13 interrupt request ) : dmac ch .13 interrupt request [b it1 ] dmac 14 ir ( dmac 14 interrupt request ) : dmac ch .14 interrupt request [b it0 ] dmac 15 ir ( dmac 15 interrupt request ) : dmac ch .15 interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. mb91590 series mn705-00009-3v0-e 532
chapter 16: interrupt request batch read 4 . registers fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 33 4.27. interrupt r equest batch read register 15 upper - order : irpr 15h (interrupt request peripheral read register 15h ) the bit configuration of the interrupt request batch read register 15 upper - order is explained . this register indicates the peripheral that has issued the interrupt requ est. (interrupt vector number # 15 ) ? irpr 15h : address 04 36 h ( access : byte , half - word , word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 extnmi xb_ecc_de br_ecc_de reserved initial value 0 0 0 0 0 0 0 0 attribute r,wx r,wx r,wx r0,wx r0,wx r0,wx r0,wx r0,wx [b it7 ] extnmi : external nmi request the extnmi bit is set by detecting external nmi request , and cleared by r eading this register. [b it6 ] xb_ecc_ d e : xbs ram double bit error generation interrupt request [b it5 ] br_ecc_ d e : b ackup ram double bit error generation interrupt request read value of each bit meaning 0 no interrupt request has been issued. 1 an interrupt request has been issued. set extnmi bit clear external nmi request detection irpr15h read or reset mb91590 series mn705-00009-3v0-e 533
chapter 16: interrupt request batch read 5 . operation fujitsu semiconductor limited chapter : interrupt request batch read fujitsu semiconductor confidential 34 5. operation this section explains the o peration of the i nterrupt request batch read. within each interrupt handler, the pertinent register is read to determine what bits are set . as a consequence, what interrupt requests ha ve been generated is found. note: this register does not provide a function that can be used to input external interrupts. read register s eirr0 and eirr1, which are used to input external interrupts. mb91590 series mn705-00009-3v0-e 534
chapter 17: ppg 1 . overview fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 1 chapter : ppg this chapter explains the ppg. 1. overview 2. features 3. configuration 4. registers 5. operation 6. setting 7. q&a 8. sample programs 9. notes code : 17_mb91590_hm_e_ppg_00 6 _2011112 7 mb91590 series mn705-00009-3v0-e 535
chapter 17: ppg 1 . overview fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 2 1. overview this section explains an overview of the ppg. the programmable pulse generator (ppg) is used to generate one - shot (rectangular wave) or pulse width modulation (pwm) outputs . the ppg can be used in a wi de range of applications because the cycle and duty of its output can be freely changed by software. cycle v alue reload borr ow count clo ck do wn counter pin output v alue match latch inv ersion buf f er duty v alue mb91590 series mn705-00009-3v0-e 536
chapter 17: ppg 2 . features fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 3 2. features this section explains features of the ppg. ? number of ppg: 24 (output: 24 channels, ppg0, ppg1, ppg2, ppg3, ppg4, ppg 5, ppg6, ppg7, ppg8, ppg9, ppg10 , ppg11, ppg12, ppg13, ppg14, ppg15, ppg16, ppg17, ppg18, ppg19, ppg20, ppg21, ppg22, ppg23 ) ? count clock: selects from 4 types (peripheral clock (pclk ) /1, /4, / 16, /64) ? cycle: cycle = count clock (pcsr register value + 1 ) (example) count clock = 16 mhz (62.5 ns), pcsr value = 63999 cycle = 62.5ns (63999+1) = 4ms ? duty: duty = count clock (pdut register value + 1) ? output waveform: 6 types shown in the figure below: figure 2-1 output waveforms ? interrupt factors: one of the follow ing four interrupts is selected ? software trigger ? borrow occurrence on the counter (match with the specified cycle) ? duty match ? borrow occurrence on the counter (match with the specified cycle) or duty match ? activation triggers ? software trigger (set with software trigger bit) ? internal trigger: trigger with register written trigger with reload timer ? external trigger ? one-shot wavefor m (rectangular wav e) ? pwm waveform ? fi x ed output no r mal pola r ity : "l" fi x ed output inver ted pola r ity : "h" fi x ed output no r mal pola r ity : inver ted pola r ity : no r mal pola r ity : inver ted pola r ity : mb91590 series mn705-00009-3v0-e 537
chapter 17: ppg 3 . configuration fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 4 3. configuration this section explains a configuration of the p p g. figure 3-1 configuration diagram (for each channel) pwm ope r ation one-shot clo ck buf f er control circuit reload duty match duty match borr ow compare tr igger tr igger borr ow selector selector ena b le only read do wn counter buf f er cycle v alue duty v alue division r atio prg0-specific function ena b le only w r ite ena b le only w r ite prescaler prescaler output lev el (latch) stop disa b le resta rt ena b le resta rt no inter r upt request wr ite 0 : flag clear inter r upt request disa b le inter r upt no r mal output inver ted output l fi x ed output h fi x ed output ena b le inter r upt no ef f ect on ope r ation no ef f ect on ope r ation soft w are t r igger rising edge f alling edge soft w are t r igger or t r igger input counter borr ow duty match counter borr o w or duty match both edges read : al wa ys '0' reload timer ch.0 reload timer ch.1 exte r nal t r igger (trg) ena b le ope r ation en0 bit of gcn2n gcn1n : bit3 - 0 en1 bit of gcn2n en2 bit of gcn2n gcn2n:bit0 gcn2n:bit1 gcn2n:bit2 gcn2n:bit3 en3 bit of gcn2n 16-bit reload timer ch.0 16-bit reload timer ch.1 exte r nal t r igger exte r nal t r igger exte r nal t r igger exte r nal t r igger disa b le setting ena b le/stop ope r ation count clo ck tr igger selection select inter r upt cause edge selection edge detection pcn : bit13 mdse pcn : bit11,10 pclk pclk / 4 pclk / 16 pclk / 64 pcn : bit15 pcn : bit5 pcn : bit4 pcn : bit9, 0 pgms osel cks1, 0 inter r upt exte r nal ppg pin setting ppg0 to ppg3 tsel03-00 en1 en0 en2 en3 egs1, 0 cnte r trg irqf stgr irs1,0 pcn : bit14 pcn : bit12 pcn : bit7, 6 pcn : bit3, 2 pdut ppgdiv pcsr ptmr iren div1, 0 ppgdi v :bit1, 0 1/1 1/2 1/4 1/8 0 1 0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 : 0 0 0 0 0 0 0 0 mb91590 series mn705-00009-3v0-e 538
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 5 4. registers this section explains registers of the ppg. ? table of base addresses (base_addr) and external pins table 4-1 table of base addresses and external pins channel base_addr external pin ppg output trigger input 0 0x026c ppg0 / ppg0_1 / ppg0_2 trg0 1 0x0274 ppg1 / ppg1_1 / ppg1_2 / ppg1_ 3 2 0x027c ppg2 / ppg2_1 / ppg2_2 3 0x0284 ppg3 / ppg3_ 1 / ppg3_2 4 0x028c ppg4 / ppg4_1 / ppg4_2 trg1 5 0x0294 ppg5 / ppg5_1 / ppg5_2 6 0x029c ppg6 / ppg6_1 / ppg6_2 7 0x02a4 ppg7 / ppg7_1 / ppg7_2 8 0x02ac ppg8 / ppg8_1 / ppg8_2 trg2 9 0x02b4 ppg9 / ppg9_1 / ppg9_2 10 0x02bc ppg10 / ppg10_1 / ppg10_2 11 0x0 150 ppg 11_1 1 2 0x0 158 ppg 12_1 trg3 13 0x0 160 ppg 13_1 14 0x0 168 ppg 14_1 15 0x0 170 ppg 15_1 16 0x0 178 ppg 16 trg4 17 0x0 180 ppg 17 18 0x0 188 ppg 18 19 0x0 190 ppg 19 20 0x0 198 ppg 20 trg5 21 0x0 1a0 ppg 21 22 0x0 1a8 ppg 22 23 0x0 1b0 ppg 23 mb91590 series mn705-00009-3v0-e 539
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 6 ? registers map table 4-2 registers map address register s register function +0 +1 +2 +3 0x0 144 gcn1 3 reserved gcn2 3 general control register 1 3 general control register 2 3 0x0 148 gcn1 4 reserved gcn2 4 general control register 1 4 gener al control register 2 4 0x0 14c gcn1 5 reserved gcn2 5 general control register 1 5 general control register 2 5 0x0 150 ptmr 11 pcsr 11 ppg timer register 11 ppg cycle setting register 11 0x0 154 pdut 11 pcn 11 ppg duty setting register 11 ppg control status regis ter 11 0x0 158 ptmr 12 pcsr 12 ppg timer register 12 ppg cycle setting register 12 0x0 15c pdut 12 pcn 12 ppg duty setting register 12 ppg control status register 12 0x0 160 ptmr 13 pcsr 13 ppg timer register 13 ppg cycle setting register 13 0x0 164 pdut 13 pcn 13 ppg duty setting register 13 ppg control status register 13 0x0 168 ptmr 14 pcsr 14 ppg timer register 14 ppg cycle setting register 14 0x0 16c pdut 14 pcn 14 ppg duty setting register 14 ppg control status register 14 0x0 170 ptmr 15 pcsr 15 ppg timer register 15 ppg cycle setting register 15 0x0 174 pdut 15 pcn 15 ppg duty setting register 15 ppg control status register 15 0x0 178 ptmr 16 pcsr 16 ppg timer register 16 ppg cycle setting register 16 0x0 17c pdut 16 pcn 16 ppg duty setting register 16 ppg control statu s register 16 0x0 180 ptmr 17 pcsr 17 ppg timer register 17 ppg cycle setting register 17 0x0 184 pdut 17 pcn 17 ppg duty setting register 17 ppg control status register 17 0x0 188 ptmr 18 pcsr 18 ppg timer register 18 ppg cycle setting register 18 mb91590 series mn705-00009-3v0-e 540
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 7 address register s register function +0 +1 +2 +3 0x0 18c pdut 18 pcn 18 ppg duty setting register 18 ppg control status register 18 0x0 190 ptmr 19 pcsr 19 ppg timer register 19 ppg cycle setting register 19 0x0 194 pdut 19 pcn 19 ppg duty setting register 19 ppg control status register 19 0x0 198 ptmr 20 pcsr 20 ppg timer r egister 20 ppg cycle setting register 20 0x0 19c pdut 20 pcn 20 ppg duty setting register 20 ppg control status register 20 0x0 1a0 ptmr 21 pcsr 21 ppg timer register 21 ppg cycle setting register 21 0x0 1a4 pdut 21 pcn 21 ppg duty setting register 21 ppg contro l status register 21 0x0 1a8 ptmr 22 pcsr 22 ppg timer register 22 ppg cycle setting register 22 0x0 1ac pdut 22 pcn 22 ppg duty setting register 22 ppg control status register 22 0x0 1b0 ptmr 23 pcsr 23 ppg timer register 23 ppg cycle setting register 23 0x0 1b 4 pdut 23 pcn 23 ppg duty setting register 23 ppg control status register 23 0x025c gcn10 reserved gcn20 general control register 10 general control register 20 0x0260 gcn11 reserved gcn21 general control register 11 general control register 21 0x0264 gcn 12 reserved gcn22 general control register 12 general control register 22 0x0268 reserved ppgdiv ppg0 output division setting register 0x026c ptmr0 pcsr0 ppg timer register 0 ppg cycle setting register 0 0x0270 pdut0 pcn0 ppg duty setting register 0 ppg control status register 0 0x0274 ptmr1 pcsr1 ppg timer register 1 ppg cycle setting register 1 0x0278 pdut1 pcn1 ppg duty setting register 1 ppg control status register 1 mb91590 series mn705-00009-3v0-e 541
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 8 address register s register function +0 +1 +2 +3 0x027c ptmr2 pcsr2 ppg timer register 2 ppg cycle setting register 2 0x0280 pdut 2 pcn2 ppg duty setting register 2 ppg control status register 2 0x0284 ptmr3 pcsr3 ppg timer register 3 ppg cycle setting register 3 0x0288 pdut3 pcn3 ppg duty setting register 3 ppg control status register 3 0x028c ptmr4 pcs r4 ppg timer register 4 ppg cycle setting register 4 0x0290 pdut4 pcn4 ppg duty setting register 4 ppg control status register 4 0x0294 ptmr5 pcsr5 ppg timer register 5 ppg cycle setting register 5 0x0298 pdut5 pcn5 ppg duty setting register 5 ppg control status register 5 0x029 c ptmr6 pcsr6 ppg timer register 6 ppg cycle setting register 6 0x02a0 pdut6 pcn6 ppg duty setting register 6 ppg control status register 6 0x02a4 ptmr7 pcsr7 ppg timer register 7 ppg cycle setting register 7 0x02a8 pdut7 pcn7 ppg duty setting register 7 ppg control status register 7 0x02ac ptmr8 pcsr8 ppg timer register 8 ppg cycle setting register 8 0x02b0 pdut8 pcn8 ppg duty setting register 8 ppg control status register 8 0x02b4 ptmr9 pcsr9 ppg timer register 9 ppg cycle setting register 9 0x02b8 pdut9 pcn9 ppg duty setting register 9 ppg control status register 9 0x02bc ptmr10 pcsr10 ppg timer register 10 ppg cycle setting register 10 0x02c0 pdut10 pcn10 ppg duty setting register 10 ppg control status register 10 mb91590 series mn705-00009-3v0-e 542
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 9 4.1. ppg cycle setting register : pcsr t he bit configuration of the ppg c ycle s etting r egister ( pcsr ) is shown below . the ppg cycle setting register (pcsr) specifies a cycle of the ppg. ? pcsr : address base_addr + 02 h ( access : half - word , word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 s15 s14 s13 s12 s11 s10 s9 s8 initial value x x x x x x x x attribute rx,w rx,w rx,w rx,w rx,w rx,w rx,w rx,w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 s7 s6 s5 s4 s3 s2 s1 s0 initial value x x x x x x x x attribute rx,w rx,w rx,w rx,w rx,w rx,w rx,w rx,w ? the ppg cycle setting register has a buffer. data transfer from the buffer to the counter occurs automatically when a borrow occurs on the counter. ? be sure to set the ppg duty setting register (pdut) after the ppg cycle setting register is rewritten. ? ppg cycle setting registers must be accessed in half - word (16 - bit) or word (32 - bit). ( see " 9. notes ".) mb91590 series mn705-00009-3v0-e 543
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 10 4.2. ppg duty setting register : pdut th e bit configuration of the ppg duty s etting r egister (p dut) is shown below . the ppg duty setting reg ister (pdut) specifies the duty of the ppg output waveform. ? pdut : address base_addr + 04 h ( access : half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 d15 d14 d13 d12 d11 d10 d9 d8 initial value x x x x x x x x attribute rx,w rx,w rx,w rx ,w rx,w rx,w rx,w rx,w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x attribute rx,w rx,w rx,w rx,w rx,w rx,w rx,w rx,w ? the ppg duty setting register has a buffer. data transfer from the buffer to the counter occurs automatically when a borrow occurs on the counter. ? for the ppg duty setting register, set a value that is smaller than the value set for the ppg cycle setting register (pcsr). ( see " 9. notes ". ) ? if an equal value is set on the ppg duty setting register and the ppg cycle setting register (pcsr), the result is as follows: ? if the polarity is normal (osel = "0" ), the output is always "h". ? if the polarity is inverted (osel = "1" ), the output is always "l". (the osel bit is the output polarity selection bit on the ppg control status register (pcn).) ? ppg duty setting registers must be accessed in half - word (16 - bit) or word (32 - bit). ( see " 9. notes ". ) mb91590 series mn705-00009-3v0-e 544
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 11 4.3. ppg control status register : pcn th e bit configuration of the ppg control status r egister (p cn) is shown below . the ppg control status register (pcn) controls operation of the ppg and shows status of the ppg as well . ? pcn : address base_addr + 06 h ( access : byte, half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 cnte strg mdse r trg cks1 cks0 pgms D initial value 0 0 0 0 0 0 0 D attribute r/w r0,w r/w r/w r/w r/w r/w r1,wx rewrite while in operation bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 egs1 egs0 iren irqf irs1 irs0 reserve d osel initial value 0 0 0 0 0 0 0 0 attribute r/w r/w r/w r(rm1),w r/w r/w r/w0 r/w rewrite while in operation : rewrite enabled, : rewrite disabled (see " 9. notes ". ) [b it15 ] cnte : timer operation enable cnte operation 0 inactive 1 active this bit enables th e operation of the ppg. [b it14 ] strg : software trigger strg operation 0 ppg operation is not influenced by the value written to this bit (which is always "0" when read). 1 a software trigger is generated. if this bit is set to "1", the ppg is activate d by a software trigger. the software trigger activates the ppg independent of the trigger generated by the en bit. [b it13 ] mdse : mode selection mdse mode 0 pwm operation 1 one - shot operation ? if this bit is set to "0", the ppg is enabled to perform pwm operation, thus generating a sequence of pulses. ? if this bit is set to "1", the ppg generates only one pulse. mb91590 series mn705-00009-3v0-e 545
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 12 [b it12 ] rtrg : restart enable rtrg operation 0 restart disabled 1 restart enabled when the restart enable bit is set to "1", the ppg is enab led to restart with a trigger ( such as software, an internal factor, or an external factor). [b it11 , bit 10 ] cks1, cks0 : count clock selection cks1 cks0 down counter count clock selection 0 0 peripheral clock (pclk) 0 1 division of the peripheral clock f requency by 4 1 0 division of the peripheral clock frequency by 16 1 1 division of the peripheral clock frequency by 6 4 [b it9 ] pgms : ppg output mask selection pgms operation 0 no output mask 1 output mask (output is fixed to "l": osel = " 0 ") ? when t his bit is set to "1", the ppg output can be clamped to "l" or "h" regardless of the mode selection, cycle, and duty settings. ? the output level can be specified by the output polarity selection bit (pcnn:osel). (n = 0 to 23 ) [b it8 ] - : undefined bit the r ead value is always "1". this does not affect the writing operation. [b it7 , bit 6 ] egs1, egs0 : trigger input edge selection egs1 egs0 selected edge 0 0 writing does not affect on the operation 0 1 rising edge 1 0 falling edge 1 1 both edges (rising or falling) select a source edge for activation with the trigger input edge se lection bit s (esg [ 1:0 ] ) to the trigger input selected by the trigger specification bits (gcn10/11/12 /13 /1 4 /1 5: tsel3/2/1/0 ) of the ppg registers. [b it5 ] iren : interrupt request ena ble iren operation 0 interrupt request disabled 1 interrupt request enabled [b it4 ] irqf : interrupt request flag irqf read write 0 no interrupt request clears the interrupt request flag. 1 i nterrupt request present writing does not affect on the oper ation if this bit is set to "0" when the interrupt request flag (irqf) = "1" , the interrupt request flag (irqf ="1") that is set takes precedence. mb91590 series mn705-00009-3v0-e 546
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 13 [b it3 , bit 2 ] irs1, irs0 : interrupt factor selection irs1 irs0 selection 0 0 software trigger or trigger i nput 0 1 borrow occurrence on the counter (match with the specified cycle) 1 0 counter matched with the specified duty value 1 1 borrow occurrence on the counter (matched with the specified cycle) or counter matched with duty value these bits select th e operation that generates an interrupt request. [b it1 ] reserved "0" should be written to this bit. [b it0 ] osel : ppg output polarity selection osel operation 0 normal polarity 1 inverted polarity if the ppg output mask selection bit (pcnn:pgms) is set to "1", setting the output polarity selection bit (osel) to "0" or "1" causes the output to be clamped to "l" or "h", respectively. (n = 0 to 23 ) mb91590 series mn705-00009-3v0-e 547
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 14 4.4. general control register 10-13 : gcn10 to gcn1 3 th e bit c onfiguration of the general control r egister 10- 13(gc n10 to gcn13) is shown below . the general control register selects the trigger input for ppg0 to ppg1 5. gcn10 : ppg0 to ppg 3 gcn11 : ppg4 to ppg 7 gcn12 : ppg8 to ppg 11 gcn1 3 : ppg 12 to ppg 15 ? gcn10 : address 025c h ( access: half - word) ? gcn11 : address 0260 h ( acce ss: half - word) ? gcn12 : address 0264 h ( access: half - word) ? gcn1 3 : address 0 144 h ( access: half - word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tsel3[3:0] tsel2[3:0] initial value 0 0 1 1 0 0 1 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tsel1[3:0] tsel0[3:0] initial value 0 0 0 1 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w mb91590 series mn705-00009-3v0-e 548
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 15 [b it15 to bit 12 ] tsel3[3:0] : trigger specification for ppg3 , ppg7 , ppg 11 and ppg 15 [b it11 to bit 8 ] tsel2[3:0] : trigger specification for ppg2 , ppg6 , ppg10 and ppg 14 [b it7 to bit 4 ] tsel1[3:0] : trigger specification for ppg1 , ppg5 , ppg9 and ppg 13 [b it3 to bit 0] tsel0[3:0] : trigger specification for ppg0 , ppg4 , ppg8 and ppg 12 tsel0[3:0] (ppg0/4/8 /12 ) tsel1[3:0] ( ppg1/5/9 /13 ) tsel2[3:0] (ppg2/6/10 /14 ) tsel3[3:0] (ppg3/7 /11/15 ) activation trigger specification 0 0 0 0 en0 bit (gcn20/21/22 /23 register) 0 0 0 1 en1 bit ( gcn20/21/22/2 3 register) 0 0 1 0 en2 bit ( gcn20/21/22/2 3 register) 0 0 1 1 en 3 bit ( gcn20/21/22 /2 3 register) 0 1 0 0 16 - bit reload timer 0 0 1 0 1 16 - bit reload timer 1 1 0 0 0 external trigger 1 0 0 1 external trigger 1 0 1 0 external trigger 1 0 1 1 external trigger 1 1 x x setting is prohibited other than above setting is prohibited (see " 9. notes " .) when an edge that is specified with the trigger input edge selection bits (pcnn : egs[1:0]) (n = 0 to 15 ) is detected for the specified activation trigger , selected ppg0 to ppg 15 will be activated. mb91590 series mn705-00009-3v0-e 549
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 16 4.5. general control register 14, 15 : gcn1 4, gcn1 5 th e bit configuration of the general control r egister 14,15 (gcn14, gcn15) is shown below . the general control register selects the trigger input for ppg 16 to ppg 23 . gcn1 4 : ppg 16 to ppg 19 gcn1 5 : ppg 20 to ppg 23 ? gcn1 4 : address 0 148 h ( access: half - word) ? gc n1 5 : address 0 14c h ( access: half - word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 tsel3[3:0] tsel2[3:0] initial value 0 0 1 1 0 0 1 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tsel1[3:0] tsel 0[3:0] initial value 0 0 0 1 0 0 0 0 attribute r/w r/w r/w r/w r/w r/w r/w r/w [b it15 to bit 12 ] tsel3[3:0] : trigger specification for ppg19 and ppg 23 [b it11 to bit 8 ] tsel2[3:0] : trigger specification for ppg18 and ppg 22 [b it7 to bit 4] tsel1[3:0] : trigger specification for ppg17 and ppg 21 [b it3 to bit 0] tsel0[3:0] : trigger specification for ppg16 and ppg 20 tsel0[3:0] (ppg 16/20 ) tsel1[3:0] (ppg 17/21 ) tsel2[3:0] (ppg 18/22 ) tsel3[3:0] (ppg 19/23 ) activation trigger specification 0 0 0 0 en0 bit (gc n2 4 /2 5 register) 0 0 0 1 en 1 bit (gcn2 4 /2 5 register) 0 0 1 0 en 2 bit (gcn2 4 /2 5 register) 0 0 1 1 en 3 bit (gcn2 4 /2 5 register) 0 1 0 0 16 - bit reload timer 2 0 1 0 1 16 - bit reload timer 3 1 0 0 0 external trigger 1 0 0 1 external trigger 1 0 1 0 exter nal trigger 1 0 1 1 external trigger 1 1 x x setting is prohibited other than above setting is prohibited (see " 9. notes " .) when an edge that is specified with the trigger input edge selection bits (pcnn : egs[1:0]) (n = 16 to 23 ) is detected for the sp ecified activation trigger , selected ppg 16 to ppg 23 will be activated. mb91590 series mn705-00009-3v0-e 550
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 17 4.6. general control register 20-25 : gcn20 to gcn2 5 th e bit configuration of the general control r egister 20- 25 (gcn20 to gcn25) is shown below . the general control register generates the internal trigger level with software for ppg0 to ppg 23 . gcn20 : ppg0 to ppg 3 gcn21 : ppg4 to ppg 7 gcn22 : ppg8 to ppg 11 gcn2 3 : ppg 12 to ppg 15 gcn2 4 : ppg 16 to ppg 19 gcn2 5 : ppg 20 to ppg 23 ? gcn20 : address 025f h ( access: byte) ? gcn21 : address 0263 h ( access: byte) ? gcn22 : address 0267 h ( access: byte) ? gcn2 3 : address 0 147 h ( access: byte) ? gcn2 4 : address 0 14b h ( access: byte) ? gcn2 5 : address 0 14f h ( access: byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved reserved reserved reserved en3 en2 en1 en0 initial va lue 0 0 0 0 0 0 0 0 attribute r/w0 r/w0 r/w0 r/w0 r/w r/w r/w r/w [b it7 to bit 4] reserved th ese bit s must always be written to "0". ( see " 9. notes " .) [b it3 ] en3 : t rigger input [b it2 ] en2 : t rigger input [b it1 ] en1 : t rigger input [b it0 ] en0 : t rigger input en n internal triggers en n 0 sets the level to "l" 1 sets the level to " h " ? sets the internal trigger level. ? when one of the en trigger inputs (en0, en1, en2, en3) is selected for the trigger specification bits (tsel3, tsel2, tsel1, tsel0) in the ge neral control registers ( gcn 10 to gcn 15) , selected en becomes the trigger input bit for the ppg. ? when the state selected with the trigger input edge selection bit s (egs[1:0] ) of the ppg control status register is activated by the trigger input bits (select ed en0, en1, en2 and en3) with software, this trigger will activate the ppg. mb91590 series mn705-00009-3v0-e 551
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 18 4.7. ppg timer register : ptmr th e bit configuration of the ppg timer r egister (ptmr) is shown below . the ppg timer register (ptmr) allows reading the ppg timer count down values of p pg0 to ppg 23 . ? ptmr : address base_addr + 00 h ( access: half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 t15 t14 t13 t12 t11 t10 t9 t8 initial value 1 1 1 1 1 1 1 1 attribute r,wx r,wx r,wx r,wx r,wx r,wx r,wx r,wx bit 7 bit 6 b it 5 bit 4 bit 3 bit 2 bit 1 bit 0 t7 t6 t5 t4 t3 t2 t1 t0 initial value 1 1 1 1 1 1 1 1 attribute r,wx r,wx r,wx r,wx r,wx r,wx r,wx r,wx ? the count value of the 16 - bit down counter can be read from these bits. ? th e ppg timer register ( ptmrn ) cannot be read correctly by the byte access . (n = 0 to 23 ) mb91590 series mn705-00009-3v0-e 552
chapter 17: ppg 4 . registers fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 19 4.8. ppg0 output division setting register : ppgdiv th e bit configuration of the ppg 0 output division setting r egister (p pgdiv) is shown below . the ppg0 output division setting register (ppgdiv) sets the output div ision ratio for ppg0. ? ppgdiv : address 026b h ( access: byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - - - - div1 div0 initial value - - - - - - 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w [b it7 to bit 2 ] - : undefined the read valu e is always "1". writing does not affect the operation. [b it1 , bit 0] div1, div0 : d ivision ratio setting div1 div0 division ratio 0 0 1/1 0 1 1/2 1 0 1/4 1 1 1/8 sets the division ratio for ppg0 output. note : following restrictions will apply for set ting 1/2, 1/4 and 1/8 divisions. ? the duty of the output waveform is fixed to 50%. ? setting the one - shot operation (pcn:mdse = 1) is prohibited. ? setting the ppg reversed output function (pcn:osel = 1) is prohibited. ? setting the ppg fixed output state (pcn:pgms, osel = 01, 10, 11) is prohibited. ? setting is prohibited when pcsr = pdut. mb91590 series mn705-00009-3v0-e 553
chapter 17: ppg 5 . operation fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 20 5. operation this section explains the operation of the ppg. there are 24 of ppg (programmable pulse generator) to output programmable pulses independently/ systematically. follow ings are explanations for each operation mode. 5.1 . pwm operation 5.2 . one - shot o peration 5.3 . restart operation mb91590 series mn705-00009-3v0-e 554
chapter 17: ppg 5 . operation fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 21 5.1. pwm o peration this section explains the pwm operation of the ppg. during the pwm operation, programmable variable - duty pulses are output at the ppg pin. (1) writing cycle values (2) writing duty value and transferring cycle value to the buffer (3) enabling of ppg operation (4) activation trigger generation (5) loading cycle value and duty value (6) rewriting duty value and transferring cycle value to the buffer (7) count er decrement ena b le count activ ation tr igger buf f er (cycle v alue) (2) wr iting (6) r ewr iting load load (7) d o wn count duty cycle v alid edge duty match duty match counter borr ow counter borr ow (12) clear (9) i nv ersion match match (14) reload (14) reload (13) reload (13) reload match borr ow inv ersion inv ersion clear (10) d o wn count (11) borr ow buf f er (duty v alue) do wn count v alue (ptmr) no r mal pola r ity inver ted pola r ity inter r upt f actor ppg pin output pcsr pdut mb91590 series mn705-00009-3v0-e 555
chapter 17: ppg 5 . operation fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 22 (8) the down counter mat ches the duty value (9) output level inversion at the ppg pin (10) count er decrement (11) counter borrow occurrence (12) clearing ppg pin output level (restoration to normal state) (13) reloading cycle value (14) reloading duty value (15) repeat step (6) t o (14) (see " 9.notes "). calculation formulas: cycle = {cycle value (pcsr) + 1} count clock duty = {duty value (pdut) + 1} count clock time to pulse output = [cycle value (pcsr) - duty value (pdut)] count clock mb91590 series mn705-00009-3v0-e 556
chapter 17: ppg 5 . operation fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 23 5.2. one - shot o peration this section explai ns the one- shot operation of the ppg. during the one - shot operation, one - shot pulses are output at the ppg pin. (8) i nv ersion ena b le count activ ation tr igger buf f er (cycle v alue) buf f er (duty v alue) do wn count v alue (ptmr) no r mal pola r ity inver ted pola r ity inter r upt f actor ppg pin output v alid edge duty match counter borr ow duty cycle (11) clear (10) borr ow (5) load (5) load (6) d o wn count (9) d o wn count (7) match mb91590 series mn705-00009-3v0-e 557
chapter 17: ppg 5 . operation fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 24 (1) writing cycle values (2) writing duty value and transferring cycle value to the buffer (3) enabling of ppg op eration (4) activation trigger generation (5) loading cycle value and duty value (6) count er decrement (7) the down counter matches the duty value (8) output level inversion at the ppg pin (9) count er decrement (10) counter borrow occurrence (11) clearing ppg pin output level (restoration to normal state) (12) end of operation sequence ( see " 9. notes ".) mb91590 series mn705-00009-3v0-e 558
chapter 17: ppg 5 . oper ation fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 25 5.3. restart operation this section explains the restart operation of the ppg. the restart operation is as follows: * n = duty, t = cycle, m = cycle setting re gister (pcsr) value, n = duty setting register (pdut) value when restart operation is disabled, second and latter triggers will be invalid for both the pwm operation and the one - shot operation. (triggers after the down counter is stopped will still be vali d even if second and latter triggers occur .) n t n t ? resta r ted b y pwm ope r ation resta r ted b y the t r igger rising edge detection tr igger tr igger m n 0 ppg m n 0 ppg ? resta r ted b y one-shot ope r ation rising edge detection resta r ted b y the t r igger mb91590 series mn705-00009-3v0-e 559
chapter 17: ppg 6 . setting fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 26 6. setting this section explains setting of the ppg. table 6-1 settings required for ppg operation setting setting register setting method cycle and duty value setting ppg cycle setting (pcsr0 to pcs r 23 ) ppg duty setting (pdut0 to pdut 23 ) see 7.1 enabling ppg op eration ppg control status (pcn0 to pcn 23 ) see 7.2 operation mode selection (pwm/one - shot) see 7.3 restart enable see 7.4 count clock selection see 7.5 ppg output mask selection see 7.6 trigger selection ? software trigger ? external trigger ? internal trigger (reload timer, gcn20/21/22/2 3 /2 4 /2 5: en bit) ppg control status (pcn0 to pcn 23 ) see 7.7 trigger input from trg pin general control 10/11/12 /1 3 /1 4 /1 5 (gcn10/11/12 /1 3 /1 4 /1 5 ) output polarity selection ppg control status (pcn0 to pcn 23 ) see 7.8 ppg pin output setting set the pins as peripheral out put. for setting, see the " chapter : i/o ports". trigger generation ? external trigger ? software trigger trigger input from trg pin see 4.3 ppg control status (pcn0 to pcn 23 ) ? reload timer see " chapter : reload timer". ? gcn20/21 /22 /2 3 /2 4 /2 5 : en bit general control 20/21/22 /2 3 /2 4 /2 5 (gcn20/21/22 /2 3 /2 4 /2 5 ) see 4.6 table 6-2 settings required for stopping ppg operation setting setting register setting method ppg stop bit setting ppg control status (pcn0 to pcn 23 ) see 7.11 mb91590 series mn705-00009-3v0-e 560
chapter 17: ppg 6 . setting fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 27 table 6-3 settings required for fixing output level setting setting register setting method output polarity select ion ppg control status (pcn0 to pcn 23 ) see 7.8 ppg output mask selection see 7.6 setting cycle value = duty value ppg duty setting (pdut0 to pdut 23 ) see 7.6 table 6-4 settings required for ppg interrupt setting setting register setting method setting for ppg interrupt vector and ppg interrupt level see " chapter : interrupt control (interrupt controller) ". see 7.12 ppg interrupt factor selection (activation trigger generation, borrow generation, duty match) ppg control status (pcn0 to pcn 23 ) see 7.13 ppg interrupt setting interrupt request clear interrupt request enable se e 7.14 mb91590 series mn705-00009-3v0-e 561
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 28 7. q&a this section explains q&a of the ppg. 7.1 . how to s et ( r ewrite) c ycle and d uty v alues 7.2 . how to e nab le/ s top ppg o peration? 7.3 how to s et ppg o peration m ode (pwm/ o ne - shot) 7.4 . how to r estart 7.5 . type and s election of c ount c lock 7.6 . how to f ix the ppg p in o utput l evel 7.7 . type and s election of a ctivation t rigger 7.8 . how to r everse the output p olarity 7.9 . how to c hange a p in to a ppg o utput p in 7.10 . how to g enerate a ct ivation t rigger 7.11 . how to s top ppg o peration 7.12 . i nterrupt - related r egisters 7.13 . type a nd s election of i nterrupts 7.14 . how to e nable/ d isable/ c lear interrupt mb91590 series mn705-00009-3v0-e 562
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 29 7.1. how to s et ( r ewrite) cycle and d uty values this section explains how to set (rewrite) the cycle and duty values. cycle value setting and duty value setting ? set the cycle value in the ppg cycle setting register pcsrn. (n = 0 to 23 ) ? set the duty value in the ppg duty setting register pdutn. (n = 0 to 23 ) ? as the ppg cycle setting register and ppg dut y setting register have their own buffers, no timing consideration for writing is required. calculation formulas: pcsr register value = {cycle/count clock} - 1 pdut register value = {"h" width (duty) * /count clock} - 1 *: normal polarity (osel=0) available setting range pcsr register value = pdut register value to ffff h (65535) pdut register value = 0 to pcsr register value note : be sure to set the duty value after the cycle is set.(see " 9. notes ".) mb91590 series mn705-00009-3v0-e 563
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 30 7.2. how to enable/s top ppg operation? this section explains how to enable/stop the ppg operation . enabling ppg operation use the ppg operation enable bit (pcnn : cnte) . (n = 0 to 23) control ppg operation enable bit (cnte) how to stop ppg operation set to "0" how to enable ppg operation set to "1" activate the ppg after the ppg operation is enabled. (see " 9. notes ".) mb91590 series mn705-00009-3v0-e 564
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 31 7.3. how to s et ppg o peration m ode (pwm/ o ne - shot) this section explains how to set the ppg operation mode (pwm/one - shot). use the mode selection bit (pcnn : mdse) for selecting an operation mode. (n = 0 to 23 ) operating mode mode selection bit (mdse) how to set to pwm operation set to "0" how to set to one - shot operation set to "1" (see " 9. notes ".) mb91590 series mn705-00009-3v0-e 565
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 32 7.4. how to restart this section explains how to restart the ppg . restart enable ppg restart can be enabled while the ppg is running. use the restart enable bit (pcnn : rtrg) for setting.(n = 0 to 23 ) (see " 9. notes ".) mb91590 series mn705-00009-3v0-e 566
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 33 7.5. type and selection of c ount c lock this section explains the type and selection of the count clock. count clock selection the count clock can be selected from the following four types in the table below: use the count clock selection bit (pcnn : cks[1:0]). (n = 0 to 23 ) count clock count clock selection bit example) peripheral clock (pclk) = 16 mhz cks1 cks0 count clock cycle (1 to ffff h ) pclk 0 0 16mhz 12 5.0 ns to 4.096 s pclk/4 0 1 4mhz 500 ns to 16.384 s pclk/16 1 0 1mhz 2.0 s to 65.536 ms pclk/64 1 1 250khz 8.0 s to 262.144 ms (see " 9. notes " .) mb91590 series mn705-00009-3v0-e 567
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 34 7.6. how to fix the ppg p in o utput l evel this section explains how to fix the ppg pin output level. ppg output mask s election the ppg pin output level can be fixed. use the ppg output mask selection bit (pcnn : pgms) and duty value (pdut) for setting.(n = 0 to 23 ) ppg pin output ppg output polarity selection bit (osel) setting method how to fix the level to "l" in normal polarity osel is "0" set the ppg output mask selection bit (pgms) to "1" how to fix the level to "h" in normal polarity osel is "0" set cycle value (pcsr) = duty value (pdut) how to fix the level to "h" in reversed polarity osel is "1" set the ppg output mask selection bit (pgms) to "1" how to fix the level to "l" in reversed polarity osel is "1" set cycle value (pcsr) = duty value (pdut) ppg ppg example outputting pwm to all "l" or all "h" decrease the duty v alue wr ite "1" to pgms (mask bit) on occurrence of an inter r upt caused b y a borr o w. if "0" is wr itten to pgms (mask bit) on occurrence of an inter r upt caused b y a borr ow , a ppg wavefor m can be gene r ated without outputting glitch . increase the duty v alue wr ite the same v alue as the cycle setting register v alue to the duty cycle setting register on occurrence of an inter r upt caused b y a compare match . setting register mb91590 series mn705-00009-3v0-e 568
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 35 7.7. type and selection of a ctivation trigger this section explains the type and selection of the activation trigger. ? selecting internal trigger ? the software trigger is always valid. ? the internal trigger of ppg0 to ppg 3 is the gcn20 register . the internal trigger of ppg 4 to ppg 7 is the gcn2 1 register . the internal trigger of ppg 8 to ppg 11 is th e gcn2 2 register . the internal trigger of ppg 12 to ppg 15 is the gcn2 3 register . the internal trigger of ppg 16 to ppg 19 is the gcn2 4 register . the internal trigger of ppg 20 to ppg 23 is the gcn2 5 register . ? use tsel0/tsel1/tsel2/tsel3 of the following general control register s for the settings for the internal triggers : gcn 10 register ( ppg0 to ppg 3) gcn 11 register ( ppg4 to ppg 7) gcn 12 register ( pp g8 to ppg 11) gcn 13 register ( ppg 12 to ppg 15) gcn 14 register ( ppg 16 to ppg 19) gcn 15 register ( ppg 20 to ppg 23 ) setti ngs for ppg0 to ppg 3 are as follows: internal trigger example for ppg0 (gcn10 : ts el0[3:0] setting value) example for ppg 1 (gcn10 : ts el 1 [3:0] setting value) example for ppg 2 (gcn10 : ts el 2 [3:0] setting value) example for ppg 3 (gcn10 : ts el 3 [3:0] setting value) how to select en0 bit of the gcn20 register set to "0000" how to select en1 bit of the gcn20 register set to "0001" how to select en 2 bit of the gcn20 register set to "0010" how to select en 3 bit of the gcn20 register set to "0011" how to se lect reload timer 0 set to "0100" how to select reload timer 1 set to "0101" mb91590 series mn705-00009-3v0-e 569
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 36 ? selecting external trigger use tsel0/tsel1/tsel2/tsel3 of the following general control register s for the settings for the external triggers : gcn10 register ( ppg0 to ppg 3) gcn1 1 register ( ppg4 to ppg 7) gcn12 register ( ppg8 to ppg 11) gcn13 register (ppg12 to ppg 15) gcn14 register ( ppg16 to ppg 19) gcn15 register ( ppg20 to ppg 23) settings for ppg0 to ppg 3 are as follows: external trigger example for ppg0 (gcn10 : tse l0[3:0] setting v alue) example for ppg 1 (gcn10 : tse l1 [3:0] setting value) example for ppg 2 (gcn10 : tse l2 [3:0] setting value) example for ppg 3 (gcn10 : tse l3 [3:0] setting value) how to select external trigger (trgn) set to any of following values. "1000" , "1001", " 1010", "1011" specifying a same trigger to multiple ppg s will activate multiple ppg s simultaneously. (see " 9. notes ".) ? selecting internal/external trigger edge use trigger input edge selection bit s (pcn0 : egs[1:0]) to (pcn 23: egs[1:0]) for internal/external trigger edge settings. selecting internal trigger edge trigger input edge selection bit s (egs[1:0]) no trigger is detected (software trigger only) set to "00" trigger is generated at "l" "h" (rising) set to "01" trigger is generated at "h" "l" (fal ling) set to "10" trigger is generated at both edges set to "11" (see " 9. notes ".) mb91590 series mn705-00009-3v0-e 570
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 37 7.8. how to reverse the output polarity the section explains how to reverse the output polarity. output polarity selection the polarity in the normal state can be specified as following table: use the ppg output polarity selection bit (pcnn : osel) for setting. ( n = 0 to 23) ("normal state" is a state which does not output pulses.) output level in the normal state ppg output polarity selection bit (osel) set to "0" set to "1" to achiev e "h" l evel output (inverted polarity) l h h to achiev e "l" l evel output (normal polarity) l hl mb91590 series mn705-00009-3v0-e 571
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 38 7.9. how to c hange a p in to a ppg o utput pin the section explains how to change a pin to a ppg output pin. set the pins as peripheral output. for setting, see " chapter : i/o ports". mb91590 series mn705-00009-3v0-e 572
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 39 7.10. how to generate a ctiva tion t rigger the section explains how to generate an activation trigger. trigger generation th e f ollowing is how to generate activation triggers. how to activate software trigger use the software trigger bit (pcnn : strg) for setting. (n = 0 to 23) if "1" is written to the software trigger bit (strg), the activation trigger will be generated. this bit is always valid independent of the state of gcn10 register to gc n15 register. how to activate with external trigger see " 7.7 type and s election of a ctivation t rigger ". set the pins trg0, trg1 and trg2 as peripheral input. for setting, see " chapter : i/o ports". then you will be able to generate the activation trigger by changing the input level for the pins tr g0, trg1 and trg2. how to activate with reload timer 0/1 you need to set up and activate the reload timer. see " chapter : reload timer" for details. the activation trigger will be generated when underflow of the reload timer generated the specified edge in the reload timer output signal. how to activate with en trigger input bits (gcn20/21/22 /2 3 /2 4 /2 5: en [ 0:3] ) the activation trigger will be generated by rewriting the level of the en trigger input bits (gcn20/21/22/2 3 /2 4 /2 5: en [ 0:3] ) with software. edge softwa re setting (en0, en1, en2, en3) rising edge first set the en bit to "0", then set the en bit to "1". falling edge first set the en bit to "1", then set the en bit to "0". how to activate multiple ppg s simultaneously multiple ppg s will be activated on t rigger by specifying the same trigger (trigger input bit) from the ppg trigger specification bits. note : the ppg will not be activated on the activation trigger before the ppg operation is enabled. be sure to enable the ppg operation before generating the activation trigger. (see " 7.2 how to e nable/ s top ppg o peration? ".) mb91590 series mn705-00009-3v0-e 573
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 40 7.11. how to s top ppg o peration this section explains how to stop the ppg operation. set the ppg stop bit. (see " 7.2 how to e nable/ s top ppg o peration? ".) mb91590 series mn705-00009-3v0-e 574
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 41 7.12. i nterrupt -related registers this section explains the interrupt - related registers. setting for ppg interrupt vector and ppg interrupt level the ppg number, interrupt level and interrupt vector are as follows: for information on the interrupt level and interrupt vector, see " chapter : interrupt control (interrupt controller) ". interrupt vector (default) interrupt level setti ng register (icr[4:0]) ppg0 #40 address: 0fff5c h interrupt level register (icr24) address: 004 58 h ppg1 ppg10 ppg11 ppg20 ppg21 ppg2 #41 address: 0fff58 h interrupt level register (icr25) address: 004 59 h ppg3 ppg12 ppg13 ppg22 p pg23 ppg4 #42 address: 0fff54 h interrupt level register (icr26) address: 004 5a h ppg5 ppg14 ppg15 ppg6 # 43 address: 0fff50 h interrupt level register (icr27) address: 004 5b h ppg7 ppg16 ppg17 ppg8 # 44 address: 0fff4c h interrupt level register (icr28) address: 004 5c h ppg9 ppg18 ppg19 clear the interrupt request flags (pcn n: irqf) by software before the recovery from the interrupt process as the flags will not be cleared automatically. (write "0" to the irqf bit) ( n = 0 to 23) mb91590 series mn705-00009-3v0-e 575
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 42 7.13. type and selection of i nterrupts this section explains the type and selection of interrupts . selecting interrupt factor the i nterrupt factor can be selected from following four factors: use interrupt factor setting bit s (pcnn : irs[1:0]) for setting. ( n = 0 to 23) interrupt factor interrupt factor setting bit s (irs[1:0]) software trigger or internal trigger set to "00" down counter borrow (match with the specified cycle) set to "01" duty match set to "10" down counter borrow (match with the specified cycl e) o r duty match set to "11" mb91590 series mn705-00009-3v0-e 576
chapter 17: ppg 7 . q&a fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 43 7.14. how to enable/disable/clear interrupt this section explains how to enable/disable/clear interrupt. interrupt request enable flag and interrupt request flag use the interrupt request enable bit (pcnn : iren) for enabling interru pts. ( n = 0 to 23) operation interrupt request enable bit (iren) how to disable interrupt request set to "0" how to enable interrupt request set to "1" use the interrupt request bit (pcnn : irqf) for clearing interrupt requests . (n = 0 to 23) operation i nterrupt request bit (irqf) how to clear interrupt request write "0" (see " 9. notes ".) mb91590 series mn705-00009-3v0-e 577
chapter 17: ppg 8 . sample programs fujitsu semiconductor limited c hapter : ppg fujitsu semiconductor confidential 44 8. sample programs this section explains sample programs of the ppg. setting procedure example 1 pwm output from ppg4, software trigger (duty1/4), normal polarity initi al setting (ppg4) activation (ppg4) < initial setting > - port register name.bit name ppg output setting for ports see " chapter : i/o port". - ppg4 control register name.bit name control register set ting time r operation enable ? software trigger (unprocessed) ? operation mode selection ? restart disable ? clock source selection ? output mask selection ? edge selection ? interrupt disable ? interrupt flag clear ? output polarity selection ? pcn4 .cnte .strg .mdse . rtrg .cks1 -0 .pgms . egs1 -0 .iren .irqf .irs1 -0 .osel - cycle setting register name.bit name cycle setting for ppg4 pcsr4 - duty setting register name.bit name duty setting for ppg4 pdut4 < activation > - ppg4 activation register name.bit name ppg4 activation pcn4.strg < other s> ( note ) you need settings for clock and ? _set_il ? (numerical value) in advance. see ? chapter : clock ? and ? chapter : interrupt control (interrupt controller) ? for details. program exampl e 1 void ppg _sample_1(void) { ppg4 _initial(); ppg4 _start(); } void ppg4 _initial(void) { port_setting_ppg4_out(); /* set the ppg4 pins as peripheral in put. */ io_ pcn4 . hword = 0x 8000 ; /* setting value = 1000_0000_0000_000 0 */ /* bit15 = 1 cnte timer enable */ /* bit14 = 0 strg software trigger */ /* bit13 = 0 mdse pwm operation */ /* bit12 = 0 rtrg restart disable */ /* bit11 to 10 = 00 cks1,0 */ /* bit9 = 0 pgms ppg output mask */ /* bit8 = 0 undefined bit */ /* bit 7 to 6 = 00 egs1,0 edge selection: disabled */ /* bit5 = 0 iren interrupt request enable */ /* bit4 = 0 irqf interrupt request flag */ * bit3 to 2 = 00 irs1,0 interrupt factor: software trigger */ /* bit1 = 0 undefined bit */ /* bit 0 = 0 osel normal polarity */ io_pcsr4 = 0x0909; /* ppg cycle setting */ io_pdut4 = 0x0242; /* ppg duty ratio (1/4) setting */ } void ppg4 _start(void) { io_pcn4.bit.strg = 1; /* bit14 = 1 strg software trigger */ } mb91590 series mn705-00009-3v0-e 578
chapter 17: ppg 8 . sample programs fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 45 setting procedure example 2 ppg one - shot output from ppg2, reload timer ch . 0 (duty1/2), normal polarity initial setting (ppg2) initial setting (reload timer 0) activation (ppg2) < initial setting > - port register name.bit name ppg output setting for ports see ? chapter : i/o port ? . - ppg2 control register name.bit name control register setting time r operation enable ? software trigger (unprocessed) ? operation mode selection ? restart disable ? clock source selection ? output mask selection ? edge selection ? interrupt disable>> interrupt flag clear>> output polarity selection>> pcn2 .cnte .strg .mdse . rtrg .cks1 -0 .pgms .egs1 -0 .iren .irqf .irs1 -0
osel - cycle setting register name.bit name cycle setting for ppg2 pcsr2 - duty setting register name.bit name duty setting for ppg2 pdut2 - t rigger selection register name.bit name ppg2 trigger selection gcn10.tsel2 < initial setting (reload timer 0) > - control for reload timer 0 register name.bit name control register setting mode selection ? internal clock selection ? trigger selection ? output level selection>> reload enable ? interrupt disable>> interrupt flag clear>> count enable ? software trigger (unprocessed) ? tmcsr0 .mod .trgm,csl .trgm .ou tl .reld .inte .uf .cnte .trg - count value count value setting tmrlra0 - trigger will be input to the ppg2 by activation of the reload timer 0 register name.bit name software trigger generation tmcsr0.trg < other s> ( note ) you need s ettings for clock and ? _set_il ? (numerical value) in advance. see ? chapter : clock ? and ? chapter : interrupt control (interrupt controller) ? for details. program example 2 void ppg _sample_ 2 (void) { ppg2 _initial(); rtim0_initial(); rtim 0_ start (); } void ppg2 _initial(void) { port_setting_ppg2_out(); /* set the ppg2 pins as peripheral in put */ io_ pcn2 . hword = 0x 8040 ; /* setting value = 1000_0000_ 01 00_000 0 */ /* bit15 = 1 cnte timer enable */ /* bit14 = 0 strg software trigger */ /* bit13 = 0 mdse pwm operation */ /* bit12 = 0 rtrg restart disable */ /* bit11 to 10 = 00 cks1,0 */ /* bit9 = 0 pgms ppg output mask */ /* bit8 = 0 undefined bit */ /* bit7 to 6 = 01 egs1,0 edge selection: rising edge */ /* bit5 = 0 i ren interrupt request enable */ /* bit4 = 0 irqf interrupt request flag */ /* bit3 to 2 = 00 irs1,0 interrupt factor: software trigger */ /* bit1 = 0 undefined bit */ / * bit0 = 0 osel normal polarity */ io_pcsr2 = 0x0909; /* ppg cycle setting */ io_pdut2 = 0x0484; /* ppg duty ratio (1/2) setting */ io_gcn10.bit.tsel2 = 4; /* bit11 to 8 = 0100 tsel23 to 20 reload timer ch . 0 */ } void rtim0_initial(void) { io_tmcsr0.hword = 0x0012; /* setting value = 00 00_0000_0001_0010 */ /* bit15 to 14 = 00 mod=00 single mode */ /* bit13 to 12 = 00 trgm=00 no external trigger detection / software trigger */ /* bit11 to 9 = 000 csl=000 count source selection (peripheral clock/2) */ /* bit8 to 6 = 000 gate=0 , ef=0 */ /* bit5 = 0 outl=0 external output level */ /* bit4 = 1 reld=1 reload enable */ /* bit3 = 0 inte=0 interrupt request disabled */ /* bit2 = 0 uf=0 flag clear */ /* bit1 = 1 cnte=1 time r operation enable / activation trigger wait */ /* bi t0 = 0 trg=0 trigger is still disabled */ io_tmrlra0 = 0xffff; /* initial value for counting */ } void rtim0_start(void) { io_tmcsr0 = io_tmcsr0 | 0x0001; /* bit0 = 1 trg software trigger */ } mb91590 series mn705-00009-3v0-e 579
chapter 17: ppg 8 . sample programs fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 46 setting procedure example 3 ppg one - shot output from ppg1, high output, a ctivation trigger (gcn20:en1) initial setting (ppg1) activation (ppg1) < initial setting > -p ort register name.bit name ppg output setting for ports see ? chapter : i/o port ? . -p pg1 control register name.bit name control register setting timer operation enable ? software trigger (unprocessed) ? operation mode selection ? restart disable ? clock source selection ? output mask selection ? edge selection ? interrupt disable>> interrupt flag c lear>> output polarity selection>> pcn1 .cnte .strg .mdse . rtrg .cks1 -0 .pgms .egs1 -0 .iren .irqf .irs1 -0 .
sel - cycle setting register name.bit name cycle setting for ppg1 pcsr1 - duty setting register name .bit name duty setting for ppg1 pdut1 - trigger selection register name.bit name ppg1 trigger selection gcn10.tsel 1 - trigger signal level register name.bit name trigger level = "l" gcn20.en1 - ppg1 activati on register name.bit name ppg1 activation pcn4.strg trigger signal level register name.bit name trigger level = "h" gcn20.en1 < other s> ( note ) you need settings for clock and ? _set_il ? (numerical value) in advance. see ?c hapter : clock ? and ? chapter : interrupt control (interrupt controller) ? for details. program example 3 void ppg _sample_ 3 (void) { ppg1 _initial(); ppg1 _ start (); } void ppg1 _initial(void) { port_setting_ppg1_out(); /* set the ppg1 pins as peripheral in pu t */ io_ pcn1 . hword = 0x a040 ; /* setting value = 1010_0000_ 01 00_000 0 */ /* bit15 = 1 cnte timer enable */ /* bit14 = 0 strg software trigger */ /* bit13 = 1 mdse one - shot operation */ /* bit12 = 0 rtrg restart disable */ /* bit11 - 10 = 00 cks1,0 */ * bit9 = 0 pgms ppg output mask */ /* bit8 = 0 undefined bit */ /* bit7 - 6 = 01 egs1,0 edge selection: rising edge */ /* bit5 = 0 iren interrupt request enable */ /* bit4 = 0 irqf interrupt request flag */ /* bit3 - 2 = 00 irs1,0 interrupt factor: software trigger */ /* bit1 = 0 undefined bit */ /* bit0 = 0 osel normal polarity */ io_pcsr1 = 0x0909; /* ppg cycle setting */ io_pdut1 = 0x0484; /* ppg duty ratio (1/2) setting */ io_gcn10. bit.tsel 1 = 1 ; /* bit 3-0 = 0 001 tsel03 to 00 en1 bit of gcn20 */ io_gcn20 = 0x00; /* bit1 = 0 en1 bit of gnc20 */ } void ppg1 _start(void) { io_pcn4.bit.strg = 1; /* bit14 = 1 strg software trigger */ io_gcn20 = 0x02; /* bit1 = 1 en1 bit of gnc20 */ } mb91590 series mn705-00009-3v0-e 580
chapter 17: ppg 8 . sample programs fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 47 setting procedure example 4 interval interrupt ppg output from ppg4, software trigger (duty1/4), normal polarity initial setting (ppg4) activation (ppg4) interrupt - port register name.bit name ppg output setting for ports see ? chapter : i/o port ? . - ppg1 control register name.bit name control register setting time r operation enable ? software trigger (unprocessed) ? operation mode selection ? restart disable ? clock source selection ? output mask selection ? edge selection ? interrupt disable>> interrupt flag clear>> output polarity selection>> pcn4 .cnte .strg .mdse . rtrg .cks1 -0 .pgms .egs1 -0 .iren .irqf .irs1 -0 .osel - cycle setting register name.bit name cycle setting for ppg4 pcsr4 - duty setting register name.bit name duty setting for ppg4 pdut4 -i nterrupt setting re gister name.bit name ppg4 interrupt level setting icr 26 setting for i flag (ccr) - ppg4 activation register name.bit name interrupt enable pcn4. i ren ppg4 activation pcn4.strg < interrupt > - interrupt process register name.bit name ( given process ) interrupt request flag clear pcn4.irqf < interrupt vector > vector table setting < other s> ( note ) you need settings for clock and ? _set_il ? (numerical value) in advance. see ? chapter : clock ? and ? chapter : interrupt control (interrupt controller) ? for details. program example 4 void ppg _sample_ 4 (void) { ppg4 _initial(); ppg4 _ start (); } void ppg4 _initial(void) { port_setting_ppg4_out(); /* set the ppg4 pins as peripheral in put. */ io_ pcn4 . hword = 0x 8 004 ; /* setting value = 1000_0000_ 00 00_0 100 */ /* bit15 = 1 cnte timer enable */ /* bit14 = 0 strg software trigger */ /* bit13 = 1 mdse on e- shot operation */ /* bit12 = 0 rtrg restart disable */ /* bit11 to 10 = 00 cks1,0 */ /* bit9 = 0 pgms ppg output mask */ /* bit8 = 0 undefined bit */ /* bit7 to 6 = 01 egs1,0 edge selection: rising edge */ /* bit5 = 0 iren interrupt request enable */ /* bit4 = 0 irqf interrupt request flag */ /* bit3 to 2 = 01 irs1,0 i nterrupt factor: cycle match */ /* bit1 = 0 undefined bit */ /* bit0 = 0 osel normal polarity */ io_pcsr4 = 0x0909; /* ppg cycle setting */ io_pdut4 = 0x0242; /* ppg duty ratio (1/4) setting */ io_icr[26].byte = 0x10; /* interrupt level (given value) */ __ei(); /* interrupt enable */ } void ppg4 _start(void) { io_pcn4.bit.iren = 1; /* bit5 = 1 iren interrupt request enable */ io_pcn4.bit.strg = 1; /* bit14 = 1 strg software trigger */ } __interrupt voi d ppg4_int(void) { /* given process */ io_pcn4.bit.irqf = 0; /* bit14 = 0 irqf interrupt request flag */ } interrupt routine must be specified with the vector table. #pragma intvect ppg4_int 42 mb91590 series mn705-00009-3v0-e 581
chapter 17: ppg 9 . notes fujitsu semiconductor limited chapter : ppg fujitsu semiconductor confidential 48 9. notes notes on the use of the ppg are shown in this sectio n. ? if the timing when the interrupt request flag ( pcnn : irqf ) becomes "1" and the timing to become "0" are duplicated, the operation for setting the interrupt request flag to "1" will be prioritized and the request for clearing the flag will be invalid. ( n = 0 to 23) ? if the load timing and counting timing of the down counter are duplicated, the load operation will be prioritized. ? the time from the activation trigger to finish loading the counter value requires up to 2.0 t (t: per ipheral clock). ? be sure to set the duty values (pdutn) after the cycle value is set if you make initial setting and rewriting of the cycle value pcsrn. (be sure to write the values in the order of (1) pcsrn, (2) pdutn.) i n addition, only pdut can be rewrit ten for rewriting the duty value only. ( n = 0 to 23) ? when you set the duty values (pdutn), use values smaller than the cycle values (pcsrn). when larger values are set, rewrite the duty values to the smaller ones after the ppg operation is disabled. ( n = 0 to 23) ? the ppg cycle setting register pcsrn and ppg duty setting register pdutn must be accessed in half - word (16 - bit). both upper value and lower value will not be written if the access is made in byte. ( n = 0 to 23) ? to activate the ppg, the timer operat ion enable bit ( pcnn : cnte ) must be set to "1" to enable the ppg operation before the activation or simultaneously. ( n = 0 to 23) ? do not change the configuration of the mode (mdse), restart enable (rtrg), count clock (cks[2:0]), trigger input edge (egs[1:0] ), interrupt factor (irs [1:0] ), internal trigger (tsel), and output polarity selection (osel), while the ppg is in operation. if you changed the value while the ppg is in operation, first disable the ppg operation, and then retry register setting. ? when you write values to the gcn20/21/22 /23/24/25 , the undefined part of upper 4 bits must always be written to "0". if you have written "1" instead of "0", first stop the ppg operation, and then rewrite them. ? when values other than specified values (1100 to 1111) are set to the activation trigger selection bits (tsel3, tsel2, tsel1, tsel0) of the gcn10/11/12 /13/14/15 , the operation will be returned to the normal operation if you first disable the ppg operation, then write the specified values. ? when the timer opera tion enable bit ( pcnn : cnte ) is set to "0" to disable the ppg operation while the ppg n is in operation, the ppg will be stopped to retain the status. (count value and output level will be retained) moreover, when the timer operation enable bit ( pcnn : cnte ) i s set to "1" to enable the ppg operation, the ppg will be restarted from the state where the ppg stopped. ( n = 0 to 23) ? as writing to the bits 11 and 10 (count clock selection bit s cks1 and cks0) of the ppg control register will immediately be reflected ju st after the writing, setting change must be performed with the counting stopped. tr igger maxi m um 2.0t load clo ck count v alue ppg inter r upt counter borr ow v alid edge duty match mb91590 series mn705-00009-3v0-e 582
chapter 18: watchdog timer 1 . overview fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 1 chapter : watchdog timer this chapter explains the watchdog timer. 1. overview 2. features 3. configuration 4. registers 5. operation 6. usage example code : 18_mb91590_h m_e _wdt_00 5 _201111 27 mb91590 series mn705-00009-3v0-e 583
chapter 18: watchdog timer 1 . overview fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 2 1. overview this section explains the overview of the watchdog t imer. this series has two watchdog timers that can detect software and hardware running out of control, and generate reset requests. figure 1-1 block diagram (overview) watchdog 0 (s oftware watchdog) watchdog reset 0 watchdog 1 watchdog reset 1 (h ardware watchdog) bus access peripheral clock (pclk) cr oscillat or mb91590 series mn705-00009-3v0-e 584
chapter 18: watchdog timer 2 . features fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 3 2. features this section explains features of the watchdog timer. ? watchdog timer 0 (software watchdog) ? stop mode detection function able to detect the transition to watch mode or stop mode and generate a reset request. ? watchdog timer clear the timer is cleared by operation initialization reset or by writing the inverse value of the value previously written to the clear register. ? illegal write detection function if the incorrect value is written to the clear register, a reset request is generated. ? watchdog timer period the period can be selected from among sixteen choices of the peripheral clock (pclk) (2 9 to 2 24 ) cycles. ? count stop conditions the count stops while the cpu is stopp ed. ? watchdog timer 1 (hardware watchdog) this timer is driven by the clock generated by the built - in cr oscillator circuit immediately after the reset is released. for information on cr oscillator settings (calibration), see "chapter : rtc/wdt1 ( calibration ) ". ? watchdog timer clear the timer is cleared by the operation initialization reset or by writing " 0x a5" to the clear register. ? illegal write detection function if a value other than " 0x a5" is written to the clear register, a reset request is generated. ? wa tchdog timer period the period is fixed by the hardware at cr oscillator 2 15 cycles. ? count stop conditions the count stops when using ice, during sleep mode, watch mode, stop mode, and when waiting for the oscillator to stabilize when recovering from sta ndby mode. mb91590 series mn705-00009-3v0-e 585
chapter 18: watchdog timer 3 . configuration fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 4 3. configuration this section shows the configuration of the watchdog timer. figure 3-1 block diagram (detailed) wdtcpr0 c pa t wdtcr0 rstp wdtcr0 wt wdtcpr1 c pa t wdtcr1 wt pclk ov erfl ow ov erfl ow pclk cr oscillator cr oscillator cr oscillator cmp rst rst stop/ w atch mode pclk en rst en rst wdt0 stops wdt1 stops in sleep mode and stand b y mode pclk "0xa5" register v alue cmp register v alue w atchdog timer 0 w atchdog timer 1 w atchdog reset 0 w atchdog reset 1 ov erflow ov erflow r s q r s q maintained in sleep mode and stand b y mode (24-bit up counter) period s el ect io n maintained (24-bit up counter) period s el ect io n "0xa5" overflow cycle select ion overflow cycle select ion mb91590 series mn705-00009-3v0-e 586
chapter 18: watchdog timer 4 . registers fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 5 4. registers this section explains the registers of the watchdog timer. table 4-1 register s map address register s register function +0 +1 +2 +3 0x003c wdtcr0 wdtcpr0 wdtcr1 wdtcpr1 watchdog timer configuration register 0 watchdog timer 0 clear register watchdog timer 1 cycle information register watchdog timer 1 clear register mb91590 series mn705-00009-3v0-e 587
chapter 18: watchdog timer 4 . regis ters fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 6 4.1. watchdog control register 0 : wdtcr0 (watchdog timer conf iguration register 0) the bit configuration of the w atchdog c ontrol r egister 0 ( wdtcr0 ) is explained . this register configures each of the settings of watchdog timer 0. writing to this register is ignored after watchdog timer 0 activates . ? wdtcr0 : address 003c h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved rstp reserved wt[3:0] initial value 0 0 0 0 0 0 0 0 attribute r0,w 0 r/w r0,w 0 r0,w 0 r/w r/w r/w r/w [b it 7] r eserved "0" is always written to this bit . the readi ng value is "0" . [b it6 ] rstp (reset by stop) : stop mode detection reset enable this bit configures whether a reset is generated when a transition to watch mode or stop mode is detected while watchdog timer 0 is operating. when this bit is enabled, the wat chdog timer reset 0 occurs when the cpu switches to watch mode or stop mode. when this bit is not enabled, watchdog timer 0 is paused when the cpu switches to watch mode or stop mode, and the count stops until the cpu recovers from watch mode or stop mode. rstp stop mode detection 0 not detected (initial value) 1 generates a reset when detected writing to this bit is ignored after watchdog timer 0 activates . [b it 5, bit4] r eserved "0" is always written to these bit s. the reading value is "0" . mb91590 series mn705-00009-3v0-e 588
chapter 18: watchdog timer 4 . registers fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 7 [b it3 to bit 0] wt[3:0] (watchdog timer interval) : watchdog timer cycle selection these bits configure the number of cycles from when watchdog timer 0 was last cleared until watchdog reset 0 is issued as follows. wt[3:0] watchdog timer 0 cycle 0000 pclk (peripher al clock) 2 9 cycles 0001 pclk 2 10 cycles 0010 pclk 2 11 cycles 0011 pclk 2 12 cycles 0100 pclk 2 13 cycles 0101 pclk 2 14 cycles 0110 pclk 2 15 cycles 0111 pclk 2 16 cycles 1000 pclk 2 17 cycles 1001 pclk 2 18 cycles 1010 pclk 2 19 c ycles 1011 pclk 2 20 cycles 1100 pclk 2 21 cycles 1101 pclk 2 22 cycles 1110 pclk 2 23 cycles 1111 pclk 2 24 cycles writing to these bits are ignored after watchdog timer 0 activates . watchdog timer 0 is not counted during periods where the cpu is not operating. counting is performed while the cpu is operating even if dma transfers are being performed. mb91590 series mn705-00009-3v0-e 589
chapter 18: watchdog timer 4 . registers fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 8 4.2. watchdog timer 0 clear register : wdtcpr0 (watchdog timer clear pattern register 0) the bit configuration of the w atchdog timer 0 clear r egister ( wdtc p r0 ) is explained . this register activates or clears (delays the issue of a reset) watchdog timer 0. ? wdtcpr0 : address 003d h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpat[7:0] initial value 0 0 0 0 0 0 0 0 attribut e r0,w r0,w r0,w r0,w r0,w r0,w r0,w r0,w [b it7 to bit 0] cpat[7:0] (clear pattern) : watchdog timer 0 clear watchdog timer 0 activates by the first write to this register after the reset is released. the watchdog timer is cleared after being activated by writing a value with all of the bits inverted from the previous value written. if a value other than the inverse value of the previously written value is written, the watchdog reset 0 is issued at that time. the value read out from this register is always " 0x00 " regardless of the value written. mb91590 series mn705-00009-3v0-e 590
chapter 18: watchdog timer 4 . registers fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 9 4.3. watchdog timer 1 cycle information register : wdtc r1 (watchdog timer c ycle information register 1) the bit configuration of the w atchdog timer 1 c ycle information r egister ( wdtcr 1) is explained . this register conf igures each of the settings of watchdog timer 1. ? wdtcr1 : address 003e h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved wt[3:0] initial value 0 0 0 0 0 1 1 0 attribute r0,wx r0,wx r0,wx r0,wx r0,wx r1,wx r1,wx r0,wx this register cannot be rewriten. [b it7 to bit4] reserved "0" is always read. writing to it has no effect on operation . [bi t3 to bit 0] wt[3:0] (watchdog timer interval) : watchdog timer cycle selection these bits configure the number of cycles from when watchdog timer 1 was last cleared until watchdog reset 1 is issued. the cycle is fixed to 2 15 cycles. writing to these bits are ignored. wt[3:0] watchdog timer 1 cycle 0110 cr oscillator 2 15 cycles ( initial value, fixed ) mb91590 series mn705-00009-3v0-e 591
chapter 18: watchdog timer 4 . registers fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 10 4.4. watchdog timer 1 clear register : wdtcpr1 (watchdog timer clear pattern register 1) the bit configuration of the w atchdog timer 1 clear r egister ( wdtc pr 1) is explained . this register clears watchdog timer 1 (delays the issue of a reset). ? wdtcpr1 : address 003f h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cpat[7:0] initial value 0 0 0 0 0 0 0 0 attribute r0,w r0,w r0,w r0,w r0,w r0,w r0,w r0,w [b it7 to bit 0] cpat[7:0] (clear pattern) : watchdog timer 1 clear watchdog timer 1 activates after the reset is released. the watchdog timer is cleared after being activated by writing " 0x a5" . when a value other than " 0x a5" is written, the watchdog reset 1 is issued at that time. the value read out from this register is always " 0x00 " regardless of the value written . mb91590 series mn705-00009-3v0-e 592
chapter 18: watchdog timer 5 . operation fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 11 5. operation this section explains the operation of the w atchdog timer. this section explains the watchdog timer function. ? software watchdog function ? setup before activating watchdog timer 0, set bits 3 to 0: wt[3:0] of the wdtcr0 register to select the per iod from clearing the watchdog timer until the reset is issued. because watchdog timer 0 is only counted when the cpu is operating, set the period based on the number of program steps and the clock division setting. before activating watchdog timer 0, set bit6: rstp of the wdtcr0 register to select whether or not to generate a reset when a transition to watch mode or stop mode is detected. ? when rstp=0, the timer stops in watch mode or stop mode. ? when rstp=1, a reset is generated as soon as the cpu enters watch mode or stop mode. if you are usin g watch mode or stop mode, set rstp =0. writing to the rstp bits is ignored after watchdog timer 0 activates . ? starting watchdog timer 0 starts by the first write of any data to the wdtcpr0 register after reset . it does not matter what the write data is. the wdtcpr0 register always reads out " 0x00 " regardless of the data written. ? operation this section explains the operation of watchdog timer 0 after it has activated . counting conditions watchdog timer 0 counts the ris ing edges of the peripheral clock (pclk) while the cpu is operating. dma transfers do not effect the operation of the count. the count only stops while the cpu is stopped, such as in sleep mode. sampling of the cpu operating state is performed on the perip heral clock (pclk), with changes in the operating state within the peripheral clock cycle ignored. the count is stopped in emulator mode when the ice is connected. the count is also stopped if the watchdog reset suppression function is enabled in the debug interface functions while the ice is connected. in all of the above circumstances, because the counter is not cleared but is only paused when the count is stopped, when the count resumes the count continues from the counter value prior to the stop. becaus e the peripheral clock is stopped during the oscillat ion stabilization wait time of the source clock, the watchdog timer count also stops. mb91590 series mn705-00009-3v0-e 593
chapter 18: watchdog timer 5 . operation fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 12 clearing the timer once the watchdog timer has activated , the timer must be cleared before the timer period has elap sed. clearing the watchdog timer is performed by writing data to wdtcpr0. the write data must be the value with all bits inverted of the data previously written to wdtcpr0. when watchdog timer 0 is activated , for example, if it is activated by writing " 0x 55" to wdtcpr0, the timer is cleared subsequently by alternatingly writing " 0xaa " then " 0x 55" then " 0x aa " then " 0x 55". because the read value of wdtcpr0 is always " 0x00 " , the value written previously cannot be determined by reading wdtcpr0. storing the previ ously written value in a different location can be avoided by performing two consecutive writes when performing a single clear. reset request generation watchdog timer 0 generates a watchdog reset request under the following conditions. ? an overflow of the configured watchdog timer cycle occurs ? there is a transition to watch mode or to stop mode while stop mode detection reset is enabled ? a value other than the inverse value of the previous written value is written to the clear register ? hardware watchdog func tion ? setup bits 3 to bit 0: wt[3:0] of the wdtcr1 register of watchdog timer 1 is fixed in hardware. ? activating watchdog timer 1 activates immediately after the reset is released. ? operation this section explains the operation of watchdog timer 1 after it ha s activated . counting conditions watchdog timer 1 counts the rising edges of the cr oscillator. the count is stopped in emulator mode when the ice is connected. the count is also stopped if the watchdog reset suppression function is enabled in the debug in terface functions while the ice is connected. the count stops during sleep mode, watch mode, stop mode, and when waiting for the oscillator to stabilize when recovering from standby mode. clearing the timer once the watchdog timer has activated , the timer must be cleared before the timer period has elapsed. watchdog timer 1 is cleared by writing " 0x a5" to wdtcpr1. reset request generation watchdog timer 1 generates a watchdog reset request under the following conditions. ? an overflow of the watchdog timer cy cle occurs ? a value other than " 0x a5" is written to wdtcpr1 mb91590 series mn705-00009-3v0-e 594
chapter 18: watchdog timer 6 . usage example fujitsu semiconductor limited cha pter : watchdog timer fujitsu semiconductor confidential 13 6. usage example this section shows a usage example of the w atchdog timer. this example is provided for clearing the watchdog timer. figure 6-1 example of clearing the watchdog timers within pe r iodic create pe r iodic w atchdog timer clo c k settings boot ? per iodically clear w atchdog timer 1 du r ing the set time so that ? set w atchdog timer 0 . ? clear w atchdog 0 . ? clear w atchdog 1 . ? p er for m other processing as necessa ry. ( var ious calib r ation s , etc.) ? use the main time r , ppg, base time r , etc . to r un the pe r iodic inter r upt w atchdog reset (wdt1) does not appl y. ? w atchdog timer 1 is ena b led ev en if not configured . ser vice based on the time r. settings inter r upt se rvice inter r upt se rvice b y timer ? clear watchdog 0. ? clear watchdog 1. ? perform other processing as necessary. (various calibrations, etc.) ? use the main timer, ppg, base timer, etc. to run the periodic interrupt service based on the timer. ? set watchdog timer 0. ? watchdog timer 1 is enabled even if not configured. ? periodically clear watchdog timer 1 during the set time so that watchdog reset (wdt1) does not apply. mb91590 series mn705-00009-3v0-e 595
chapter 18: watchdog timer 6 . usage example fujitsu semiconductor limited chapter : watchdog timer fujitsu semiconductor confidential 14 mb91590 series mn705-00009-3v0-e 596
chapter 19: base timer 1 . overview fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 1 chapter : base timer this chapter explains the base timer. 1. overview 2. features 3. configuration 4. registers 5. operation code : 19_mb91590_hm_ _ basetim_0 10 _201111 28 mb91590 series mn705-00009-3v0-e 597
chapter 19: base timer 1 . overview fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 2 1. overview this section explains the overview of the base timer. this series includes the base timer for 2 channels. these base timers provide the following functions: ? 16/32 - bit reload timer ? 16- bit pwm timer ? 16- bit ppg timer ? 16/32 - bit pwc timer mb91590 series mn705-00009-3v0-e 598
chapter 19: base timer 2 . features fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 3 2. features this section explains features of the base timer. this series includes the base timer for 2 channels. each channel sele cts and uses appropriate ones of the following functions: 2.1 16/32 - bit reload timer 2.2 16 - bit pwm timer 2.3 16/32 - bit pwc timer 2.4 16 - bit ppg timer mb91590 series mn705-00009-3v0-e 599
chapter 19: base timer 2 . features fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 4 2.1. 16/32-bit reload timer this section explains the 16/32 - bit reload timer of the base timer. a base timer can be used as a 16/32 - bit reload t imer. the 16/32 - bit reload timer is a timer that decreases from a preset value. ? i/o mode you can select a signal (external clock, external activation trigger, waveform) i/o operation using the base timer i/o selection function. ? timer mode you can run multiple timers for individual channels and can combine 16 - bit reload timers for two channels into one 32 - bit reload timer. ? operation mode you can select one of the following two: ? reload mode: in this mode, when the down counter underflows, the preset value (cycle) is reloaded to allow the timer to restart counting. ? one - shot mode: once the down counter underflows, the counter will no longer count. ? count clock you can select one of five internal (peripheral) clocks and three external clocks (eck signals). ? int ernal clock (peripheral clock): clock obtained by dividing the frequency of the peripheral clock (pclk) by 1, 4, 16, 128, or 256. ? external clock (eck signal): rising edges, falling edges, or both edges are detected. ? activation trigger one of the following can be selected: ? software trigger ? external event: rising edge, falling edge, or both edges ? 16/32 - bit reload timer reactivation: the 16/32 - bit reload timer can be reactivated when an activation trigger is detected during counting. ? interrupt request an interrupt request can be generated in one of the following events: ? irq0: when an underflow occurs ? irq1: when a 16/32 - bit reload timer activation trigger is detected mb91590 series mn705-00009-3v0-e 600
chapter 19: base timer 2 . features fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 5 2.2. 16- bit pwm timer this section explains the 16- bit pwm timer of the base timer. the 16 - bit pwm timer, pwm standing for pulse width modulator timer , produces a desired waveform at an external pin when a duty ratio of the pulse width is specified. ? i/o mode you can select a signal (external clock, external activation trigger, waveform) i/o operation u sing the base timer i/o selection function. ? operation mode you can select one of the following two: ? reload mode: in this mode, when the 16 - bit down counter underflows, the preset cycle is reloaded to allow the timer to restart counting. ? one - shot mode: onc e the 16 - bit down counter underflows, the counter will no longer count. ? count clock you can select one of five internal (peripheral) clocks and three external clocks (eck signals). ? internal clock (peripheral clock): clock obtained by dividing the frequency of the peripheral clock (pclk) by 1, 4, 16, 128, or 256. ? external clock (eck signal): rising edges, falling edges, or both edges are detected. ? activation trigger one of the following can be selected: ? software trigger ? three external events: (rising edge, falling edge, or both edges detection) ? 16- bit pwm timer reactivation the 16 - bit pwm timer can be reactivated when an activation trigger is detected during counting. ? output waveform the output signal from the external pin can be fixed at the "l" or "h" l evel. ? interrupt request an interrupt request can be generated in one of the following events: ? irq0 : when an underflow occurs or counting is performed up to a preset value (duty) ? irq1 : when a 16 - bit pwm timer activation trigger is detected mb91590 series mn705-00009-3v0-e 601
chapter 19: base timer 2 . features fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 6 2.3. 16/32- bit pwc timer this section explains the overview of the 16/32 - bit pwc timer of the base timer. the 16/32 - bit pwc timer, pwc standing for pulse width counter, is used to measure pulse widths or cycles. ? i/o mode you can select a signal (waveform) i/o operation usin g the base timer i/o selection function. ? timer mode you can run multiple timers for individual channels and can combine 16 - bit pwc timers for two channels into one 32 - bit pwc timer. ? operation mode you can select one of the following two: ? single measureme nt mode: in this mode, measurement is conducted only once. ? continuous measurement mode: in this mode, after one sequence of measurement is conducted, the input of the next measurement start edge is awaited and the detection of the next measurement start ed ge triggers another sequence of measurement. ? count clock you can select one of the internal (peripheral) clocks obtained by dividing the frequency of the peripheral clock (pclk) by five types. ? clocks obtained by dividing the frequency of the peripheral clock (pclk) by 1, 4, 16, 128, and 256. ? measurement mode you can select one of the following five options relating to the pulse width and cycle to be measured : ? "h" pulse width: duration in which the input signal is maintained at the "h" level ? "l" pulse widt h: duration in which the input signal is maintained at the "l" level ? rising edge interval: period from the detection of a rising edge to the detection of the next rising edge ? falling edge interval: period from the detection of a falling edge to the detecti on of the next falling edge ? edge - to - edge pulse width: the width between consecutive input edges is one of the following: ? period from the detection of a rising edge to the detection of the falling edge ? period from the detection of a falling edge to the dete ction of the rising edge ? 16/32 - bit pwc timer reactivation the 16/32 - bit pwc timer can be reactivated when an activation trigger is detected during counting. ? interrupt request an interrupt request can be generated in one of the following events: ? irq0 : wh en an overflow occurs ? irq1 : when measurement ends mb91590 series mn705-00009-3v0-e 602
chapter 19: base timer 2 . features fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 7 2.4. 16- bit ppg timer this section explains the 16- bit ppg timer of the base timer. the 16 - bit ppg timer, ppg standing for programmable pulse generator timer , is a timer that generates a waveform with a desired pulse width. ? i/o mode you can select a signal (external clock, external activation trigger, waveform) i/o operation using the base timer i/o selection function. ? operation mode you can select one of the following two: ? reload mode: a sequence of "l" - level and "h" - level signals (consecutive pulses) is output. ? one - shot mode: a string of one "l" - level signal and one "h" - level signal (single pulses) is output. ? count clock you can select one of five internal (peripheral) clocks and three external clocks (eck s ignals). ? internal clock (peripheral clock): clock obtained by dividing the frequency of the peripheral clock (pclk) by 1, 4, 16, 128, or 256. ? external clock (eck signal): rising edges, falling edges, or both edges are detected. ? activation trigger one of t he following can be selected: ? software trigger ? three external events: (rising edge, falling edge, or both edges detection) ? 16- bit ppg timer reactivation the 16 - bit ppg timer can be reactivated when an activation trigger is detected during counting. ? inter rupt request an interrupt request can be generated in one of the following events: ? irq0 : when an underflow occurs based on the value of the base timer x h width setting reload register (btxprlh). ? irq1 : when a 16 - bit ppg timer activation trigger is detected . mb91590 series mn705-00009-3v0-e 603
chapter 19: base timer 3 . configuration fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 8 3. configuration this section explains the configuration of the base timer. figure 3-1 block diagram (overview) counter trigger logic interrupt logic registers counter trigger logic interrupt logic registers i/o selection register (btsel01) i/o selection logic interrupt irq0 : underflow/overflow/duty match irq1 : trigger/measurement completion interrupt interrupt irq0, irq1 bus access channel 0 channel 1 interrupt irq0, irq1 tioa 0 tioa1 (input for i/o mode1 and output or unused for other th an i/o mode 1) tiob0 tiob1 simultaneous software activation register (bt sssr) base timer mb91590 series mn705-00009-3v0-e 604
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 9 4. registers this section explains registers of the base timer. ? list of base addresses (base _ addr) and external pins table 4-1 table of base addresses (base_addr) and external pins ch annel number base address external pin 0 0x0080 tioa0, tioa1, tiob0, and tiob1 are assigned based on the btsel01 register setting. 1 0x0090 mb91590 series mn705-00009-3v0-e 605
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 10 ? registers map table 4-2 registers map address register s register fu nction +0 +1 +2 +3 0x0080 [common] bt0tmr [common] bt0tmcr [common] timer register 0 [common] control register 0 0x0084 reserved [reload timer] bt0stc [pwm] bt0stc [ppg] bt0stc [pwc] bt0stc reserved [reload timer] status control register 0 [ pwm] status control register 0 [ ppg] status control register 0 [ pwc] status control register 0 0x0088 [reload timer] bt0pcsr [ pwm] bt0pcsr [ppg] bt0prll [pwc] reserved [reload timer] reserved [pwm] bt0pdut [ppg] bt0prlh [pwc] bt0dtbf [reload timer] cycle setting register 0 [pwm] cycle setting register 0 [ppg] l width setting reload register 0 [pwm] duty setting register 0 [ppg] h width setting reload register 0 [pwc] data buffer register 0 0x008c reserved 0x0090 [common] bt1tmr [common] bt1tmcr [common] timer reg ister 1 [common] control register 1 0x0094 reserved [reload timer] bt1stc [pwm] bt1stc [ppg] bt1stc [pwc] bt1stc reserved [reload timer] status control register 1 [ pwm] status control register 1 [ ppg] status control register 1 [ pwc] status control registe r 1 0x0098 [reload timer] bt1pcsr [ pwm] bt1pcsr [ppg] bt1prll [pwc] reserved [reload timer] reserved [pwm] bt1pdut [ppg] bt1prlh [pwc] bt1dtbf [reload timer] cycle setting register 1 [pwm] cycle setting register 1 [ppg] l width setting reload register 1 [pwm] duty setting register 1 [ppg] h width setting reload register 1 [pwc] data buffer register 1 0x009c btsel01 reserved btsssr i/o selection register simultaneous software activation register mb91590 series mn705-00009-3v0-e 606
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 11 4.1. common registers this section explains the common registers of the base timer. the registers described here are common to various operations. mb91590 series mn705-00009-3v0-e 607
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 12 4.1.1. timer registers 0, 1 : btxtmr (base timer 0/1 timer register) t he bit configuration of t imer r egister s 0, 1 (btxtmr) is shown below . these registers are used to read the counter value on the timer. the registers are only valid when its content represents a reload, pwm, or ppg timer. the value read from the registers is undefined if a pwc timer is read. for information on the values that will be read, see the section of ope ration description. note : these registers must be accessed in 16 - bit mode. ? btxtmr : address base_addr + 00 h ( access: half - word) bit 15 bit 14 - - - bit 2 bit 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r,wx r,wx - - - r,wx r,wx r,wx mb91590 series mn705-00009-3v0-e 608
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 13 4.1.2. ti mer control registers 0, 1 : btxtmcr (base timer 0/1 timer control register) th e bit configuration of t imer c ontrol r egister s 0, 1 (btxtmcr) is shown below . these registers are used to variously configure and stop the base timer and to issue software trig gers. notes : ? if you need to change the fmd[2:0] setting, once reset it to fmd[2:0] = 000, and then set fmd[2:0] to the desired value. ? reserved bits must be set to "0". ? if you want to set bits of these register s except for the software trigger (strg) bit, p roceed as follows: 1. once stop operation by writing fmd[ 2:0] = 000 or cten = 0. 2. write desired values to the timer function selection bits (fmd[2:0]) and other bits. ? when writing to the software trigger bit (strg), be careful not to clear other bits. ? since fm d[2:0] = 000 specifies reset mode, you cannot set other bits when setting fmd[2:0] = 000. ? these registers must be accessed in 16 - bit mode. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxtmcr : address b ase_addr + 02 h ( access: half - word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved cks[2:0] [pwm - ppg] rtgen [others] reserved [pwm - ppg] pmsk [pwc] egs [2] [others] reserved egs[1:0] initial value 0 0 0 0 0 0 0 0 attribute r/w r0,wx(* 3) r/w r /w r/w r/w r0,wx(*1) r/w r0,wx(*1) r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 [reload timer - pwc] t32 [others] reserved fmd[2:0] [reload timer - pwm - ppg] osel [others] reserved mdse cten strg initial value 0 0 0 0 0 0 0 0 attribute r/w r0,wx (*1) r0,wx(*2) r/w r/w r/w r/w r/w0(*1) r/w r/w r0,w (*1) attribute assumed for "reserved" (*2) attribute assumed for a 32 - bit timer serving an odd - numbered channel (* 3) attribute assumed for a 32 - bit timer serving an odd - numbered channel or for a 16/32 -b it pwc timer mb91590 series mn705-00009-3v0-e 609
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 14 [b it15 ] reserved writing to this bit does not affect the operation. [b it14 to bit 12 ] cks[2:0] (clock select) : count clock selection bits select a count clock. c ks [2:0] description clock source description 000 internal clock (peripheral cl ock (pclk)) 1 division 001 4 division 010 16 division 011 128 division 100 256 division 101 [reload timer/pwm/ppg] external clock (eck signal) [ pwc] setting is prohibited rising edge 110 falling edge 111 both edges in the pwc mode, settings o f 101,110, and 111 are prohibited. [ pwm/ppg] [b it11 ] rtgen (restart by trigger enable) : restart enable bit if "1" is written to the strg bit or an external activation trigger (tgin signal ) is detected, this bit sets whether or not to recount the value of cycle setting register (btxpcsr)/l width setting reload register (btxprll) by reloading it to the 16 - bit down counter. rtgen description of operation 0 does not reactivate 1 reactivates [ pwm / ppg ] [b it10 ] pmsk (pulse mask) : pulse output mask bit select a level of waveform to output (tout signal) from the followings: ? normal output : output the waveform output from the 16 - bit pwm/ppg timer without modification. ? fixed output : output a sequence of "l" level or "h" level signals regardless of the settings of cycle or duty. pmsk description 0 normal output 1 fixed output if the fixed output is selected by writing "1" to this bit, the level being output will vary depending on the settings of the osel bit. ? if osel=0 : "l" level will be output. ? if osel=1 : "h" level will be output. mb91590 series mn705-00009-3v0-e 610
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 15 [reload timer/pwm/ppg] [b it9 , bit 8 ] egs[1:0] (edge select) : trigger input selection bit s select an effective edge for the external activation trigger (tgin) signal. egs[1:0] description 00 trigger input has no effe ct on the operation 01 rising edge 10 falling edge 11 both edges [pwc] [b it10 to bit 8] egs[2:0] (edge select) : measurement mode selection bits select a measurement mode. egs[2:0] description 000 "h" pulse width measurement: duration in which the inp ut signal is maintained at the "h" level 001 rising edge interval measurement: time from the detection of a rising edge to the detection of the next rising edge 010 falling edge interval measurement: time from the detection of a falling edge to the detec tion of the next falling edge 011 edge - to - edge pulse width measurement: the width between consecutive input edges is either:(1) or (2). (1) time from the detection of a rising edge to the detection of the falling edge (2) time from the detection of a fall ing edge to the detection of the rising edge 100 "l" pulse width measurement: duration in which the input signal is maintained at the "l" level(time from the detection of a falling edge to the detection of the rising edge) 101 110 111 setting is prohibit ed [reload timer/pwc] [b it7 ] t32 (timer 32bit) : 32- bit timer selection bit select whether to run the 16/32 - bit timer individually by each channel or use the two channels as 32 - bit timer through a cascade connection. set this bit for both channel 0 and c hannel 1. t32 ( channel 0) t32 ( channel 1) description 0 0 16 - bit timer independent operation respectively 0 1 setting is prohibited 1 0 32 - bit timer 1 1 setting is prohibited mb91590 series mn705-00009-3v0-e 611
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 16 note : change this bit after changing the fmd[2:0] to 000.(once you have changed the fmd[2:0] to 000, set the t32 bit and fmd[2:0] to a required value at the same time. ) [b it6 to bit 4] fmd[2:0] (function mode) : timer function selection bit s these bits are used to select a function of base timer. to change these bits, go to 000 (reset mode) first, and set it to another mode. fmd[2:0] description 000 reset mode (writing fmd = 000 will reverse the state of the base timer after the reset. each register will be reset to the initial value.) 001 16 - bit pwm timer 010 16 - bit ppg timer 011 16/32 - bit reload timer 100 16/32 - bit pwc t imer 101 110 111 setting is prohibited [b it3 ] osel (output select) : output polarity selection bit when this bit is set, the signal level (h/l) output from tout will be inverted. osel description 0 norma l output 1 inverted output [b it2 ] mdse (mode select) : mode selection bit [reload timer - pwm] mdse description 0 reload mode: when the down counter underflows, the value of the base timer x cycle setting register (btxpcsr) is reloaded to continue count ing. 1 one - shot mode: once the down counter underflows, the counter will no longer count. mb91590 series mn705-00009-3v0-e 612
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 17 [ppg] mdse description 0 reload mode: a sequence of "l" - level and "h" - level signals (consecutive pulses) is output. 1 one - shot mode: a string of one "l" - level si gnal and one "h" - level signal (single pulses) is output. [pwc] mdse description 0 continuous measurement mode: in this mode, after one sequence of measurement is conducted, the input of the next measurement start edge is awaited and the detection of the next measurement start edge triggers another sequence of measurement. 1 single measurement mode: in this mode, measurement is conducted only once. [b it1 ] cten (count enable) : counter operation enable bit enables/disables the counter operation. cten de scription 0 disables/stops the operation. 1 enables the operation. [b it0 ] strg (software trigger) : software trigger bit functions as a trigger for timer activation, etc. notes : ? when writing to this bit, be careful not to clear other bits. ? when writing to cten and fmd[2:0] simultaneously, issue a trigger as soon as the operation is enabled. strg description 0 ignores. 1 issues a trigger. mb91590 series mn705-00009-3v0-e 613
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 18 4.1.3. i/o selection register : btsel01 (base timer select register ch.0 and ch.1) t he bit configuration of the i/o s election r egister (btsel01) is shown below . these bits are used to set the i/o mode of ch.0 and ch.1 for the base timer. notes : ? these registers must be accessed in 8 - bit mode. ? these registers will not be initialized even if reset mode is set (writing of bt xtmcr : fmd = 000). ? btsel01 : address 009c h ( access: byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sel01[3:0] initial value 1 1 1 1 0 0 0 0 attribute r1,wx r1,wx r1,wx r1,wx r/w r/w r/w r/w [b it3 to bit 0] sel01[3:0] (select) : ch.0/ch.1 i/ o selection bits these bits are used to set the i/o mode of ch.0 and ch.1 for the base timer. sel01[3:0] description 0000 i/o mode 0 (16 - bit timer standard mode) 0001 i/o mode 1 (32 - bit timer full mode) 0010 i/o mode 2 (external trigger sharing mode) 0 011 setting is prohibited 0100 i/o mode 4 (timer activation/stop mode) 0101 i/o mode 5 (simultaneous software activation mode) 0110 i/o mode 6 (software activation timer activation/stop mode) 0111 i/o mode 7 (timer activation mode) 1xxx setting is pro hibited mb91590 series mn705-00009-3v0-e 614
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 19 4.1.4. simultaneous software activation register : btsssr (base timer software synchronous start register) t he bit configuration of the s imultaneous s oftware a ctivation r egister (btsssr) is shown below . th is register is the input signal in the i/o mod es 5 and 6. trigger can be generated simultaneously for all channels with this register. ? btsssr : address 009e h ( access: byte, half - word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 reserved initial value 1 1 1 1 1 1 1 1 attribute r1,wx r1,wx r1,w x r1,wx r1,wx r1,wx r1,wx r1,wx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sssr1 sssr0 initial value 1 1 1 1 1 1 1 1 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r1,w r1,w [b it1 ] sssr1 (software synchronous start register ch.1) : simultane o us software activation bit ch.1 [b it0 ] sssr0 (software synchronous start register ch.0) : simultaneous software activation bit ch.0 these bits are the input signal in the i/o modes 5 and 6. for the connections, see figure 5-2 . s ssr0/1 description 0 no effect on the operation . 1 "1" pulse to the timer input,then the corresponding channel is activated. mb91590 series mn705-00009-3v0-e 615
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 20 4.2. registers for 16/32- bit reload timer this section explains registers for 16/32 - bit reload timer. 4.2.1 . status control register s 0, 1 : btxstc (base timer 0/1 status control) 4.2.2 . cycle setting register s 0, 1 : btxpcsr (base timer 0/1 pulse counter start register) mb91590 series mn705-00009-3v0-e 616
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 21 4.2.1. st atus control registers 0, 1 : btxstc (base timer 0/1 status control) t he bit configuration of s tatus c ontrol r egister s 0, 1 (btxstc) is shown below . these registers control interrupt requests. notes : ? reserved bits must be set to "0". ? for the read - modify -w rite instruction to tgir and udir, "1" is read out. ? these registers must be accessed in 8 - bit mode. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxstc : address base_addr + 05 h ( access: byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tgie reserved udie reserved tgir reserved udir initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r/w r0,w0 r/w r0,w0 r(rm1),w r0,w0 r(rm1),w [ bit 6] tgie (trigger interrupt enable) : trigger interrupt request enabl e bit this bit sets whether or not to generate a trigger interrupt request when an activation trigger for 16/32 - bit reload timer has been detected (tgir = 1). [ bit 4] udie (underflow interrupt enable) : underflow interrupt request enable bit this bit sets w hether or not to generate an underflow interrupt request when the down counter underflows (udir = 1). tgie / udie description 0 disables 1 enables [ bit 2] tgir (trigger interrupt register) : trigger interrupt request flag bit this bit indicates that an activation trigger for the 16/32 - bit reload timer has been detected. when the tgie bit is set to "1" while this bit is "1", a trigger interrupt request will be generated. [ bit 0] udir (underflow interrupt register) : underflow interrupt request flag bit this bit indicates that the down counter value has changed from "0000 h " to "ffff h " and an underflow occurred. when this bit is "1" and the udie bit is set to "1", an underflow interrupt request is generated. tgir / udir read write 0 no trigger detection/underflo w occurred. this bit is cleared. 1 trigger detection/underflow occurred. no effect on the operation mb91590 series mn705-00009-3v0-e 617
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 22 4.2.2. cycle setting registers 0, 1 : btxpcsr (base timer 0/1 pulse counter start register) t he bit configuration of c ycle s etting r egister s 0, 1 (btxpcsr) is sh own below . these registers with a buffer set the cycle for 16/32 - bit reload timer. the down counter counts down from the value set to these registers. notes : ? these registers must be accessed in 16 - bit mode. ? set these registers after selecting a base timer function to the 16/32 - bit reload timer (fmd2 to fmd0 = 011) using the fmd2 to fmd0 bits of the timer control register (btxtmcr). ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxpcsr : address base_addr + 08 h ( access: half - word) bit 15 bit 14 - - - bit 2 bit 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r/w r/w - - - r/w r/w r/w [ bit 1 5 to bit 0] d[15:0] (data) : data bit s these registers with a buffer set the cycle for the 16/32 - bit reload timer. the down counter counts down from the value set to these registers. the value set to these registers is loaded to the 16 - bit down counter in the following cases: ? when the 16/32 - bit reload timer is started ? when the down counter underflows the follo wing values are set to these registers when two channels of a 16 - bit reload timer are cascaded and it is used as the 32 - bit reload timer. ? value of even - number channel cycle setting register (btxpcsr) : value of lower 16 - bit ? value of the odd - number channe l cycle setting register (btxpcsr) : value of upper 16 - bit for this reason, in the 32 - bit timer mode, write values into these registers in the following order. 1. odd - number channel base timer x cycle setting register (btxpcsr) 2. even - number channel base timer x cycle setting register (btxpcsr) mb91590 series mn705-00009-3v0-e 618
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 23 4.3. registers for 16 - bit pwm timer this section explains registers for 16 - bit pwm timer. 4.3.1 . status control register s 0, 1 : btxstc (base timer 0/1 status control) 4.3.2 . cycle setting register s 0, 1 : btxpcsr (base timer 0/1 pulse counter start register) 4.3.3 . duty setting registers 0, 1 : btxpdut (base t imer 0/1 pulse duty register) mb91590 series mn705-00009-3v0-e 619
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 24 4.3.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) t he bit configuration of s tatus c ontrol r egiste rs 0, 1 (btxstc) is s hown below . these registers control interrupt requests. notes : ? reserved bits must be set to "0". ? for the read - modify - write instruction to tgir, dtir, and udir, "1" is read out. ? these registers must be accessed in 8 - bit mode. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxstc : addres s base_addr + 05 h ( access: byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tgie dtie udie reserved tgir dtir udir initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r/w r/w r/w r0,w0 r(rm1),w r(rm1),w r(rm1),w [ bit 6] tgie (trigger interrupt enabl e) : trigger interrupt request enable bit this bit sets whether or not to generate a trigger interrupt request when a 16 - bit pwm timer activation trigger is detected (tgir = 1). [ bit 5] dtie (duty interrupt enable) : duty match interrupt request enable bit this bit sets whether or not to generate a duty match interrupt request when the value of the 16 - bit down counter matches the value of the base timer x duty setting register (btxpdut) (dtir = 1). [ bit 4] udie (underflow interrupt enable) : underflow interrupt request enable bit this bit sets whether or not to generate an underflow interrupt request when the down counter underflows (udir = 1). tgie / dtie / udie description 0 disables. 1 enables. [ bit 2] tgir (trigger interrupt register) : trigger interrupt request flag bit this bit indicates that a 16 - bit pwm timer activation trigger is detected. when this bit is "1" and the tgie bit is set to "1", a trigger interrupt request is generated. [ bit 1] dtir (duty interrupt register) : duty match interrupt request fl ag bit this bit indicates that the value of the 16 - bit down counter matches the value of the duty setting register (btxpdut) (a duty matches). when this bit is "1" and the dtie bit is set to "1", a duty match interrupt request is generated. [ bit 0] udir (un derflow interrupt register) : underflow interrupt request flag bit this bit indicates that the 16 - bit down counter value changed from "0000 h " to "ffff h " and an underflow occurred. when this bit is "1" and the udie bit is set to "1", an underflow interrupt request is generated. mb91590 series mn705-00009-3v0-e 620
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 25 tgir / dti r / udir read write 0 a trigger detection, duty match and underflow did not occur. this bit is cleared. 1 a trigger detection, duty match or underflow occurred. no effect on the operation . mb91590 series mn705-00009-3v0-e 621
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 26 4.3.2. cycle setting registers 0, 1 : btx pcsr (base timer 0/1 pulse counter start register) t he bit configuration of c ycle s etting r egister s 0, 1 (btxpcsr) is shown below . these registers with a buffer set the cycle for the 16 - bit pwm timer. the 16 - bit down counter counts down from the value set to these registers. when the counter value matches the value set to these registers, the level of the output signal (tout ) is inverted. notes : ? these registers must be accessed in 16 - bit mode. ? set these registers after selecting a base timer function to the 16 - bit pwm timer using the fmd2 to fmd0 bits of the timer control register (btxtmcr). ? be sure to rewrite the duty setting register (btxpdut) when these registers are rewritten. ? do not set a value smaller than the value set to the duty setting register (btxpdut). ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxpcsr : address base_addr + 08 h ( access: half - word) bit 15 bit 14 - - - bit 2 bit 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r/w r/w - - - r/w r/w r/w [ bit 1 5 to bit 0] d[15:0] (data) : data bit s these registers with a buffer set the cycle for the 16 - bit pwm timer. the 16 - bit down counter counts down from the value set to these registers. when the counter value matches the value set to these registers, the level of the output signal (tout) is inverted. these registers have a buffer and thus can be rewritten during counting. the value set to these registers is loaded to the 16 - bit down counter in the following cases: ? when the 16 - bit pwm timer is activated ? when the down counter underflows when the same value is set to these registers and the base timer x duty setting register (btxpdut), the level of the output signal (tout) can be fixed. the output signal level is as follows according to the setting of the osel bit of the base timer x timer control register (btxtmcr): ? osel=0: "h" level ? osel=1: "l" level mb91590 series mn705-00009-3v0-e 622
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 27 4.3.3. duty setting register s 0, 1 : btxpdut (base timer 0/1 pulse duty register) t he bit configuration of duty setting register s 0, 1 (btx pdut) is sh own below . these registers with a buffer set the duty for the 16 - bit pwm timer. when the 16 - bit down counter value matches the value set to these registers, the level of the output signal (tout) is inverted. notes : ? these registers must be accessed in 16 - bit mode. ? set these registers after selecting a base timer function to the 16 - bit pwm timer using the fmd2 to fmd0 bits of the timer control register (btxtmcr). ? do not set the value higher than the value set to the cycle setting register (btxpcsr) when these registers are rewritten. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxpdut : address base_addr + 0a h ( access: half - word) bit 15 bit 14 - - - bit 2 bt 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r/w r/w - - - r/w r/w r/w [ bit 1 5 to bit 0] d[15:0] (data) : data bit s these registers with a buffer set the duty for the 16 - bit pwm timer. when the 16 - bit down counter value matches the value set to these registers, the level of the output signal (tout) is inverted. these registers have a buffer and thus can be rewritten during counting. if the 16 - bit down counter underflows, the buffer value will be transferred. when the same value is set to these registers and the base timer x cycle setting register (btxpcsr), the level of the output signal (tout) can be fixed. the output signal level is as follows according to the setting of the osel bit of the base timer x timer control register (btxtmcr): ? osel=0: all "h" level ? osel=1: all "l" leve l mb91590 series mn705-00009-3v0-e 623
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 28 4.4. registers for 16 - bit ppg timer this section explains registers for 16 - bit ppg timer. 4.4.1 . status control register s 0, 1 : btxstc (base timer 0/1 status control) 4.4.2 . l width setting register s 0, 1 : btxprll (base timer 0/1 pulse length of "l" register) 4.4.3 . h width setting register s 0, 1 : btxprlh (base timer 0/1 pulse length of "h" register) mb91590 series mn705-00009-3v0-e 624
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 29 4.4.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) t he bit configuration of s tatus c ontrol r egister s 0, 1 (btxstc) is shown below . these registers control interrupt requests. notes : ? reserved bits must be set to ?0?. ? for th e read - modify - write instruction to tgir and udir, "1" is read out. ? these registers must be accessed in 8 - bit mode. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxstc : address base_addr + 05 h ( access: b yte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved tgie reserved udie reserved tgir reserved udir initial value 0 0 0 0 0 0 0 0 attribute r0,w0 r/w r0,w0 r/w r0,w0 r(rm1),w r0,w0 r(rm1),w [ bit 6] tgie (trigger interrupt enable) : trigger interrupt request enable bit this bit sets whether or not to generate a trigger interrupt request when a 16 - bit ppg timer activation trigger is detected (tgir = 1). [ bit 4] udie (underflow interrupt enable) : underflow interrupt request enable bit this bit sets whe ther or not to generate an underflow interrupt request when the base timer x h width setting reload register (btxprlh) completed counting down and the counter underflows (udir = 1). tgie / udie description 0 disable d . 1 enable d . [ bit 2] tgir (trigger inte rrupt register) : trigger interrupt request flag bit this bit indicates that a 16 - bit ppg timer activation trigger is detected. when this bit is "1" and the tgie bit is set to "1", a trigger interrupt request is generated. [ bit 0] udir (underflow interrupt register) : underflow interrupt request flag bit this bit indicates that the base timer x h width setting reload register (btxprlh) completed counting down and an underflow occurred. an underflow will occur if the register attempts counting down when the 1 6- bit down counter value is "0000 h ". when this bit is "1" and the udie bit is set to "1", an underflow interrupt request is generated. tgir / udir read write 0 no trigger detection/underflow occurred. this bit is cleared. 1 trigger detection/underflow occu rred. no effect on the operation . mb91590 series mn705-00009-3v0-e 625
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 30 4.4.2. l width setting register s 0, 1 : btxprll (base timer 0/1 pulse length of "l" register) t he bit configuration of l w idth s etting r egister s 0, 1 (btxprll) is shown below . these registers set the default level for the signal output from the 16 - bit ppg timer. notes : ? these registers must be accessed in 16 - bit mode. ? set these registers after selecting a base timer function to the ppg timer using the fmd2 to fmd0 bits of the timer control register (btxtmcr). ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxprll : address base_addr + 08 h ( access: half - word) bit 15 bit 14 - - - bit 2 bit 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r/w r/w - - - r/w r/w r/w [ bit 1 5 to bit 0] d[15:0] (data) : data bit s these registers set the default level for the signal output from the 16 - bit ppg timer. when the 16 - bit down counter completes counting down the value set to these registers, the level of the output waveform (tout) will be inverted. setting these registers and the base timer x h width setting reload register (btxprlh) determines the widths of "l" level and "h" level for the output signal. the signal level width set to these registers depends on the setting of the osel bi t of the timer control register (btxtmcr) as follows: ? osel=0: "l" level width ? osel=1: "h" level width the value set to registers is loaded to the 16 - bit down counter when a 16 - bit ppg timer activation trigger is detected or when the base timer x h width setting reload register (btxprlh) completed counting values and underflows. mb91590 series mn705-00009-3v0-e 626
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 31 4.4.3. h width setting registers 0, 1 : btxprlh (base timer 0/1 pulse length of "h" register) t he bit configuration of h w idth s etting r egister s 0, 1 (btxprlh) is shown below . these registers with a buffer set the width of signal level output when the base timer x l width setting reload register (btxprll) completes counting values. notes : ? these registers must be accessed in 16 - bit mode. ? set these registers after selecting a base timer function to the ppg timer using the fmd2 to fmd0 bits of the timer control register (btxtmcr). ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxprlh : address base_addr + 0a h ( access: half - word) bit 15 bit 14 - - - bit 2 bit 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r/w r/w - - - r/w r/w r/w [ bit 1 5 to bit 0] d[15:0] (data) : data bit s these registers with a buffer set the width of signal level output when the l width setting reload register (btxprll) completes counting values. when the 16 - bit down counter completes counting down the value set to these registers, the signal level of the output waveform (tout) will be inverted. setting these registers and the base timer x l width setting reloa d register (btxprll) determines the widths of "l" level and "h" level for the output signal. the signal level width set to these registers depends on the setting of the osel bit of the base timer x timer control register (btxtmcr) as follows: ? osel = 0: "h" level width ? osel = 1: "l" level width these registers have a buffer and thus can be rewritten during counting. these registers transfer values at the following timing. ? transfer to the buffer ? when a 16 - bit ppg timer activation trigger is detected ? when the base timer x h width setting reload register (btxprlh) completes counting down values and underflows ? transfer to the 16 - bit down counter ? when counting down from the value of the base timer x l width setting reload register (btxprll) is completed. for rew riting timing, see " ? write timing " in " 5.6.3 operation in reload mode ". mb91590 series mn705-00009-3v0-e 627
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 32 4.5. 16/32-bit pwc timer register this section explains regist ers for 16/32 - bit pwc timer. 4.5.1 . status control registers 0, 1 : btxstc (base timer 0/1 status control) 4.5.2 . data buffer register s 0, 1 : b txdtbf (base timer 0/1 data buffer register) mb91590 series mn705-00009-3v0-e 628
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 33 4.5.1. status control registers 0, 1 : btxstc (base timer 0/1 status control) t he bit configuration of s tatus c ontrol r egister s 0, 1 (btxstc) is s hown below . these registers control interrupt requests. notes : ? reser ved bits must be set to "0". ? for the read - modify - write instruction to ovir, "1" is read out. ? these registers must be accessed in 8 - bit mode. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd= 000). ? btxstc : address b ase_addr + 05 h ( access: byte) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 err edie reserved ovie reserved edir reserved ovir initial value 0 0 0 0 0 0 0 0 attribute r,w0 r/w r0,w0 r/w r0,w0 r,wx r0,w0 r(rm1), w [ bit 7] err (error) : error flag bit this b it indicates that the next measurement is completed before the measurement result is read from the data buffer register (btxdtbf) in the continuous measurement mode and the measurement result has been overwritten by the new value. the old value is discarde d. this bit is cleared to "0" when a value is read from the data buffer register (btxdtbf). err description 0 the measurement result has not been overwritten. 1 the measurement result has been overwritten. [ bit 6] edie (end interrupt enable) : measureme nt completion interrupt request enable bit this bit sets whether or not to generate a measurement completion interrupt request when the measurement of the 16/32 - bit pwc timer is completed (edir = 1). [ bit 4] ovie (overflow interrupt enable) : overflow interrupt request enable bit this bit sets whether or not to generate an overflow interrupt request when the up counter overflows (ovir = 1). edie / ovie description 0 disable d 1 enable d mb91590 series mn705-00009-3v0-e 629
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 34 [ bit 2] edir (end interrupt register) : measurement completion interrupt request flag bit this bit indicates that the measurement of the 16/32 - bit pwc timer is completed. when this bit is "1" and the edie bit is set to "1", a measurement completion interrupt request is generated. this bit is cleared when the measurement result (btxdtbf) is read out. [ bit 0] ovir (overflow interrupt register) : overflow interrupt request flag bit this bit indicates that the up counter value has changed from "ffff h " to "0000 h " and an overflow occurred. when this bit is "1" and the ovie bit is set to "1", an overflow interrupt request is generated. this bit is cleared when "0" is written. edir / ovir read write 0 measurement completion/overflow has not been occurred. (edir) no effect on the operation . (ovir) this bit is cleared. 1 measurement comple tion/overflow has been occurred. no effect on the operation . mb91590 series mn705-00009-3v0-e 630
chapter 19: base timer 4 . registers fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 35 4.5.2. data buffer registers 0, 1 : btxdtbf (base timer 0/1 data buffer register) t he bit configuration of d ata b uffer r egister s 0, 1 (btxdtbf) is sho wn below . these registers are used to read out t he measurement value of the 16/32 - bit pwc timer and the up counter value. notes : ? these registers must be accessed in 16 - bit mode. ? these registers will also be initialized when reset mode is set (writing of btxtmcr : fmd = 000). ? btxdtbf : address base_addr + 0a h ( access: half - word) bit 15 bit 14 - - - bit 2 bit 1 bit 0 d[15:0] initial value 0 0 - - - 0 0 0 attribute r,wx r,wx - - - r,wx r,wx r,wx [ bit 1 5 to bit 0] d[15:0] (data) : data bit s these registers are used to read out the measurement value of th e 16/32 - bit pwc timer and the up counter value. the value read from these registers is different in the single measurement mode and continuous measurement mode. ? single measurement mode: the up counter value is read during counting and the measurement resul t is read after the measurement completion. ? continuous measurement mode: the value measured previously is read both during counting and after the measurement completion. the up counter value cannot be read. the following values are set to these registers when two channels of a 16 - bit pwc timer are cascaded and it is used as the 32 - bit pwc timer. ? value of even - number channel data buffer register (btxdtbf): value of lower 16 - bit ? value of odd - number channel data buffer register (btxdtbf): value of upper 16- bi t in the 32 - bit timer mode, read these registers value in the following order. 1. even - channel data buffer register (btxdtbf) 2. odd - channel data buffer register (btxdtbf) mb91590 series mn705-00009-3v0-e 631
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 36 5. operation this section explains the o peration of the base timer. 5.1 . selection of timer function 5.2 . i/o allocation 5.3 . 32- bit mode operation 5.4 . 16/32 - bit reload timer operation 5.5 . 16- bit pwm timer operation 5.6 . 16- bit ppg timer operation 5.7 . 16/32 - bit pwc timer operation mb91590 series mn705-00009-3v0-e 632
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 37 5.1. selection of timer function this section explains selection of the timer function. select the timer function for btxtmcr : fmd[2:0]. mb91590 series mn705-00009-3v0-e 633
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 38 5.2. i/o allocation this section explains i/o allocation. set i/ o of the base timer for the btsel01 register before using the timer. you can select one of the following seven: ? i/o mode 0 16- bit timer standard mode the base timer operates separately for each channel in this mode. ? i/o mode 1 32- bit timer full mode the even - number channel signals of the base timer are allocated to the external pin in this mode. ? i/o mode 2 external trigger sharing mode the external activation trigger can be input to two channels of base timer at the same time in this mode. using this mod e allows simultaneous activation of two channels of base timer. ? i/o mode 4 timer activation/stop mode activation/stop of the odd - number channel is controlled by the even - number channel in this mode. the odd- number channel is started with the rising edge(*) of the output signal from the even - number channel and stops with the falling edge(*). ? i/o mode 5 simultaneous software activation mode more than one channels are started by the software at the same time in this mode. ? i/o mode 6 software activation time r activation/stop mode activation/stop of the odd - number channel is controlled by the even - number channel in this mode. the even - number channel is started by the software. the odd - number channel is started with the rising edge(*) of the output signal from the even - number channel and stops with the falling edge(*). ? i/o mode 7 timer activation mode activation of the odd - number channel is controlled by the even - number channel in this mode. the odd- number channel is started with the rising edge(*) of the output signal from the even - number channel. (*): make a setting using the trigger input selection bit (btxtmcr : egs). mb91590 series mn705-00009-3v0-e 634
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 39 figure 5-1 wiring diagram of each i/o mode (1) tiobn tioan tiobm tioam ch. n ch. m eck tgin tin tout eck tgin tin tout tiobn tioan tiobm tioam ch. n ch. m eck tgin tin tout tiob n ti o an tiob m ti o am ch.n ch.m e ck tgin t in to ut e ck tgin t in to ut cou t tiob n ti o an tiob m ti o am ch.n ch.m e ck tgin t in to ut dtrg e ck tgin t in to ut cou t blo c k dia gram f or i/o mode 0 (16-bit timer standard mode) base timer base timer base timer base timer base timer base timer base timer base timer blo c k dia gram f or i/o mode 1 (32-bit timer full mode) blo c k dia gram f or i/o mode 2 (exte r nal t r igger sha r ing mode) blo c k dia gram f or i/o mode 4 (timer acti v ation/stop mode) m:ch.0 n:ch.1 mb91590 series mn705-00009-3v0-e 635
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 40 figure 5-2 wiring diagram of each i/o mode ( 2) tiob n ti o an tiob m ti o am ch. n ch. m ec k tgin t in to ut ec k tgin t in to ut cou t block diagram for i/o mode 5 (simultaneous software activation mode) block diagram for i/o mode 6 (software activation timer activation/stop mode) block diagram for i/o mode 7 (timer activation mode) tiob n ti o an tiob m ti o am ch. n ch. m eck tgin tin to ut eck base timer base timer tgin tin to ut software activation signal (sssrn bit) software activation signal (sssrm bit) tiob n ti o an tiob m ti o am ch. n ch. m eck tg in tin to ut dt rg eck tg in tin to ut cou t software activation signal (sssrm bit) base timer base timer base timer base timer m:ch.0 n:ch.1 mb91590 series mn705-00009-3v0-e 636
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 41 5.3. 32- bit mode operation this section explains the 32- bit mode operation. the reload timer and pwc timer can be operated in the 32 - bit mode using two channels. the basic function/operation in the 32 - bit mode is shown below. mb91590 series mn705-00009-3v0-e 637
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 42 5.3.1. 32- bit mode function this section explains the 32- bit mode function. this fun ction realizes the operation of the 32 - bit data reload timer or 32 - bit data pwc timer by combining two channels of base timer. the upper 16 - bit timer counter value of the odd - number channel is also loaded when the lower 16 - bit timer counter value of the ev en - number channel is read. thus, the timer counter value in operation can also be read. mb91590 series mn705-00009-3v0-e 638
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 43 5.3.2. 32- bit mode setting this section explains the 32- bit mode setting. first, set "000" to the fmd bit s of the btxtmcr register of the even - number channel to reset to the reset mode, then select the reload timer or pwc timer and set the operation as in the 16 - bit mode. while doing so, set to the 32 - bit mode by writing "1" to the t32 bit of the btxtmcr register. leave the t32 bit of the odd- number channel "0". you do not hav e to set the reset mode. for the reload timer, set the upper 16 - bit reload values of the 32- bit to the cycle setting register of the odd - number channel, then set the lower 16 - bit reload values to the cycle setting register of the even - number channel. the t ransition to the 32 - bit mode is reflected immediately after the writing to the t32 bit. thus, setting change for both channels must be done when the counting is stopped. to transit from the 32 - bit mode to the 16 - bit mode, set "000" to the fmd bit s of the b txtmcr register of the even - number channel to reset t o the reset mode for both the even - number and odd - number channels, and make a setting in the 16 - bit mode for each channel. mb91590 series mn705-00009-3v0-e 639
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 44 5.3.3. 32- bit mode operation this section explains 32 - bit mode operation. after settin g the 32 - bit mode when the reload timer or pwc timer is started with the control of the even - number channel, the timer/counter of the even - number channel operates with lower 16 - bit and the timer/counter of the odd - number channel operates with upper 16- bit. the 32 - bit mode operation depends on the setting of the even - number channel. thus, the setting of the odd- number channel (excepting the cycle setting register for the reload timer) is ignored. timer activation, waveform output and interrupt signal also ap ply the setting of the even - number channel. (the odd - number channel is masked with the value fixed to l.) for the configuration, see figure 5- 11 and figure 5- 28 . mb91590 series mn705-00009-3v0-e 640
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 45 5.4. 16/32-bit reload timer operation this sec tion explains the 16/32 - bit reload timer operation. this section explains the operation performed when the base timer included in this series is used as the 16/32 - bit reload timer. an example is also given to set various operation conditions. figure 5-3 block diagram (1 6- bit reload timer operation) btxpcs r 16-bit mode t3 2=0 ck s eg s 2 3 2 0 2 7 2 8 str g cten cte n m ds e 16 bt xtmr t3 2 o se l udie tg ie ir q0 ir q1 edg e dete ction btxpcsr : base timer x cycle set t ing r egist er (btxpcsr) btxt mr : bas e timer x timer r egi ster (b txtmr ) external activati on edg e ( tgi n signal) output waveform (t out signal) inver t control t oggle gene r ation division circuit edg e dete ction per iphe r al clo ck load count clock external clock (eck signal) down counter underflow count enabled count enabled underflow trigger tr igger timer enabled generation ( pc l k) interrupt request interrupt request interrupt source mb91590 series mn705-00009-3v0-e 641
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 46 figure 5-4 block diagram (32 - bit reload timer operation) bt0pcsr 32-bit mode t3 2=1 ck s pcl k eg s 2 3 2 0 2 7 2 8 str g cte n cte n mds e 16 bt 0t mr t3 2 o se l udie tg ie ch.0 ch.1 bt1t mr ) bt1pcsr t3 2= 0 16 ir q0 ir q1 edge dete cti on bt1 pcsr : bas e timer 1 cycle se tt ing r e gi s te r (bt1 pcsr ) bt 1t mr : ba se timer 1 timer re gi ster (b t1tm r) bt0 pcsr : bas e timer 0 cycle se tt ing r e gi s te r (bt0 pcsr ) bt 0t mr : ba se timer 0 timer re gi ster (b t0tm r) load count clock down counter underflow enabled count count clock load down counter underflow count output waveform (tout signal) invert control toggle division edge dete cti on peripheral clock external clock (eck signal) external activation interrupt trigger trigger timer enabled underflow count circuit trigger (tgin signal) enabled enabled generation source generation interrupt request interrupt request mb91590 series mn705-00009-3v0-e 642
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 47 5.4.1. overview t his section explains the o verview of the 16/32 - bit r eload t imer o peration . the 16/32 - bit reload timer is a timer that decreases from the value set in the base timer x cycle setting register (btxpcsr). this timer has a function of generating an underflow interrupt request when the down counter underflows. the 16/32 - bit reload timer has two modes: timer mode and operation mode. the operation of the timer varies in accordance with combinations of these modes. ? timer mode: one of the following two modes can be selected using the t3 2 bit of the base timer x timer control register (btxtmcr). ? 16- bit timer mode (t32 = 0): 16 - bit reload timer can operate individually for each of the channels. ? 32- bit timer mode (t32 = 1): 2 channels can be cascaded and used as a 32 - bit reload timer. ? opera tion mode: one of the following two modes can be selected using the mdse bit of the base timer x timer control register (btxtmcr). ? reload mode (mdse = 0): in this mode, when the down counter underflows, the preset value (cycle) is reloaded to allow the tim er to restart counting. ? one - shot mode (mdse = 1): once the down counter underflows, the counter will no longer count. mb91590 series mn705-00009-3v0-e 643
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 48 5.4.2. operation in reload mode t his section explains the o peration in r eload m ode . this section explains the operation in reload mode. ? overvie w in this mode, the value set in the base timer x cycle setting register (btxpcsr) is reloaded every time an underflow occurs to ensure that countdown is continued. to use this mode, set reload mode by resetting the mdse bit of the base timer x timer contr ol register (btxtmcr) to "0" (mdse=0) . ? operation ? activation activate the 16/32 - bit reload timer with the following procedure: 1. permit 16/32 - bit reload timer operation by setting the cten bit of the base timer x timer control register (btxtmcr) to "1" (cten= 1) . the 16/32 - bit reload timer begins to wait for an activation trigger. 2. enter an activation trigger by one of the following methods: ? set the strg bit of the base timer x timer control register (btxtmcr) to "1" (software trigger). ? enter an effective edge (an edge set in the egs1 and egs0 bits) for an external activation trigger (tgin signal). notes : ? the external activation trigger (tgin signal) entry method varies depending on the i/o mode specified by the i/o selection register (btsel01). see " 5.2 i/o allocation ". ? to start counting as soon as the operation is permitted, set both cten and strg bits of the base timer x timer control register (btxtmcr) to "1". counting operation when an activation trigge r is input, the value (cycle) set in the base timer x cycle setting register (btxpcsr) is loaded to the down counter, which begins counting down, after one of the following lengths of time elapses: ? if a software trigger is input: 1t (t: count clock cycle) ? if an external activation trigger (tgin signal) is input: 2t to 3t (t: count clock cycle) mb91590 series mn705-00009-3v0-e 644
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 49 figure 5 - 5 and figure 5- 6 show t he count start timing . figure 5-5 count start timing (software trigger) figure 5-6 count start timing (external activation trigger (tgin signal), effective edge = rising edge) note : the external activation trigger (tgin signal) entry method varies depending on the i/o mode specified by the i/o selection register (btsel01). see " 5.2 i/o allocation ". when the down counter underflows after attempting to count down further from the value of "0000 h ", the value (cycle) set in the base timer x cycle setting register (btxpcsr) is reloaded to the down counter, which continues to count down. if an underflow occurs, the udir bit of the base timer x status control register (btxstc) changes to "1". at this time, an underflow interrupt request occurs if the udie bit is set to "1". figure 5- 7 shows the operation in case of an underflow. figure 5-7 operation in case of an underflow 0000 h 2 t to 3t (external trigger) load count clock reload value counter value exte r nal acti v ation -1 -1 tr igger xxx x h cten bit strg bit 1 t load count clock reload value counter value - 1 - 1 000 h ud ir load count clock counter value underflow reload value - - mb91590 series mn705-00009-3v0-e 645
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 50 ? output waveform the waveform (tout signal) of the 16/32 - bit reload timer can be output. the waveform (tout signal) to be output varies according to the setting of the osel bit of the base timer x timer control register (btxtmcr). table 5-1 correspondence between output polarities and output waveforms output polarity output waveform normal polarity (osel = 0) "l" level pulse i s output when counting starts. thereafter, the output level is inverted every time an underflow occurs. inverted polarity (osel = 1) "h" level pulse is output when counting starts. thereafter, the output level is inverted every time an underflow occurs. figure 5 - 8 shows the output waveform in reload mode. figure 5-8 output waveform in reload mode (normal polarity) ti o a0 , tioa1 pins cten bit opposite (inversion) level when osel=1 activation trigger under flow mb91590 series mn705-00009-3v0-e 646
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 51 5.4.3. operation in one - shot mode this section explains the operation in one - shot mode. this section explains the operation in one -s hot mode. ? overview in this mode, the counter will no longer count down once an underflow occurs. to use this mode, set one - shot mode by setting the mdse bit of the base timer x timer control register (btxtmcr) to "1" (mdse=1) . ? operation ? activation the sa me operation as in reload mode. see " overview " in " 5.4.2 operation in reload mode ". ? counting operation the operation is the same as in reload mode until an underflow occurs. see " overv iew ". when the down counter underflows, the value (cycle) set in the base timer x cycle setting register (btxpcsr) is reloaded to the down counter. however, the down counter stops counting. if an underflow occurs, the udir bit of the base timer x status c ontrol register (btxstc) changes to "1". at this time, an underflow interrupt request occurs if the udie bit of the base timer x status control register (btxstc) is set to "1". figure 5 - 9 shows the operation in case of an underflow. figure 5-9 operation in case of an underflow ? output waveform the waveform (tout signal) of the 16/32 - bit reload timer can be output. the waveform (tout signal) to be output varies according to the setting of the osel bit of the base timer x timer control register (btxtmcr). table 5 - 2 shows the correspondence between output polarities and output waveforms. table 5-2 correspondence between output polarities and output waveforms output polarity output waveform normal polarity (osel = 0) when an activation trigger is input (counting in progress), "h" level pulse is output. "l" level pulse is output while the timer waits for an activation trig ger. inverted polarity (osel = 1) when an activation trigger is input (counting in progress), "l" level pulse is output. "h" level pulse is output while the timer waits for an activation trigger. 0000 h udir load count clock counter value underflow reload value - 1 - 1 mb91590 series mn705-00009-3v0-e 647
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 52 figure 5 - 10 shows the output waveform in one - shot mode. figure 5- 10 output waveform in one - shot mode (normal polarity) ti o a0 , tioa1 pins cten bit underflow opposite (inversion) level when osel=1 waiting for activation trigger activation trigger mb91590 series mn705-00009-3v0-e 648
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 53 5.4.4. 32- bit timer mode operation this section explains the 32- bit t imer m ode o peration . this section explains the setting and operation for cascading 2 channels of a 16 - bit reload timer and using them as a 32 - bit reload timer. ? overview using the t32 bit of the base timer x timer control register (btxtmcr), 2 channels of a 16 - bit reload timer can be cascaded and used as a 32 - bit reload timer. in this mode, the even - numbered channel corresponds to the lower 16 - bit operation, and the odd - numbered channel corresponds to the upper 16 - bit operation. therefore, set the reload values in the order of the upper 16 bits (odd - number channel s) the lower 16 bits (even - number channels) and read the down counter values in the order of the lower 16 bits (even - number channels) the upper 16 bits (odd - number channels). ? setting procedure (example) to set 32 - bit timer mode, set the t32 bit of the base timer x timer control register (btxtmcr) of even - number channels to "1" and the t32 bit of the base timer x timer control register (btxtmcr) of the odd- number channels to "0". when setting 32 - bit timer mode, set the registers using the procedure show n below. different register settings should be used between even - number and odd - number channels. the following shows an example of using a cascade connection. 1. specify ch.0 to reset mode by setting fmd2 to fmd0 bits of base timer 0 timer control register (b t0tmcr). (fmd2 to fmd0 = 000) 2. select 16/32 - bit reload timer for ch.0 and ch.1 by setting the fmd2 to fmd0 bits of the base timer x timer control register (bt0tmcr, bt1tmcr) of ch.0 and ch.1. (fmd2 to fmd0 = 011) at the same time, select 32 - bit timer mode b y setting the t32 bit of the base timer 0 timer control register (bt0tmcr). 3. set a reload value in the upper 16 bits in the base timer 1 cycle setting register (bt1pcsr). 4. set a reload value in the lower 16 bits in the base timer 0 cycle setting register (bt 0pcsr). notes : ? rewrite the t32 bit while the operation of both of the even - number and odd - number channels is stopped. whether the counting operation is stopped can be checked by setting the cten bit of the base timer x timer control register (btxtmcr) to " 0" (cten=0) . ? a reload value in the base timer x cycle setting register (btxpcsr) must be set in the order of the odd - number even - number channels. ? operation in 32 - bit timer mode, the counting operation is basically the same as in 16 - bit timer mode. however, the counting operation conforms to the settings of the even - number channels, ignoring the settings of the registers nex t to the odd - number channels. ? base timer x timer control register (btxtmcr) ? base timer x status control register (btxstc) this section explains the counting in the 32 - bit timer mode. 1. when the 32 - bit reload timer activates, the values in the odd - number cha nnel base timer x cycle setting register (btxpcsr) and the even - number channel base timer x cycle setting register (btxpcsr) (lower 16- bit) are loaded to the down counter. 2. the down counter starts counting as a 32 - bit counter with the even - number channels serving as the lower 16- bit and the odd - number channels as the upper 16- bit. mb91590 series mn705-00009-3v0-e 649
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 54 3. when the down counter underflows, the udir bit of the base timer x timer control register (btxtmcr) of the even - number channels changes to "1". the channel configuration in 32 - bit timer mode is shown below. figure 5- 11 configuration in 32 - bit timer mode notes : ? the value of the down counter can be checked by reading the base timer x timer register (btxtmr). in the 32 - bit timer mode, it must be read in the order of the lower 16- bit (even - numbered channel) upper 16- bit (odd - number channel). ? in 32 - bit timer mode, the operation of the 32 - bit reload timer conforms to the settings of the even - number channels. therefore, activation triggers and interrupt requests from even - number channels are valid. the output signal (tout) from an odd - number channel pin is fixed to "l" level. ch.1 ch.0 t32=1 t32=0 underfl ow underfl ow upper 16-bit inter r upt request low er 16-bit wavefor m output read/w r ite signal low er 16-bit upper 16-bit exte r nal acti v ation t r igger reload v alue reload v alue do wn counter do wn counter mb91590 series mn705-00009-3v0-e 650
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 55 5.4.5. interrupts this section explains interrupts of the base timer. an interrupt request is generated in one of the following e vents: ? an activation trigger is detected. (trigger interrupt request) ? an underflow occurs (underflow interrupt request). table 5-3 interrupt occurrence conditions interrupt request interrupt request flag permission of interrupt request interrupt request clear trigger interrupt request btxstc : tgir=1 btxstc : tgie=1 set the tgir bit of btxstc to "0". underflow i nterrupt request btxstc : udir=1 btxstc : udie=1 set the udir bit of btxstc to "0". notes : ? once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request will be issued when the interrupt is enabled. to enable the generation of an interrupt request, perform one of the following operations: ? clear the current interrupt request before enabling the generation of an interrupt request. ? clear the current interrupt request when enabling the interrupt. ? either clear the current interrupt request after disabling the generation of an interrupt request or clear the current interrupt request within the interrupt processing routine. ? for interrupt vector numbers used when issuing an interrupt request, see " c. list of interr upts vector " in entitled " appendix ". ? set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (icr00 to icr47). for information on interrupt level setting, see the chapter entitled " chapter : interrupt c ontrol (interrupt controller) ". mb91590 series mn705-00009-3v0-e 651
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 56 5.4.6. precautions for using this device this section explains precautions for using this device . note the following when using the 16/32 - bit reload timer: ? notes on program setting ? change the following bits of the base timer x t imer control register (btxtmcr) after stopping the 16- bit down counter by resetting cten bit to "0" (cten=0) . ? cks2 to cks0 bits ? egs1 and egs0 bits ? t32 bit ? fmd2 to fmd0 bits ? mdse bit ? all registers are initialized when the fmd2 to fmd0 bits of the timer contr ol register (btxtmcr) are set to "000" to select reset mode. ? before the base timer function or t32 bit can be changed, the base timer must be reset once. except when rewriting the status of fmd2 to fmd0 bits or t32 bit of the timer control register (btxtmc r) after a reset, be sure to set the fmd2 to fmd0 bits to "000" to select the reset mode. then, rewrite the status of these bits. ? notes on operations ? if the count timing of the down counter and the load timing occur at the same time, the load operation i s given precedence. ? if a 16/32 - bit reload timer activation trigger is detected when counting ends in one - shot mode, the value (cycle) set in the base timer x cycle setting register (btxpcsr) is loaded to the 16 - bit down counter, which begins counting. ? a di fferent signal (external clock, external activation trigger, wave form) i/o operation can be selected using the base timer i/o selection function. ? notes on interrupts ? if an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at the same time, the flag clear instruction is ignored. the interrupt request flag is held to "1". mb91590 series mn705-00009-3v0-e 652
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 57 5.5. 16- bit pwm timer operation t his section explains the 16- bit pwm t imer o peration . this section explains the operation per formed when the base timer included in this series is used as the 16 - bit pwm timer. an example is also given to set various operation conditions. figure 5- 12 block diagram (16 - bit pwm timer operation) ck s pclk egs 2 3 2 0 2 7 2 8 str g cte n cten m ds e 16 osel udie tg ie dti e 16 16 pm sk btxpdu t irq0 irq1 edge btxpcsr: ba s e timer x cyc l e setting register (btxpcsr) btxpdut: ba s e timer x duty s e tting register (btxp d ut) load writing buffer peripheral clock buffer invert control match detection division edge load count clock waveform output (tout signal) external clock (eck signal) 16-bit toggle underflow count underflow/duty interrupt external activation trigger (tgin signal) trigger trigger interrupt request timer enabled btxpdu t btxpcsr count enabled enabled down counter generation circuit detection detection request match interrupt source generation mb91590 series mn705-00009-3v0-e 653
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 58 5.5.1. overview t his section explains the o verview of the 16 - bit pwm t imer o peration . the 16 - bit pwm timer sets the cycle in the cycle setting register (btxpcsr) an d the duty in the duty setting register (btxpdut). a desired waveform (tout signal) can be output by setting values in these registers. the 16 - bit pwm timer starts decre as ing from the value set in the base timer x cycle setting register (btxpcsr). when the value of the down counter matches the value of the duty setting register (btxpdut), the output signal (tout) level is inverted. when the down counter underflows, the output level is inverted again. this method enables output of a desired waveform (tout si gnal) with a cycle and duty. one of two 16 - bit pwm timer operation modes can be selected using the mdse bit of the timer control register (btxtmcr) as follows: ? reload mode (mdse = 0): in this mode, when the 16 - bit down counter underflows, the preset cycle is reloaded to allow the timer to restart counting. ? one - shot mode (mdse = 1): once the 16 - bit down counter underflows, the counter will no longer count. mb91590 series mn705-00009-3v0-e 654
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 59 5.5.2. operation in reload mode t his section explains the o peration in r eload m ode . this section explains th e operation in reload mode. ? overview in this mode, the value set in the base timer x cycle setting register (btxpcsr) is reloaded every time an underflow occurs to ensure that countdown is continued. to use this mode, set reload mode by resetting the mdse bit of the base timer x timer control register (btxtmcr) to "0" (mdse=0) . ? operation ? activation activate the 16 - bit pwm timer with the following procedure: 1. permit the 16- bit pwm timer operation by setting the cten bit of the base timer x timer control reg ister (btxtmcr) to "1" (cten=1) . the 16 - bit pwm timer begins to wait for an activation trigger. 2. enter an activation trigger by one of the following methods: ? set the strg bit of the base timer x timer control register (btxtmcr) to "1" (software trigger). ? ent er an effective edge (an edge set in the egs1 and egs0 bits) for an external activation trigger (tgin signal). the 16 - bit down counter starts decre as ing from the value set in the base timer x cycle setting register (btxpcsr). notes : ? the external activation trigger (tgin signal) entry method varies depending on the i/o mode specified by the i/o selection register (btsel01). ? after a 16 - bit pwm timer activation trigger is detected, the following time is required before the value set in the base timer x cycle setting register (btxpcsr) can be loaded to the 16 - bit down counter: ? if a software trigger is input: 1t (t: count clock cycle) ? if an external event trigger is used: 2t to 3t (t:count clock cycle) ? counting operation when an activation trigger is input, th e 16 - bit down counter, in synchronization with the count clock, starts decreas ing from the value set in the cycle setting register (btxpcsr). when the value of the 16 - bit down counter matches the value of the duty setting register (btxpdut), the operation is performed as follows: ? the dtir bit of the status control register (btxstc) changes to "1". ? the level of the output signal (tout) is inverted. ? countdown is continued. later, when the 16 - bit down counter underflows, the operation is performed as follows: ? the udir bit of the status control register (btxstc) changes to "1" and the level of the output signal (tout) is inverted. ? the value of the cycle setting register (btxpcsr) is reloaded to continue countdown. every time an underflow occurs, the value of th e cycle setting register (btxpcsr) is reloaded to continue counting. operation to be performed when an activation trigger is input during counting depends on whether mb91590 series mn705-00009-3v0-e 655
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 60 reactivation is permitted based on the rtgen bit of the timer control register (btxtmcr). ? if reactivation is not permitted (rtgen = 0): any activation trigger is ignored when it is entered during counting. ? if reactivation is permitted (rtgen = 1): the tgir bit of the base timer x status control register (btxstc) changes to "1". in addition, the value set in the base timer x cycle setting register (btxpcsr) is reloaded to the 16 - bit down counter, which begins counting. these operations are shown below. figure 5- 13 counting operation note : if the count timing of the 16 - bit down counter and the load timing occur at the same time, the load operation is given precedence. m n 0 (1) = t ( n + 1 ) ms (2) = t ( m + 1 ) ms m : value of base timer x cycle setting re gister (btxpcsr) n : value of base timer x duty setting register (btxpdut) t : cycle of count clock m n 0 counting ope r ation when reacti v ation is not ena bled rising edge detection acti v ation t r igger is ignored (1) (2) acti v ation t r igger pwm output waveform counting ope r ation when reacti vation is enabled rising edge detection reacti vate with tr igger pwm output waveform (1) (2) (1) = t ( n + 1 ) ms (2) = t ( m + 1 ) ms m : value of base timer x cycle setting register (btxpcsr) n : value of base timer x duty setting register (btxpdut) t : cycle of count clock acti v ation t r igger mb91590 series mn705-00009-3v0-e 656
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 61 ? output waveform t he waveform (tout signal) of the 16 - bit pwm timer can be output. the waveform (tout signal) to be output varies according to the setting of the osel bit of the base timer x timer control register (btxtmcr). ? normal polarity (osel = 0) ? when the 16 - bit pwm t imer is activated: "l" level ? when a duty match occurs: "h" level ? when an underflow occurs: "l" level ? inverted polarity (osel = 1) ? when the 16 - bit pwm timer is activated: "h" level ? when a duty match occurs: "l" level ? when an underflow occurs: "h" level th e output (tout signal) can be fixed at the "l" or "h" level. the output level varies depending on the setting of the osel bit of the base timer x timer control register (btxtmcr). examples of procedures are shown below. figure 5- 14 examples of procedures for fixing to "l" and "h" levels 0002 0001 0000 xxxx duty value p w m output waveform decrement duty value p w m output waveform increment duty value underflow interrupt request duty match interrupt request "1" is set to the p ms k bit with an underflow interrupt. the output signal will be fixed to the " l" level from the set cycle. p ms k bit : p ms k bit of base timer x timer control register (b txtmcr) if the duty value is set to the cycle setting value when a duty match interrupt request is generated, the output signal will be fixed to the " h" level in the next cycle. e xample of procedure for fixing to "h" level (os e l = 0) e xample of procedure for fixing to " l" level (os e l = 0) h h h h mb91590 series mn705-00009-3v0-e 657
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 62 note: ? the output method and output destination of the waveform (tout signal) from the 16 - bit pwm timer depend on the following settings: ? base timer i/o mode ? tioa0, tioa1 pin functions ? interrupt generation timing the 16 - bit ppg timer can generate an interrupt request in one of the following events: ? an activation trigger is detected. ? the value of the 16 - bit down counter matches the value of the base timer x duty setting register (btxpdut) ? when an underflow occurs: an example of interrupt request generation timing using the following settings is shown below. ? value of the cycle setting register (btxpcsr) = 0003 h ? value of the duty setting register (btxpdut) = 0001 h figure 5- 15 interrupt request generation timing chart xxxx h 0003 h 0002 h 0000 h 0001 h 0002 h 0003 h activation trigger load count clock counter value pwm output waveform interrupt request activation edge trigger interrupt request (tgir bit) duty match interrupt request (dtir bit) underflow interrupt request (udir bit) 2 t to 3t (external activation trigger) mb91590 series mn705-00009-3v0-e 658
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 63 5.5.3. operation in one - shot mode this section explains the operation in one - shot mode. this section explains the operation in one - shot mod e. ? counting operation in this mode, counting stops if an underflow occurs when the value of the 16 - bit down counter changes from the value set in the cycle setting register (btxpcsr) to "ffff h ". to use this mode, set one - shot mode by setting the mdse bit of the timer control register (btxtmcr) to "1" (mdse=1) . ? activation it is the same operation as in reload mode. see " operation " in the section entitled " 5.5.2 operation in reload mode". ? counting operation when an activation trigger is input, the 16 - bit down counter, in synchronization with the count clock, starts decreas ing from the value set in the cycle setting register (btxpcsr). when the value of the 16 - bit down counter matches the value of the duty setting register (btxpdut), the operation is performed as follows: ? the dtir bit of the base timer x status control register (btxstc) changes to "1". ? the level of the output signal (tout signal) is inverted. ? countdown is continued. later, when the 16 - bit down counter underflows, the operation is performed as follows: ? the udir bit of the base timer x status control register (btxstc) changes to "1". ? the level of the output signal (tout signal) is inverted. ? counting stops (the 16 - bit down counter stops at the value "ffff h "). operation to be performed when an activation trigger is input during counting depends on whether reactivation is permitted based on the rtgen bit of the timer control register (btxtmcr). ? if reactivation is not permitted (rtgen = 0): any activation trigger is ignored when it is entered during counting. ? if reactivation is permitted (rtgen = 1): the tgir bit of the base timer x status control register (btxstc) changes to "1". in addition, the value set in the base timer x cycle setting register (btxpcsr) is reloaded to the 16 - bit down counter, which begins counting. mb91590 series mn705-00009-3v0-e 659
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 64 figure 5- 16 counting opera tion note : if a 16 - bit pwm timer activation trigger is detected when counting ends, the value set in the cycle setting register (btxpcsr) is loaded to the 16 - bit down counter, which begins counting. ? output waveform it is the same operation as in reload mode. see " output waveform " in " 5.5.2 operation in reload mode ". ? interrupt generation timing it is the same operation as in reload mode. see " interrupt genera tion timing " in " 5.5.2 operation in reload mode ". m n 0 pwm output waveform : value of base timer x cycle setting register (btxpcsr) : value of base timer x duty setting register (btxpdut) : count clock cycle m n t m n 0 pwm output waveform m n t activation trigger counting operation when reactivation is disabled counting operation when reactivation is enabled rising edge detection rising edge detection activation trigger is ignored reactivate with activation trigger activation trigger = t( n+1) ms = t(m+1) ms : value of base timer x cycle setting register (btxpcsr) : value of base timer x duty setting register (btxpdut) : count clock cycle = t(n+1) ms = t(m+1) ms mb91590 series mn705-00009-3v0-e 660
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 65 5.5.4. interrupt this section explains interrupts. an interrupt request is generated in one of the following events: ? an activation trigger is detected. ( t ri gger interrupt request) ? the value of the 16 - bit down counter matches the value of ( the base timer x duty setting register (btxpdut) ) (duty match interrupt request). ? an underflow occurs (underflow interrupt request). table 5-4 conditions for interrupt generation interrupt request interrupt request flag permission of interrupt request interrupt request clear trigger interrupt request btxstc : tgir = 1 btxstc : tgie = 1 set the tgir bit of btxstc to "0". dut y match interrupt request btxstc : dtir=1 btxstc : dtie=1 set the dtir bit of btxstc to "0". underflow interrupt request btxstc : udir = 1 btxstc : udie = 1 set t he udir b it of btxstc to "0". notes : ? once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request will be issued when the interrupt is enabled. to enable the generation of an interrupt request, perform one of the following operations: ? clear the current interrupt request before enabling the generation of an interrupt request. ? clear the current interrupt request when enabling the interrupt. ? either clear the current interrupt request after disabling the generation of an interrupt request or clear the current interrupt request within the interrupt processing routine. ? for interrupt vector numbers used when issuing an interrupt request, see " c. list of interrupts vector " in entitled " appendix ". ? set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (icr00 to icr47). for information on interrupt level setting, see the chapter entitled " chapter : interrupt control (interrupt controller) ". mb91590 series mn705-00009-3v0-e 661
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 66 5.5.5. precautions for using this device this section explains precautions for us ing this d evice . note the following when using the 16 - bit pwm timer: ? notes on program setting ? change the following bits of the timer control register (btxtmcr) only after stopping the 16 - bit down counter by resetting the cten bit to "0" (cten=0) . ? cks2 to cks0 bits ? egs1 and egs0 bits ? fmd2 to fmd0 bi ts ? mdse bit ? all registers are initialized when the fmd2 to fmd0 bits of the base timer x timer control register (btxtmcr) are set to "000" to select reset mode. ? before the base timer function can be changed, the base timer must be reset once. except when r ewriting the fmd2 to fmd0 bits of the base timer x timer control register (btxtmcr) after reset, be sure to clear fmd2 to fmd0 bits to "000" to select the reset mode, and then select a base timer function using the fmd2 to fmd0 bits again. ? to s et 16 - bit pw m timer cycles or duties, proceed as follows: 1. select the 16 - bit pwm timer as the base timer function by setting the fmd2 to fmd0 bits of the base timer x timer control register (btxtmcr) to "001" (fmd2 to fmd0=001) . 2. set the cycle in the base timer x cycle s etting register (btxpcsr). 3. set the duty in the base timer x duty setting register (btxpdut). ? notes on operation ? if the count timing of the 16 - bit down counter and the load timing occur at the same time, the load operation is given precedence. ? when a 16 -b it pwm timer reactivation trigger is detected when counting ends in one - shot mode, the value in the base timer x cycle setting register (btxpcsr) is loaded to the 16 - bit down counter, which then starts counting. ? a different signal (external clock, external activation trigger, wave form) i/o operation can be selected using the base timer i/o selection function. ? notes on interrupts if an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at t he same time, the flag clear instruction is ignored. the interrupt request flag is held to "1". mb91590 series mn705-00009-3v0-e 662
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 67 5.6. 16- bit ppg timer operation this section explains the 16- bit ppg t ime r o peration . this section explains the operation performed when the base timer included in t his series is used as the 16 - bit ppg timer. examples of procedures for setting various operating conditions are also provided. figure 5- 17 block diagram (16 - bit ppg timer operation) btxprll ck s pclk egs 2 3 2 0 2 7 2 8 str g cte n cte n m ds e 16 btc t os el udie tg ie pp g output btxprl h pms k irq0 irq1 btxprll : b a se timer x l wi d th setting reload (bt x prll) btxprlh : b a se timer x h wi dth setting reload (bt x prlh) btxtmr : ba s e timer x timer r egister (btxtmr) buffer trigger interrupt request invert control toggle interrupt load count clock count count underflow down counter division edge edge peripheral clock external clock (eck signal) external activation trigger (tgin signal) trigger timer enabled reload data setting underflow (tout signal) detection enabled detection circuit generation source generation enabled interrupt request mb91590 series mn705-00009-3v0-e 663
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 68 5.6.1. overview t his section explains the o verview of the 16 - bit ppg t imer o peration . the 16 - bit ppg timer, once activated, decreases from the value initially specified by the base timer x l width setting reload register (btxprll). when counting down from the value set in the l width setting reload register (btxprll) is completed, the timer begins counting down from the value set in the h wi dth setting reload register (btxprlh). when counting down from the value set in each register is completed, the output signal (tout) inverts its level. therefore, by configuring the l width setting reload register (btxprll) and h width setting reload regis ter (btxprlh), you can arbitrarily set the widths of the "l" and "h" levels. one of two 16 - bit ppg timer operation modes can be selected using the mdse bit of the timer control register (btxtmcr) as follows: ? reload mode (mdse = 0): a sequence of "l" - level and "h" - level signals (consecutive pulses) is output. ? one - shot mode (mdse = 1): a string of one "l" - level signal and one "h" - level signal (single pulses) is output. mb91590 series mn705-00009-3v0-e 664
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 69 5.6.2. pulse width calculation method this section explains the pulse w idth ca lculation m ethod . w hen the 16 - bit ppg timer has counted down by the value set in the l width setting reload register (btxprll) or base timer x h width setting reload register (btxprlh) plus 1, the output signal (tout) inverts its level. therefore, the pulse width of the signal to be output is obtained by the following formula: example: if the output polarity is normal: "l" level pulse width = t (l + 1) "h" level pulse width = t (h + 1) t: count clock cycle l: value set in the base timer x l width setting reload register (btxprll) h: value set in the base timer x h width setting reload register (btxprlh) this means that when the l width setting reload register (btxprll) and h width setting reload register (btxprlh) are set to "0000 h ", the pulse width will be equal to one cycle of the count clock. when they are set to "ffff h ", the pulse width will be equal to 65536 cycles of the count clock. mb91590 series mn705-00009-3v0-e 665
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 70 5.6.3. operation in reload mode this section explains the operation in reload mode. this section explains the operation in reload mode. ? ov erview in this mode, the values set in the base timer x l width setting reload register (btxprll) and base timer x h width setting reload register (btxprlh) are alternately reloaded to the down counter to ensure that the down counter continues to count dow n. a desired pulse width can be output continuously by rewriting the base timer x l width setting reload register (btxprll) and base timer x h width setting reload register (btxprlh) each time an underflow interrupt request is issued. to use this mode, set reload mode by resetting the mdse bit of the base timer x timer control register (btxtmcr) to "0" (mdse=0) . ? operation ? activation activate the 16 - bit ppg timer with the following procedure: 1. permit the 16- bit ppg timer operation by setting the cten bit of the timer control register (btxtmcr) to "1" (cten=1) . the 16 - bit ppg timer begins to wait for an activation trigger. 2. enter an activation trigger by one of the following methods: set the strg bit of the base timer x timer control register (btxtmcr) to "1" (so ftware trigger). enter an effective edge (an edge set in the egs1 and egs0 bits) for an external activation trigger (tgin signal). notes : ? the external activation trigger (tgin signal) entry method varies depending on the i/o mode specified by the i/o selection register (btsel01). ? after a 16 - bit ppg timer activation trigger is detected, the following time is required before the value (cycle) set in the l width setting reload register (btxprll) can be loaded to the 16 - bit down counter: ? if a software trigger is input: 1t (t: count clock cycle) ? if an external event trigger is used: 2t to 3t (t:count clock cycle) ? counting operation counting operation initiated by the entry of an activation trigger is explained below, using an example where the osel bit of the t imer control register (btxtmcr) is set for normal polarity (osel = 0). 1. the value set in the l width setting reload register (btxprll) is transferred to the 16 - bit down counter and the value set in the base timer x h width setting reload register (btxprlh) is transferred to the buffer. the 16- bit down counter begins to count down from the value of the l width setting reload register (btxprll). the output signal (tout) is at the "l" level. 2. the 16 - bit down counter completes counting down from the value of l wi dth setting reload register (btxprll). 3. the buffered value of h width setting reload register (btxprlh) is reloaded to the 16 - bit down counter, which continues counting down. the output signal (tout) is at the "h" level. 4. the 16 - bit down counter completes co unting down from the value of h width setting reload register (btxprlh), thus causing an underflow. 5. the value of l width setting reload register (btxprll) is reloaded to the 16 - bit down counter, which continues count down. the output signal (tout) is at the "l" level. in addition, the value of the h width setting reload register (btxprlh) is transferred to the buffer. 6. steps 2 to 5 are repeated to continue counting. mb91590 series mn705-00009-3v0-e 666
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 71 operation that is performed if reactivation is permitted or not during counting depends on whether reactivation is permitted based on the rtgen bit of the timer control register (btxtmcr). ? if reactivation is not permitted (rtgen = 0): any activation trigger is ignored when it is entered during counting. ? if reactivation is permitted (rtgen = 1): the tgir bit of the base timer x status control register (btxstc) changes to "1". in addition, the value of l width setting reload register (btxprll) is reloaded to the 16 - bit down counter, which starts counting. figure 5- 18 example of counting operation in reload mode counting o peration when reactivation is enabled counting o peration when reactivation is disabled activation trigger rising edge detection activation trigger is ignored. ppg output waveform underflow interrupt request (udir bit) underflow interrupt request (udir bit) interrupt request trigger interrupt request (tgir bit) m : value of base timer x l width setting reload register (btxprll) n : value of base timer x h width setting reload register (btxprlh) t : count clock cycle m n 0 (1) (1) (2) (2) ppg output wa veform rising edge detection reactivate with activation trigger activation trigger underflow interrupt request (udir bit) trigger interrupt request (tg ir bit) trigger interrupt request (tgir bit) m : value of base timer x l width setting reload register (btxprll) n : value of base timer x h width setting reload register (btxp rlh) t : count clock cycle m n 0 (1) (1) (2) (2) (1) mb91590 series mn705-00009-3v0-e 667
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 72 notes : ? the output method and output destination of the output signal (tout) from the 16 - bit ppg timer depend on the following setting s: ? base timer i/o mode ? tioa0, tioa1 pin functions ? if the count timing of the 16 - bit down counter and the load timing occur at the same time, the load operation is given precedence. ? write timing the values of the base timer x l width setting reload register (btxprll) and base timer x h width setting reload register (btxprlh) are reloaded at the following timing: the value set in the base timer x l width setting reload register (btxprll) it is loaded to the 16 - bit down counter in one of the following events : ? an activation trigger is detected. ? an underflow occurs after counting down from the value of the base timer x h width setting reload register (btxprlh) is completed. the value set in the base timer x h width setting reload register (btxprlh) it is trans ferred to the buffer in one of the following events: ? an activation trigger is detected. ? an underflow occurs after counting down from the value of the base timer x h width setting reload register (btxprlh) is completed. the content of the buffer is loaded to the 16 - bit down counter in the following event: ? counting down from the value of the base timer x l width setting reload register (btxprll) is completed. therefore, rewrite the base timer x l width setting reload register (btxprll) and base timer x h w idth setting reload register (btxprlh) during the period from the time an underflow occurs (the udir bit of the status control register (btxstc) changes to "1") to the time counting based on the next cycle begins. the new data will be effective as the next cycle. mb91590 series mn705-00009-3v0-e 668
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 73 figure 5- 19 write timing ? interrupt generation timing the 16 - bit ppg timer can generate an interrupt request in one of the following events: ? an activ ation trigger is detected. ? an underflow occurs based on the value of h width setting reload register (btxprlh). an example of interrupt request generation timing using the following settings is shown below. ? value of l width setting reload register (btxprl l) = 0001 h ? value of h width setting reload register (btxprlh) = 0001 h figure 5- 20 interrupt request generation timing chart l 0 l 1 l 2 l 3 h 0 h 1 h 2 h 3 xxxx h 0 h 1 h 2 xxxx l 0 0000 l 1 0000 l 2 0000 h 0 0000 l 0 h 0 l 1 h 1 l 2 h 2 h 1 000 0 h 2 0000 acti v ation t r igger tr igger inter r upt request underfl ow inter r upt request btxprll btxprlh buf f er f or btxprlh btxtmr ppg output waveform btxprll : base timer x l width setting reload (btxprll) ~ ~ ~ rising edge detection the "l" width and "h" width of the n e xt cycle are set to the register ~ ~ ~ btxprlh : base timer x h width setting reload (btxprlh) btxtmr : base timer x timer register (btxtmr) the "l" width and "h" width of the next cycle are set to the register xxxx h 0001 h 000 0 h 0000 h 0001 h 000 0 h 00 01 h acti v ation t r igger load count clo ck counter v alue ppg output waveform inter r upt request acti v ation edge tr igger inter r upt request (tgir bit) underfl o w inter r upt request (udir bit) 2t to 3t ( e xte r nal t r igger) mb91590 series mn705-00009-3v0-e 669
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 74 5.6.4. operation in one - shot mode this section explains the operation in one - shot mode. this section explains the operation in one - shot mod e. ? counting operation ? activation it is the same operation as in reload mode. see " operation " in " 5.6.3 operation in reload mode ". ? counting operation counting operation ini tiated by the entry of an activation trigger is explained below, using an example where the osel bit of the timer control register (btxtmcr) is set for normal polarity (osel = 0). 1. the value set in the base timer x l width setting reload register (btxprll) is transferred to the 16 - bit down counter and the value set in the base timer x h width setting reload register (btxprlh) is transferred to the buffer. the 16 - bit down counter begins to count down from the value of the l width setting reload register (btxp rll). the output signal (tout) is at the "l" level. 2. the 16 - bit down counter completes counting down from the value of l width setting reload register (btxprll). 3. the buffered value of h width setting reload register (btxprlh) is reloaded to the 16 - bit down counter, which continues counting down. the output signal (tout) is at the "h" level. 4. the 16 - bit down counter completes counting down from the value of h width setting reload register (btxprlh), thus causing an underflow. 5. the counting stops. operation tha t is performed if reactivation is permitted or not during counting depends on whether reactivation is permitted based on the rtgen bit of the timer control register (btxtmcr). ? if reactivation is not permitted (rtgen = 0): any activation trigger is ignored when it is entered during counting. ? if reactivation is permitted (rtgen = 1): the tgir bit of the status control register (btxstc) changes to "1". in addition, the value of l width setting reload register (btxprll) is reloaded to the 16- bit down counter, wh ich starts counting. mb91590 series mn705-00009-3v0-e 670
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 75 figure 5- 21 example of counting operation if reactivation is not enabled figure 5- 22 example of counting operation if reactivation is enabled ppg output waveform rising edge detection acti v ation t r igger is ignored t r igger m n 0 trigger interrupt request (tgir bit) underflow interrupt request (udir bit) : value of base timer x l width setting reload register (btxprll) : value of base timer x h width setting reload register (btxprlh) : count clock cycle = t(m+1) ms = t(n+1) m n 0 interrupt request (1) (2) (1) (2) ppg output waveform rising edge detection reactivate with activation trigger trigger m n 0 trigger interrupt request (tgir bit) underflow interrupt request (udir bit) trigger in terrupt request (tgir bit) interrupt request : value of base timer x l width setting reload register (btxprll) : value of base timer x h width setting reload register (btxprlh) : count clock cycle = t(m+1) ms = t(n+1) ms m n 0 (1) (2) (1) (2) mb91590 series mn705-00009-3v0-e 671
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 76 notes : ? the output method and output destination of the output signal (tout) from the 16 - bit ppg timer depend on the following settings: ? base timer i/o mode ? tioa0, tioa1 pin functions ? if a 16 - bit ppg timer activation trigger is detected when counting ends, the value (cycle) of l width setting reload register (btxprll) is loaded to the 16 - bit down counter, which starts counting. ? interrupt generation timi ng it is the same operation as in reload mode. see " interrupt generation timing " in " 5.6.3 operation in reload mode ". mb91590 series mn705-00009-3v0-e 672
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 77 5.6.5. interrupt s t his section explains i nterrupt s of the 16 -b it ppg t imer o peration . an interrupt request is generated in one of the following events: ? an activation trigger is detected. ( t rigger interrupt request) ? an underflow occurs based on the value of h width setting reload register (btxprlh). ( u nderflow interru pt request) table 5-5 interrupt occurrence conditions interrupt request interrupt request flag permission of interrupt request interrupt request clear trigger interrupt request btxstc : tgir = 1 btxstc : tgie = 1 set the tgir bit of btxstc to "0". underfl ow interrupt request btxstc : udir = 1 btxstc : udie = 1 set the udir bit of btxstc to "0". notes : ? once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request will be issued when the interrupt is enable d. ? to enable the generation of an interrupt request, perform one of the following operations: ? clear the current interrupt request before enabling the generation of an interrupt request. ? clear the current interrupt request when enabling the interrupt. ? eithe r clear the current interrupt request after disabling the generation of an interrupt request or clear the current interrupt request within the interrupt processing routine. ? set an interrupt level corresponding to the interrupt vector number, using interrupt control registers (icr00 to icr47). for information on interrupt level setting, see the chapter entitled " chapter : interrupt control (interrupt controller) ". mb91590 series mn705-00009-3v0-e 673
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 78 5.6.6. application notes this section explains notes when using the 16 - bit ppg timer. note the follow ing when using the 16 - bit ppg timer: ? notes on program setting ? change the following bits of the timer control register (btxtmcr) only after stopping the 16 - bit down counter by resetting the cten bit to "0" (cten=0) . ? cks2 to cks0 bits ? egs1 and egs0 bits ? fmd2 to fmd0 bits ? mdse bit ? all registers are initialized if the fmd2 to fmd0 bits of timer control register (btxtmcr) are set to "000" to select reset mode. ? before the base timer function can be changed, the base timer must be reset once. except when rewriting the fmd2 to fmd0 bits of timer control register (btxtmcr) after reset, be sure to clear fmd2 to fmd0 bits to "000" to select the reset mode, and then select a base timer function using the fmd2 to fmd0 bits again. ? set the 16 - bit ppg timer in the following steps. 1. set the 16 - bit ppg timer as the base timer function by setting the fmd2 to fmd0 bits of timer control register (btxtmcr) to "010" (fmd2 to fmd0=010) . 2. set the l width setting reload register (btxprll). 3. set the h width setting reload register (btxprlh ). ? notes on operations ? the value loading precedes if the count timing of the 16 - bit down counter and the load timing occur at the same time. ? if a 16 - bit ppg timer reactivation trigger is detected when counting ends in the one - shot mode, the value (cycle) of l width setting reload register (btxprll) is loaded to the 16 - bit down counter, which starts counting. ? a different signal (external clock, external activation trigger, wave form) i/o operation can be selected using the base timer i/o selection function . ? notes on interrupts if an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at the same time, the flag clear instruction is ignored. the interrupt request flag is held to "1". mb91590 series mn705-00009-3v0-e 674
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 79 5.7. 16/32- bit pwc timer operation this section explains the 16/32 - bit pwc timer operation. this section explains the operation performed when the base timer included in this series is used as the 16/32 - bit pwc timer. examples of procedures for setting various operating conditions are also provided. figure 5- 23 block diagram (16 - bit pwc timer operation) btxdtbf 16-bit mode t32=0 cks peripheral clock (pclk) waveform to be measured (tin signal) edge detection edge detection division circuit count clock count enable count enable activation detection stop detection up counter clear overflow overflow interrupt request measurement completion interrupt request interrupt factor generation egs 3 3 2 0 2 7 2 8 mdse cten cten mdse 16 t32 ovie edie irq0 irq1 btxdtbf : base timer x data buffer register (btxdtbf) irq 0 irq 1 mb91590 series mn705-00009-3v0-e 675
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 80 figure 5- 24 block diagram (32 - bit pwc timer operation ) 32-bit mode t32=0 ch.0 ch.1 t32=1 bt0dtbf cks egs 3 3 2 0 2 7 2 8 mdse ct e n cten mdse 16 t32 ovie edie bt1dtbf 16 irq0 irq1 peripheral clock (pclk) waveform to be measured (tin signal) edge detection edge detection division circuit count enable activation detection stop detection count clock count enable up counter clear overflow count clock count enable up counter clear overflow bt0dtbf : base timer 0 x data buffer register (bt0dtbf) bt1dtbf : base timer 1 x data buffer register (bt1dtbf) overflow interrupt request measurement completion interrupt request interrupt factor generation mb91590 series mn705-00009-3v0-e 676
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 81 5.7.1. overview this section explains the overview of the 16/32 - bit pwc timer operation. the 16/32 - bit pwc timer is used to measure the pulse width and cycle of input signals. when a measurement start edge is detected in an input signal (tin), the counting up starts. this counting stops when a measurement end edge is detected. the counted value (that is, the measured result) is stored as the pulse width or cycles in the data buffer register (btxdtbf). the 1 6/32 - bit pwc timer supports three modes: the timer mode, the operation mode, and measurement mode. the operation of the timer varies in accordance with a combination of these modes. note : the input method of the tin signal varies depending on the i/o mode that has been set by the i/o selection register (btsel01). see " 5.2 i/o allocation ". ? timer mode either of the following timer modes can be selected using the t32 bit of the timer control register (btxtmcr). ? 16- bit timer mode (t32 = 0): a 16 - bit pwc timer can operate individually for each of the channels. ? 32- bit timer mode (t32 = 1): two channels can be cascaded and used as a 32 - bit pwc timer. see " 5.7.3 32- bit timer mode operation " for details on the operation in 32 - bit timer mode. note : the t32 bit setting differs between odd - numbered and even - numbered channels when the 32 - bit timer mode is selected. for details, see " 5.7.3 32 - bit timer mode operation ". ? operation mode either of the following two modes can be selected using the mdse bit of the timer control register (btxtmcr). ? continuous measurement mode (mdse = 0): in this mode, after one sequence of measurement is conducted, the input of the next measurement start edge is awaited and the detection of the next measurement start edge triggers another sequence of measurement. ? single measurement mode (mdse = 1): in this mode, measurement is conducted only once. differences between the single and continuous measurement modes are listed on the table below. mb91590 series mn705-00009-3v0-e 677
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 82 table 5-6 differences between single and continuous measurement modes single measurement mode continuous measurement mode measurement measurement stops when a measurement end edge is detected. when a measurement end edge is detected, the measurement stops and the next measurement start edge is waited. when the next measurement start edge is detected, the measurement restarts. btxdtbf fu nction during measurement: the measured value is held. after measurement: the measurement result is held. during measurement: the previous measurement result is held. after measurement: the measurement result is held. during overflow the measurement stops . the measurement restarts from 0x0000 figure 5- 25 shows the standard operation flow. mb91590 series mn705-00009-3v0-e 678
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 83 figure 5- 25 operation flow start with cten bit of btxtmcr (cten=1) btxdtbf : base time r x ti mer c on trol regi st er (btxtmcr) btxstc : base timer x status control re gist er (btx stc) btxd tb f: base ti mer x dat a bu ffer re gi ster (btx dtb f) measurement start edge detection measurement completion stop counting edge detection select pwc mode select count clock select operation/ var ious settings resta rt clear counter measurement start edge detection conti n uous measurement mode single measurement mode star t counting star t counting increment increment ov erfl o w caused change o vir bit of ov erfl o w caused change o vir bit of change edir bit of measurement completion change edir bit of stop counting tr ans f er count v alue to btxdtbf stop ope r ation btxstc to "1" btxstc to "1" btxstc to "1" edge detection btxstc to "1" measurement modes clear interrupt request flag enable interrupts mb91590 series mn705-00009-3v0-e 679
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 84 note : in the continuous measurement mode, if the next measurement is completed before the measurement result has been read from the data buffer register (btxdtbf), the value being held by the data buffer register (btxdtbf) is overwritten by the new value. the old value is discarded. if it has occurred, the err bit of the status control register (btxstc) changes to "1". this err bit is cleared to "0" when a value is read from the base timer x data buffer register (btxdtbf). ? measurement mode either of the following five mo des can be selected using egs2 to egs0 bits of the timer control register (btxtmcr). figure 5- 26 measurement modes and their explanation measurement mode (egs2 to egs0) measurement desc r iption . count (measurement) start: at r ising edge detection count (measurement) stop : at falling edge detection width width count sta rt count stop sta rt stop measurement of h pulse width (egs2 to egs0=000) the width of the pe r iod which the the "h" l evel signal is being input is the width of the period during which the "l" level signal being input is measured. count (measurement) start: at falling edge detection count (measurement) stop: at rising edge detection measurement of l pulse width(egs2 to egs0=100) . width width count start count start count stop count stop the cycle from the f alling edge detection to the n ext f alling edge detection is measured . measurement of the cycle between falling edges (egs2 to egs0=010) count sta rt p e riod p e riod p e riod count stop start count stop start count (measurement) start: at fall ing edge detection count (measurement) stop: at fall ing edge detection the cycle from the r ising edge detection to the n ext r ising edge detection is measured count (measurement) start: at rising edge detection count (measurement) stop: at rising edge detection measurement of the cycle between rising edges (egs2 to egs0=001) p e riod count sta rt count stop start p e riod p e riod count stop start the width between the edges input continuously is measured. ?from rising edge detection to falling edge detection ?from falling edge detection to ris ing edge detection count measurement of the pulse width between all edges (egs2 to egs0=011) count (measurement) start: at edge detection count ( measurement) stop: at edge detection width width width count stop count start count sta rt mb91590 series mn705-00009-3v0-e 680
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 85 5.7.2. operation during pwc measurement this section explains the operation during pwc m easurement . this section explains the operations during measurement. for explanation of "sensitive edges" (1) and (2) described below, see fig ure 5- 26 measurement modes and their explanation . ? activation activate the 16/32 - bit pwc timer with the following procedure: enable the 16/32 - bit pwc timer operation by setting the cten bit of the timer control register (btxtmcr) to "1" (cten=1) . the coun ter value is cleared to "0000 h " and the 16/32 - bit pwc timer waits for an input of measurement start edge. (no counting occurs until an input of measurement start edge.) ? counting operation ? operation in single measurement mode if sensitive edge (1) is detected in the input signal (tin) when a measurement start edge is waited, the up counter starts counting up from "0001 h " in synchronous with the count clock. if sensitive edge (2) is detected in the input signal (tin), the up counter stops from operating. du ring this time, the up counter value is stored in the data buffer register (btxdtbf). an interrupt request can be generated at the end of measurement or at an occurrence of overflow. notes : ? in the single measurement mode, the counting stops if an overflow occurs. ? the input method of waveforms to be measured (tin signal) varies depending on the i/o mode that has been set by the i/o select ion register (btsel01). ? operation in continuous measurement mode if sensitive edge (1) is detected in the input signal ( tin) when a measurement start edge is waited, the up counter starts counting up from "0001 h " in synchronous with the count clock. if sensitive edge (2) is detected in the input signal (tin), the up counter stops from operating and waits for an input of mea surement start edge. during this time, the up counter value is stored in the data buffer register (btxdtbf). if a rising edge of the input signal (tin) is detected when a measurement start edge is waited, the up counter starts counting up from "0001 h " agai n. an interrupt request can be generated at the end of measurement or at an occurrence of overflow. note : the input method of waveforms to be measured (tin signal) varies depending on the i/o mode that has been set by the i/o select ion register (btsel01). mb91590 series mn705-00009-3v0-e 681
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 86 figure 5- 27 operation example ? reactivation if the cten bit of the base timer x timer control register (btxtmcr) is set to "1" during counting, the up counter reactivates and operates as follows. ? if the counter is reactivated when a measurement start edge is waited: the current status waiting for a measurement start edge is continued. ? if the timer is reactivated during measurement: the up counter value is cleared to "0000 h " and set to th e measurement start edge waiting status. mb91590 series mn705-00009-3v0-e 682
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 87 notes : ? if a detection of measurement end edge and a timer reactivation occur simultaneously, the following may result. in such case, set the interrupt control correctly by considering the operation of interrupt request flag. ? single measurement mode: the timer reactivates and waits for a measurement start edge. also, the edir bit (the measurement end interrupt request flag) of the status control register (btxstc) is set to "1". ? continuous measurement mode: the timer reactivates and waits for a measurement start edge. also, the edir bit (the measurement end interrupt request flag) of the status control register (btxstc) is set to "1". also, the current measurement result is transferred to the data buffer register (btxd tbf). ? if the 16/32 - bit pwc timer is reactivated in the continuous measurement mode and if a measurement start edge is detected in the input signal (tin) simultaneously, the timer immediately starts counting from the value "0001 h ". ? calculating the pulse w idth after the measurement, the measurement result can be read from the base timer x data buffer register (btxdtbf) and the measured pulse width can be calculated using the following formula. pulse width = n t n: data buffer register (btxdtbf) value t: count clock cycle mb91590 series mn705-00009-3v0-e 683
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 88 5.7.3. 32- bit timer mode operation this section explains the 32- bit ti mer m ode o peration . this section explains the setting and operation for cascading 2 channels of a 16 - bit pwc timer and using them as a 32 - bit pwc timer. ? overview using the t 32 bit of the timer control register (btxtmcr), 2 channels of a 16 - bit pwc timer can be cascaded and used as a 32 - bit pwc timer. in this mode, the even - numbered channel corresponds to the lower 16 - bit operation, and the odd - numbered channel corresponds to the upper 16 - bit operation. therefore, the up counter must be read in the order of the lower 16 bits (even - numbered channel ) the upper 16 bits (odd - numbered channel). ? setting procedure (example) to select the 32 - bit timer mode, set the t32 bit of the ba se timer x timer control register (btxtmcr) of the even - numbered channel to "1". also, set the t32 bit of the odd - numbered channel to "0". when setting 32 - bit timer mode, set the registers using the procedure shown below. the register setting differs betwe en even - numbered and odd - numbered channels. in this example, channel 0 and channel 1 are connected by cascading. 1. specify ch.0 to reset mode by setting fmd2 to fmd0 bits of the base timer 0 timer control register (bt0tmcr). (fmd2 to fmd0 = 000) 2. select 16/32 - bit pwc timer for c h.0 and ch.1 by setting the fmd2 to fmd0 bits of the base timer x timer control register (bt0tmcr, bt1tmcr) of ch.0 and ch.1. (fmd2 to fmd0 = 100 ) at the same time, select the 32 - bit timer mode by setting the t32 bit of the base timer 0 timer control register (bt0tmcr). (t32 = 1) note : rewrite the t32 bit while the operation of both of the even - numbered and odd - numbered channels are stopped. whether the counting operation is stopped can be checked by setting the cten bit of the timer control register (btxtmcr) to "0" (cten=0) . ? operations in the 32 - bit timer mode, the counting operation is basically the same as in the 16 - bit timer mode. however, the counting operation conforms to the settings of the even - number channels, ignoring the sett ings of the registers next to the odd - number channels. ? base timer x timer control register (btxtmcr) ? base timer x status control register (btxstc) this section explains the counting in the 32 - bit timer mode. 1. if the 16/32 - bit pwc timer operation is enabled using the cten bit of the timer control register (btxtmcr) (by setting cten = 1) of the even - numbered channel, the 32- bit pwc timer starts. 2. when a measurement start edge is detected in the input signal (tin), the counting starts. 3. the up counter starts cou nting as a 32 - bit counter with the even - number channel serving as the lower 16 bits and the odd - number channel as the upper 16 bits. 4. when a measurement end edge is detected in the input signal (tin), the lower 16 - bit data of the up counter is stored in the data buffer register (btxdtbf) of the even - numbered channel. also, the upper 16- bit data is stored in the data buffer register (btxdtbf) of the odd - numbered channel. the channel configuration in 32 - bit timer mode is shown below. mb91590 series mn705-00009-3v0-e 684
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 89 figure 5- 28 configuration in 32 - bit timer mode ch. 1 ch.0 t32=1 t32=0 ov erfl ow overlow upper 16-bit inter r upt low er 16-bit waveform read/w r ite signal low er 16-bit upper 16-bit pwc measurement counter v alue counter v alue up counter up counter notes : ? the down counter value can be checked by reading the data buffer register (btxdtbf). in the 32- bit timer mode, it must be read in the order of the lower 16 bits (even - numbered channel) upper 16 bits (odd - number channel). ? in 32 - bit timer mode, the operation of the 32 - bit pwc timer conforms to the settings of the even - number channel. therefore, an interrupt request of the even - numbered channel is effective. mb91590 series mn705-00009-3v0-e 685
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 90 5.7.4. interrupt this section expl ains interrupt of the base timer. an interrupt request is generated in one of the following events: ? an overflow occurs. ( o verflow interrupt request) ? the measurement ends. ( m easurement end interrupt request) table 5-7 interrupt occurrence conditions interrupt request interrupt request flag permission of interrupt request interrupt request clear overflow interrupt request btxstc : ovir=1 btxstc : ovie=1 set the ovir bit of btxstc to "0". measurement end interrupt requ est btxstc : edir=1 btxstc : edie=1 read btxdtbf notes : ? once the generation of an interrupt request is enabled while the interrupt request flag is "1", an interrupt request will be issued when the interrupt is enabled. ? to enable the generation of an interrupt request, perform one of the following operations: ? clear the current interrupt request before enabling the generation of an interrupt request. ? clear the current interrupt request when enabling the interrupt. ? either clear the current interrupt request after disabling the generation of an interrupt request or clear the current interrupt request within the interrupt processing routine. ? for interrupt vector numbers used for issuing an interrupt request, see "c. list of interrupts vector" in entitled "appendix". ? set the interrupt level corresponding to the interrupt vector number in one of the interrupt control registers (icr00 to icr47). for information on interrupt level setting, see the chapter entitled " chapter : interrupt control (interrupt controller) ". mb91590 series mn705-00009-3v0-e 686
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 91 5.7.5. ap plication notes this section explains a pplication n otes of the base timer. note the following when using the 16/32 - bit pwc timer: ? notes on program setting ? change the following bits of the base timer x timer control register (btxtmcr) after stopping the up counter by resetting the cten bit to "0" (cten=0) . ? cks2 to cks0 bits ? egs2 to egs0 bits ? t32 bit ? fmd2 to fmd0 bits ? mdse bit ? all registers are initialized when the fmd2 to fmd0 bits of the timer control register (btxtmcr) are set to "000" to select reset mode . ? before the base timer function or t32 bit can be changed, the base timer must be reset once. except when rewriting the status of fmd2 to fmd0 bits or t32 bit of the timer control register (btxtmcr) after a reset, be sure to reset the fmd2 to fmd0 bits to "000" to select the reset mode. then, rewrite the status of these bits. ? the timer may operate due to the status of previously measured signals if the followings are set simultaneously during system reset or during reset mode. ? the base timer function is s et for the 16/32 - bit pwc timer by setting the fmd2 to fmd0 bits of the base timer x timer control register (btxtmcr) to "100" (fmd2 to fmd0=100) . ? enable 16/32 - bit pwc timer operation by setting the cten bit of the base timer x timer control register (btxtmc r) to "1" (cten=1) . ? notes on operations ? the value loading precedes if the count timing of the up counter and the load timing occur at the same time. ? if the 16/32 - bit pwc timer operation is enabled by setting the cten bit of the base timer x timer control register (btxtmcr) to "1" (cten=1) , the up counter value is cleared. also, the up counter value is made invalid if it has been set before the operation is enabled. ? if the 16/32 - bit pwc timer is reactivated in the continuous measurement mode and if a measure ment start edge is detected in the input signal (tin) simultaneously, the timer immediately starts counting from the value "0001 h ". ? if two channels of pwc timers are used as a single 32 - bit pwc timer, the 16 - bit pwc timer setting of the even - numbered chann el is made valid. the timer setting of odd - numbered channel is ignored. ? the input operation of measurement waveforms varies depending on the base timer i/o selection function. ? notes on interrupts ? if an instruction to clear the interrupt request flag and an instruction to change the interrupt request flag to "1" occur at the same time, the flag clear instruction is ignored. the interrupt request flag is held to "1". ? if a detection of measurement end edge and a reactivation of 16/32 - bit pwc timer occur simu ltaneously, the following may result. in such case, set the interrupt control correctly by considering the operation of the interrupt request flag. ? pulse width single measurement mode: the timer reactivates and waits for a measurement start edge. also, th e measurement end interrupt request flag (edir) is set to "1". ? pulse width continuous measurement mode: the timer reactivates and waits for a measurement start edge. the measurement end interrupt request flag (edir) is set to "1", and the currently measure d result is transferred to the data buffer register (btxdtbf). mb91590 series mn705-00009-3v0-e 687
chapter 19: base timer 5 . operation fujitsu semiconductor limited chapter : base timer fujitsu semiconductor confidential 92 mb91590 series mn705-00009-3v0-e 688
chapter 20: reload timer 1 . overview fujitsu semiconductor limited chapter: reloa d timer fujitsu semiconductor confidential 1 chapter : reload timer this chapter explains the reload timer. 1. overview 2. features 3. configuration 4. registers 5. operation 6. application note s code : 20_mb91590_hm_e_reloadtim_00 8 _201111 28 mb91590 series mn705-00009-3v0-e 689
chapter 20: reload timer 1 . overview fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 2 1. overview this section explains the overview of the reload timer. this module is a 16 - bit reload down count timer with the interval timer mode, which counts the internal clock, and the event counter mode, which counts external events. figure 1-1 block diagram of reload timer (1 channel, overview) prescaler tout external pin peripheral clock (pclk) cascading from previous reload timer interrupt cascading to next reload timer counter & control unit ttrg external pin mb91590 series mn705-00009-3v0-e 690
chapter 20: reload timer 2 . features fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 3 2. features this section explains features of the reload timer. a 4 - channel reload timer is installed in this series . each channel is configured as foll ows: ? 16- bit down counter 1 ? 16- bit reload register 1 ? 16- bit reload / compare/ capture register 1 ? buffers described above 1 ? 6- bit prescaler for internal count clock creation 1 ? external trigger/event input (ttrg) 1 ? external toggle output (tout ) 1 ? control register 1 ? count comparator 1 this timer, equipped with the interval timer mode/event counter mode described below, can be used for the following purposes and functions by setting the registers: ? interval timer mode ? single o ne - shot o peration => single - shot timer ? dual one - shot operation ? single r eload o peration => reload timer ? dual reload operation => ppg(programmable pulse generator) ? compare mode => output compare, pwm(pulse width modulator) ? capture mode ( external trigger input/softw are trigg er use ) => pwc(pulse width counter) ? underflow interrupt/capture interrupt ? 6 types of internal clocks (peripheral clock (pclk) divided by 2/4/8/16/32/64) ? external trigger input (rising edge/falling edge/both edges) ? external gate input ? event coun ter mode ? single one - shot operation ? dual one - shot operation ? single reload operation ? dual reload operation ? compare mode ? capture mode (only software trigger) ? underflow interrupt/capture interrupt/compare interrupt ? external event input edge detection (rising edge detection/falling edge detection/both edge detection ) ? cascade mode ? use ch.0 output for ch.1 input. use ch.1 output for ch.2 input. use ch.2 output for ch.3 input. mb91590 series mn705-00009-3v0-e 691
chapter 20: reload timer 3 . configuration fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the reload timer. figure 3-1 block diagram of reload timer (1 channel, details) tout int mod0 mod1 reld inte uf ef outl cnte tmr tmrlra read/write read/write read/write read only tmrlrb count comparator count control buffer peripheral bus reload capture mode mode control reload selector csl2 csl1 csl0 gate trgm1 trgm0 tmcsr bit in any sequence trg unused compare mode end one-shot compare result underflow enable a count trigger peripheral clock capture trigger gate output ff prescaler clock selector input + synchronization ff edge control gate control peripheral clock peripheral clock ttrg select select mb91590 series mn705-00009-3v0-e 692
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: r eload timer fujitsu semiconductor confidential 5 4. registers this section explains registers of the reload timer. ? table of base address (base_addr) , external pin s table 4-1 table of base address (base_addr) , external pin s channel base_addr external pin tout ttrg 0 0x00 60 tot0 / tot0_1 / tot0_2 tin0 / tin0_1 / tin0_2 1 0x0 100 tot1 / tot1_1 / tot1_2 tin1 / tin1_1 / tin1_2 2 0x0 10 8 tot2 / tot2_1 / tot2_2 tin2 / tin2 _1 / tin2_2 3 0x0 11 0 tot3 / tot3_1 / tot3_2 tin3 / tin3_1 / tin3_2 ? registers map table 4-2 registers map address registers register function +0 +1 +2 +3 0x0060 tmrlra0 tmr0 16 - bit timer reload register a0 16 - bit time r register 0 0x0064 tmrlrb0 tmcsr0 16 - bit timer reload register b0 c ontrol status register 0 0x0 10 0 tmrlra1 tmr1 16 - bit timer reload register a1 16 - bit timer register 1 0x0 10 4 tmrlrb1 tmcsr1 16 - bit timer reload register b1 c ontrol status register 1 0x0 10 8 tmrlra2 tmr2 16 - bit timer reload register a2 16 - bit timer register 2 0x0 10 c tmrlrb2 tmcsr2 16 - bit timer reload register b2 c ontrol status register 2 0x0 11 0 tmrlra3 tmr3 16 - bit timer reload register a3 16 - bit timer register 3 0x0 11 4 tmrlrb3 tmcsr3 16 - bit timer reload register b3 c ontrol status register 3 mb91590 series mn705-00009-3v0-e 693
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 6 4.1. control status register : tmcsr (timer control and status register) t he bit configuration of the control status register is shown below . these registers control the operating mode and interrupt . it is not possible to rewrite any data other than bit7 and bit3 to bit 0 when bit1:cnte=1. it is possible to rewrite bit15 - bit 8 and bit6 - bit 4 and write counter operation enabling by writing cnte=1 simultaneously. it is also possible to rewrite bit15 - bit 8, bit6 - bit 4 and write operation disabling by writing cnte=0 simultaneously. ? tmcsr : address base_addr + 06 h ( access : byte , half - word , word ) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 mod[1:0] trgm[1:0] csl[2:0] gate initial value 0 0 0 0 0 0 0 0 attribu te r,w r,w r,w r,w r,w r,w r,w r,w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ef reserved outl reld inte uf cnte trg initial value 0 0 0 0 0 0 0 0 attribute r(rm1),w r,w r,w r,w r/w r(rm1),w r/w r0,w [b it15 , bit 14] mod [1:0] (mode) : mode selection bits mod[1:0] operation mode 00 single mode ( i nitial value ) 01 dual mode 10 compare mode 11 capture mode [b it13 , bit 12] trgm[1:0] (trigger input mode select) : ttrg input mode selection bit s these bits control input pin functions. the functions of th e interval timer mode differ from those of the event counter mode. [interval timer mode, trigger input (bit8:gate bit=0)] select an effective external edge which can be a reload trigger through ttrg input in the following manner: trgm[1:0] ttrg effective e xternal edge 00 no external trigger detection (initial value) 01 rising edge 10 falling edge 11 both edges mb91590 series mn705-00009-3v0-e 694
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 7 [ interval timer mode, gate input (bit8:gate =1)] select the pin level which enables the counter during ttrg input in the following manner: trgm [1:0] ttrg effective level x0 ttrg pin "l" counted only during the input period (initial value) x1 ttrg pin "h" counted only during the input period [ effective edge setting at the event counter mode ] in the event counter mode, select an edge for extern al event detection in the following manner: every time an external event is detected, the counter value is decreased . when an external event is selected, the setting of the bit8:gate bit becomes invalid. trgm[1:0] count target edge 00 reserved 01 rising edge 10 falling edge 11 both edges [b it11 to bit 9 ] csl[2:0] (conut source select) : count source selection bits these are count source selection bits. select a count source from the internal clock (peripheral clock (pclk) ) and the external event (ttrg input) specified following: when the event counter mode is set, set the count effective edge using bit13, bit 12:trgm[1:0]. csl[2:0] count source operation mode 000 division of the peripheral clock frequency by 2 (initial value) interval timer mode 001 division of the peripheral clock frequency by 4 010 division of the peripheral clock frequency by 8 011 division of the peripheral clock frequency by 16 100 division of the peripheral clock frequency by 32 101 division of the peripheral clock frequ ency by 6 4 110 cascade mode (ch.0:ttrg0, ch.1:tout0, ch.2:tout1, ch.3:tout2) event counter mode 111 external event (ttrg input) mb91590 series mn705-00009-3v0-e 695
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 8 [b it8 ] gate (gate input enable) : gate input enabling bit this bit controls the functions of the input pin (ttrg) of (bit 11 to bit 9:csl[2:0]=000 to 101) at the interval timer mode specified following. gate ttrg input pin functions 0 use as trigger input (initial value) 1 use as gate input this bit does not influence any operation at the event counter mode. [b it7 ] ef (exte nded flag) : extended interrupt flag this flag indicates that a compare match interrupt has occurred at the compare mode or a capture input interrupt has occurred at the capture mode. set factor [compare mode of the event counter mode] count down occurs f rom compare match (tmr = tmrlrb) [capture mode] capture input (retrigger) clear factor writing "0" to this bit or reset. writing "1" to this bit will not be effective. in synchronization with the count clock, set operation or clear operation are performed in the compare mode. the values read with read - modify - write instructions will always be "1". [b it6 ] reserved reserve d bit. data writing is ineffective. [ bit5 ] outl (output level) : output polarity setting bit this bit controls output polarity of the t imer output pin (tout). outl tout initial value tout initial output level 0 positive polarity (initial value) l level 1 negative polarity h level [ bit4 ] reld (reload enable) : reload operation enabling bit this bit sets reload operation in case of und erflow specified following: reld operation mode description of operation 0 one - shot mode no sooner does a counter underflow occur, than the count operation stops. reload is not performed until the next trigger is inputted. * ( i nitial value) 1 reload mode counter underflow occurs. at the same time, the contents of the reload register are loaded to the counter to continue count operation. * : however, the dual one - shot function reloads tmrlrb at the same time as tmrlra underflow and continues counting . after that, count operation stops at the same time as tmrlrb underflow. mb91590 series mn705-00009-3v0-e 696
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: r eload timer fujitsu semiconductor confidential 9 [ bit3 ] inte (interrupt enable) : interrupt request enabling bit this bit controls an interrupt request in case of underflow/compare match (event counter mode)/capture specified foll owing: inte description of operation 0 interrupt disabled (no interrupt is generated even if the uf/ef bit is set.) ( i nitial value) 1 interrupt enabled (an interrupt request is generated if the uf/ef bit is set.) [ bit2 ] uf (under flow flag) : underflow flag this flag indicates that underflow has occurred when the counter value is decreased f rom 0x0000. set factor counter underflow occurrence clear factor writing "0" to this bit or reset. [ bit1 ] cnte (timer counter enable ) : timer count enabling bit t his bit controls the operation of the timer as follows: cnte description of operation 0 operation disabled ( i nitial value) 1 operation enabled (waiting for activation trigger) [ bit0 ] trg (software trigger) : software trigger bit this bit generates a t imer software trigger. if a software trigger is generated, the contents of the reload register are loaded to the counter to initiate count operation. trg description of operation write " 0 " no influence on the operation write " 1 " a software trigger is ge nerated. when "0" is written into this bit, n o influence on the operation. the read value is always "0". trigger input through this register is effective only when bit1:cnte =1. writing "1" into the trg bit always generates an effective trigger if the timer is activated (bit1:cnte=1) in any operation mode. mb91590 series mn705-00009-3v0-e 697
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 10 4.2. 16-bit timer register : tmr (16bit timer regist er) t he bit configuration of the 16 - bit timer register is shown below . this register can read the timer count value. always perform 16 - bit access to this re gister. ? tmr : address base_addr + 02 h ( access : half - word ) bit 15 bit 14 .... bit 2 bit 1 bit 0 tmr[15:0] initial value x x .... x x x attribute r,wx r,wx .... r,wx r,wx r,wx [ bit15 to bit0 ] tmr [1 5 :0] (timer) : 16- bit timer this register can be read the counter value of the 16 - bit timer. the initial value is undefined . mb91590 series mn705-00009-3v0-e 698
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 11 4.3. 16-bit timer reload register a , 16- bit timer reload register b : tmrlra , tmrlrb(16bit timer reload register a/b) t he bit configuration of 16- bit timer reload register a and 16 - bit timer r eload register b is shown below . this register sets the count initial value and other items. always perform 16 - bit access to this register. ? tmrlra : address base_addr + 00 h ( access : half - word ) bit 15 bit 14 .... bit 2 bit 1 bit 0 tmrlra[15:0] initial valu e x x .... x x x attribute r/w r/w .... r/w r/w r/w ? tmrlrb : address base_addr + 04 h ( access : half - word ) bit 15 bit 14 .... bit 2 bit 1 bit 0 tmrlr b [15:0] initial value x x .... x x x attribute r,w r,w .... r,w r,w r,w [b it15 to bit 0] tmrlra [1 5 :0] ( timer reload register a) : 16 - bit reload setting register a [b it15 to bit 0 ] tmrlrb [1 5 :0] (timer reload register b) : 16 - bit reload setting register b the tmrlra register is where the count initial value is hold . the tmrlra can be used in all mode with reg ardless of the bit15, bit 14:mod[1:0] setting in the tmcsr register. the tmrlrb is to be used by the bit15, bit 14:mod[1:0] setting in the tmcsr register specified following : mode mod[1:0] tmrlrb functions single mode 00 not used dual mode 01 h width (when outl=0) counter value compare mode 10 compare register (when h width setting is outl=0) capture mode 11 capture register (tmr value upon retrigger input) when using as a counter value, underflow is generated if 1 count is set when writing 0x0000 and 6 5,536 is set when writing 0xffff. h width and l width of the timer output waveform (tout) are determined by the mod[1:0] (bit15, bit 14 of the tmcsr register), reld (bit4 of the tmcsr register), and outl (bit5 of the tmcsr register) bit setting as well as t he tmrlra/b register value. h width and l width setting of the waveform (tout) to be outputted is shown in the table below. mb91590 series mn705-00009-3v0-e 699
chapter 20: reload timer 4 . registers fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 12 mod[1:0] mode reld outl tout output h width l width 00 single 0 0 tmrlra+1 - 1 - tmrlra+1 1 0 tmrlra+1 1 01 dual 0 0 tmrlrb+1 tmrlra+1 1 tmrlra+1 tmrlrb+1 1 0 tmrlrb+1 tmrlra+1 1 tmrlra+1 tmrlrb+1 10 compare 0 0 see the explanation below. * 1 1 0 1 11 capture 0 0 tmrlra+1 - 1 - tmrlra+1 1 0 tmrlra+1 1 *: h width and l width are as follows in the compare mode: ? when tmrlrb < tmrlra (outl=0) "l" width of tmrlra - tmrlrb + 1, "h" width of tmrlrb (outl=1) "h" width of tmrlra - tmrlrb + 1, "l" width of tmrlrb ? when tmrlrb = 0 (outl=0) "l" output fixed (outl=1) "h" output fixed ? when tmr lrb > tmrlra (outl=0) "h" output fixed (outl=1) "l" output fixed ? when tmrlrb = tmrlra (outl=0) "l" output of 1 cycle, "h" width of tmrlrb (outl=1) "h" output of 1 cycle, "l" width of tmrlrb the following formula represents the tout output time (tout) when the register is used as the single mode and dual mode in the interval time mode: tout = (setting value of this register + 1) count source cycle * : the formula described above is effective only in the interval timer mode. mb91590 series mn705-00009-3v0-e 700
chapter 20: reload timer 5 . operation fujitsu semiconductor limited cha pter: reload timer fujitsu semiconductor confidential 13 5. operation t his section explain s the operation of the reload timer. 5.1 . setting 5.2 . operation procedure 5.3 . operations o f each c ounter 5.4 . cascade input 5.5 . priority of concurrent operations mb91590 series mn705-00009-3v0-e 701
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 14 5.1. setting setting of the reload timer is shown below . the operation of thi s timer is set based on the "count source" (select in the tmcsr : csl[2:0]) and counter operation ({tmcsr : mod[1:0], tmcsr : reld}). mb91590 series mn705-00009-3v0-e 702
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 15 5.1.1. count source the c ount s ource of the reload timer is shown below . select decrement conditions of the down counter in the tmcsr : csl[2:0]. table 5-1 list o f count s ource csl[2:0] count s ource operation mode 000 division of the peripheral clock frequency by 2 (initial value ) interval timer mode 001 division of the peripheral clock frequency by 4 010 division of the periphera l clock frequency by 8 011 division of the peripheral clock frequency by 16 100 division of the peripheral clock frequency by 32 101 division of the peripheral clock frequency by 6 4 110 cascade mode (ch . 0:ttrg0, ch . 1:tout0, ch . 2:tout1, ch . 3:tout2) event counter mode 111 external event (ttrg input ) mb91590 series mn705-00009-3v0-e 703
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 16 5.1.2. timer underflow period the t imer u nderflow period is shown below . underflow is defined as counter down - counting from 0x0000. set the time ( period ) to underflow occurrence since timer count operation s tart in the reload register (tmrlra/tmrlrb). after loading to the reload register, underflow takes place if the count value reaches "reload register setting value + 1" count. the timer underflow period , tuf, in the interval timer mode can be represented as follows: tuf = peripheral clock (pclk) period prescaler division value (2 - 64) (reload register value (tmrlra/b) + 1) mb91590 series mn705-00009-3v0-e 704
chapter 20: reload timer 5 . oper ation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 17 5.1.3. trigger the trigger of the reload timer is shown below . the trigger consists of the following two types: ? software trigger ... gener ated when writing "1" to the tmcsr : trg ? external pin trigger ... inputted from the ttrg pin. the ttrg pin is used as a count source in the event counter mode. hence, a software trigger is always used. in the interval timer mode, settings are made in the tm csr register. mb91590 series mn705-00009-3v0-e 705
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 18 5.1.4. gate the g ate of the reload timer is shown below . when configuring gate input (tmcsr : gate =1) in the interval timer mode, it is possible to stop counter down counting using the ttrg external pin. table 5-2 ttrg effective level trgm[0] ttrg effective level 0 ttrg pin "l" counted only during the input period (initial value) 1 ttrg pin "h" counted only during the input period mb91590 series mn705-00009-3v0-e 706
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 19 5.1.5. counter operation selection the c ounter o peration s electi on is shown below . select the operation in case of counter underflow in the mode selection bits (bit15, bit 14:mod[1:0] of the tmcsr register) and the reload operation enabling bit (bit4:reld of the tmcsr register). for details of operation in each mode, see the section of each counter operation. table 5-3 list of counter operation mod[1:0] reld operation in case of underflow counter operation name 00 0 stop the counter with 0xffff single one - shot 1 reload tmrlra single reload 01 0 (1) reload tmrlrb (2) stop the counter with 0xffff (see ? 5.3.3 dual one - shot operation ? ) dual one - shot 1 reload tmrlra and tmrlrb in turns dual reload 10 0 stop the counter with 0xffff compare one - shot 1 reload tmrlra compare reload 11 0 stop t he counter with 0xffff capture one - shot 1 reload tmrlra capture reload mb91590 series mn705-00009-3v0-e 707
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 20 5.1.6. tout pin level setting the tout pin l evel s etting is shown below . set pin output polarity using bit5:outl bit in the tmcsr register. the relationships between events and the tout pi n in each function are as follows: a/b of the section of the uf (underflow) below indicates whether down counting underflow has occurred with a value when loading tmrlra data or tmrlrb data. cmp (compare - match) shows the timing of down counting from tmrlrb = tmr. figure 5-1 tout output change in each event (1 / 3) outl function name initial value trigger counting in progress a 0 1 a a a 0 1 a b 0 1 a b a 0 1 a 0 1 a a a 0 1 uf uf uf single one-shot function single reload function dual one-shot function dual reload function capture reload function capture one-shot function trigger wait state trigger wait state trigger wait state mb91590 series mn705-00009-3v0-e 708
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 21 figure 5-2 tout output change in each event (2 / 3) figure 5-3 tout output change in each event (3 / 3) function name counting in progress initial value trigger counting in progress outl a 0 1 a 0 1 a 0 1 a 0 1 compare one-shot function (tmrlrb > tmrlra) compare one-shot function (tmrlrb = 0) compare reload function (tmrlrb > tmrlra) compare reload function (tmrlrb = 0) trigger wait state trigger wait state uf h clip h clip l clip l clip function name counting in progress initial value trigger counting in progress outl a 0 1 a 0 1 a 0 1 a 0 1 uf cmp cmp compare one-shot function (tmrlrb < tmrlra) compare one-shot function (tmrlrb = tmrlra) compare reload function (tmrlrb < tmrlra) compare reload function (tmrlrb = tmrlra) trigger wait state trigger wait state 1 count 1 count 1 count mb91590 series mn705-00009-3v0-e 709
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 22 5.2. operation procedure operation p rocedures are shown. 5.2.1 . activation 5.2.2 . retrigger 5.2.3 . underflow/reload 5.2.4 . generation of interrupt requests 5.2.5 . concurrent operation of register write and a timer activation mb91590 series mn705-00009-3v0-e 710
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 23 5.2.1. activation activation is shown below . writing "1" into the bit1:cnte bit of the tmcsr register changes the counter state to activation trigger waiting. ? ttrg input during trigger input functioning if writing "1" to the bit0:trg bit of the tmcsr register or inputting external trigger through ttrg input takes place during activation trigger waiting, the prescaler will be cleared and the timer will load a value from t he reload register to start down count operation. for ttrg, input pulse of 2 t (t indicates the peripheral clock (pclk) cycle) or more. ? ttrg input during gate input functioning if writing "1" to the bit0:trg bit of the tmcsr register during activation tr igger waiting, the prescaler will be cleared and the timer will load a value from the reload register and change the state to effective input polarity waiting. if there is any gate input with effective polarity from ttrg input in the effective input polari ty waiting, the timer initiates down count operation. for ttrg, input pulse of 2 t (t indicates the peripheral clock (pclk) cycle) or more. mb91590 series mn705-00009-3v0-e 711
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 24 figure 5-4 timer activation peripheral clock cnte (register) peripheral clock cnte (register) trg (register) ttrg (pin) ttrg (pin ) prescaler clear prescaler clock data load reload data reload data timer activation (when the trigger input function and the rising edge trigger are selected) timer activation (when in the gate input function) - 1 - 1 - 1 - 1 - 1 coun ter value prescaler clear prescaler clock data load counter value ttrg pin effective edge mb91590 series mn705-00009-3v0-e 712
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 25 5.2.2. retrigger the r etrigger is explained . the trigger which is generated during timer counting is called "retrigger". in this case, the following actions are taken: 1. initialize tout 2. load the reload register value to the counter 3. clear the 6 - bit prescaler 4. continue countin g only in the capture mode, retrigger generation transfers a value being counted to the tmrlrb to set the ef bit of the tmcsr register. note: tout is not initialized in the one shot mode at retrigger. mb91590 series mn705-00009-3v0-e 713
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 26 figure 5-5 retrigger operation tout (when outl=0) count clock ttrg(pin) trg(register) cnte(register) retrigger prescaler clear count value reload data - 1 - 1 - 1 - 1 - 1 - 1 reload data retrigger operation (ttrg is trigger input, the rising edge trigger, one - shot output) retrigger operation (ttrg is gate input, count when in h level, one - shot output) tout (when outl=0) trg(register) count clock ttrg(pin) cnte(register) trigger retrig ger prescaler clear ttrg pin effective edge count value reload data - 1 - 1 reload data - 1 - 1 - 1 one - shot mode one - shot mode mb91590 series mn705-00009-3v0-e 714
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 27 5.2.3. underflow/reload underflow/ r eload is shown below . underflow is defined as the timer down - counting from 0x0000. when underflow occurs, the bit2:uf bit of the tmcsr register is set. u nderflow takes place in the timer if the count value reaches "reload register setting value + 1" count. mb91590 series mn705-00009-3v0-e 715
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 28 5.2.4. generation of interrupt requests generation of i nterrupt r equests is shown below . when bit3:inte bit of the tmcsr register is "1", if bit2:uf bit/bit7: ef bit are set, an interrupt request is generated. in interval timer mode, the uf bit and the ef bit will be set under the following conditions. ? uf bit is set: a counter underflow occurred ? ef bit is set: a capture input occurred in capture mode when a set of bit2:uf bit of the tmcsr register and a clear of the uf bit by writing "0" occurred concurrently, writing "0" to the uf bit will be invalid and the uf bit will be set. when a set of bit7:ef bit and a clear of the ef bit by writing "0" occurred concurre ntly, writing "0" to the ef bit will be invalid and the ef bit will be set. the following is the example of generation of interrupt requests. figure 5-6 example of uf interrupt request output operation count clock counter value underflow interrupt request uf bit uf interrupt request output operation (bit4:reld= "1" and bit3:inte="1" of tmcsr register) reload data -1 0x0000 0x0001 -1 -1 mb91590 series mn705-00009-3v0-e 716
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 29 5.2.5. concurrent operation of register write and a timer activation the c oncurrent o peration of r egister w rite and a t imer a ctivation is shown below . the foll owing table shows the operation when a register write by a user and the timer operation occurred simultaneously. table 5-4 concurrent operation writing to register operation of timer operation to execute a clear of the uf bit by writing "0" setting of the uf bit setting of the uf bit (writing "0" is ignored) a clear of the ef bit by writing "0" setting of the ef bit setting of the ef bit (writing "0" is ignored) writing to the reload register l oading of timer by retrigger reloading old data (the written value will be loaded next time) mb91590 series mn705-00009-3v0-e 717
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 30 5.3. operations of each c ounter operations of each c ounter are shown. 5.3.1 . single one - shot operation 5.3.2 . single reload operation 5.3.3 . dual one - shot operation 5.3.4 . dual reload operation 5.3.5 . compare one - shot operation 5.3.6 . compare reload operation 5.3.7 . capture mode mb91590 series mn705-00009-3v0-e 718
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 31 5.3.1. single one - shot operatio n the s ingle o ne- shot o peration is shown below . when bit15, bit 14:mod[1:0]=00 and bit4:reld of the tmcsr register =0, the single one - shot operation will be performed in which the timer stops with 0xffff by an occurrence of an underflow. in the single one -s hot configuration, if an underflow occurs, the following operation will be performed. ? sets the uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? stops the count with 0xffff. ? initializes tout out put. ? timer is waiting for a trigger. for the single one - shot timer, tmrlra turns to the initial value of the counter when a reload took place. tmrlrb is not used. mb91590 series mn705-00009-3v0-e 719
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 32 figure 5-7 single one - shot operation 0x0001 0xffff 0x0000 tmrlra -1 -1 count clock ttrg(pin) ttrg pin effective edge counter value underflow uf bit reload count operation waiting for activation trigger tout (when outl=0) details of underflow operation (when the trigger input and rising edge trigger are selected) tmrlra+1 count ttrg(pin) cnte(register) ttrg pin effective edge underflow count operation waiting for activation trigger tout (when outl=0) single one-shot timer (gate="1": gate input, trgm:h input interval count) single one-shot timer (gate="0": when the trigger input and rising edge trigger are selected) ttrg(pin) trg(register) cnte(register) underflow tout (when outl=0) waiting for activation trigger count operation waiting for effective gate input tmrlra+1 count tmrlra+1 count mb91590 series mn705-00009-3v0-e 720
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 33 5.3.2. single reload operation the s ingle reload o peration is shown below . when bit15, bit 14:mod[1:0] of the tmcsr register =00, and bit4:reld of the tmcsr register =1, the single reload operation will be performed. in single reload operation, a value will be loaded from tmrlra to the timer by trigger input, a down count (decrementing the count) will start. when an underflow occurs, the value is reloaded from tmrlra again and the down count operation continues. the value of tmrlra represents the time the timer will reload. the tmrlrb register is not used. in single reload configuration, if an underflow occurs, the following operation will be performed. ? sets bit2:uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? loads tmrlra register onto the counter. ? inverts tout output. ? continues decrementing count. mb91590 series mn705-00009-3v0-e 721
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 34 figure 5-8 single reload operation tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra+1 count tmrlta+1 count tmrlta+1 count tmrlta+1 count tmrlta+1 count tmrlta+1 count tmrlta+1 count tmrlra+1 count tmrlra+1 count tmrlra+1 count tmrlra+1 count tmrlra+1 count tmrlra+1 count underflow timer reloaded register timer loaded register uf bit count operation waiting for activation trigger tout (when outl=0) tout (when outl=0) trg(register) trg(register) cnte(register) cnte(register) data load data load single reload function (gate="0": trigger input) single reload function (gate="1": gate input, trgm: h input interval count) underflow uf bit ttrg(pin) waiting for activation trigger count operation waiting for effective gate input mb91590 series mn705-00009-3v0-e 722
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 35 5.3.3. dual one - shot operation the d ual one- shot o peration is shown below . when bit15, bit 14:mod[1:0] of the tmcsr register =01, and bit4:reld of the tmcsr register =0, the timer perfo rms the dual one - shot operation. this can be used as a one - shot ppg. in dual one - shot operation, values are loaded into the counter one by one in the order of tmrlra then tmrlrb, the loaded values decrements the counter for each load. the counter will stop by the second underflow. when bit5:outl=0 of the tmcsr register, the value of tmrlra represents the time interval between a timer activation (tout output is in l level) to a toggling of the tout output to "h", and the value of tmrlrb represents the time i nterval of h width of the tout output. figure 5-9 tout pulse width when the first underflow occurs (uf - a), the following operation will take place. ? sets bit2:uf bit of the tmcsr reg ister. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? loads tmrlrb to the counter. ? inverts tout output. ? starts a down count from tmrlrb. when the second underflow (uf - b) occurs, the following operation will take place. ? s ets bit2:uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? stops the count with 0xffff. ? initializes tout output. ? timer is waiting for an activation trigger. trigger tout external pin output delay = tmrlra h width = tmrlrb mb91590 series mn705-00009-3v0-e 723
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 36 figure 5- 10 dual one - shot operation tmrlra tmrlrb tmrlrb count tmrlrb + 1 tmrlra + 1 tmrlra + 1 tmrlrb + 1 tmrlrb + 1 tmrlra + 1 waiting for activation trigger waiting for activation trigger waiting for activation trigger waiting for activation trigger tmrlrb + 1 tmrlra tmrlrb a -1 0 b -1 -1 -1 -1 0 a -1 0 -1 -1 b 0xffff a:tmrlra b:tmrlrb uf-a uf-b uf-a tmrlra tmrlra tmrlrb a -1 0 b -1 -1 -1 -1 0 a -1 0 -1 b 0xffff a:tmrlra b:tmrlrb uf-a uf-b uf-a tout (outl=0) dual one-shot operation (gate input) dual one-shot operation ( when the trigger input and rising edge trigger are selected) count clock underflow uf bit cnte(register) count clock underflow uf bit cnte(register) trg(register) ttrg(pin) ttrg(pin) ttrg pin effective edge timer reloaded register tout (when outl=0) counter value timer reloaded register counter value tmrlra + 1 count count count count count count count mb91590 series mn705-00009-3v0-e 724
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 37 5.3.4. dual reload operation the d ual one- shot o peration is shown below . when bit15, bit 14:mod[1:0] of the tmcsr register =01, and bit4:reld of the tmcsr register =1, the timer perfor ms the dual reload operation. in dual reload operation, the values of tmrlra and tmrlrb are loaded alternatively and decrement the counters for each load, that is, loads tmrlra onto the counter and decrements the counter, and if an underflow occurs, loads tmrlrb onto the counter and decrement the counter, and if an another underflow occurs, loads tmrlra onto the counter and decrements the counter, and so on. when bit5:outl=0 of the tmcsr register, the value of tmrlra represents the time interval between a t imer activation (tout output is in l level) to a toggling of the tout output to "h", and the value of tmrlrb represents the time interval of h width of the tout output. if an underflow (uf - a) occurs at the down count after loading a value from the tmrlra, the following operation will be performed. ? sets bit2:uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? loads tmrlrb to the counter. ? inverts tout output. ? starts a down count from tmrlrb. if an u nderflow (uf - b) occurs at the down count after loading a value from the tmrlrb, the following operation will be performed. ? sets bit2:uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? loads tmrlr a to the counter. ? inverts tout output. ? starts a down count from tmrlra. mb91590 series mn705-00009-3v0-e 725
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 38 figure 5- 11 dual reload operation ab b a b a a b a:tmrlra b:tmrlrb a uf-a uf-a uf-a uf-a uf-b uf-b uf-b count from tmrlra count from tmrlrb a a a b b b a:tmrlra b:tmrlrb t out (when outl=0) a uf-a uf-a uf-a uf-b uf-b count from tmrlra count from tmrlrb underfl ow uf bit cnte(register) cnte(register) trg(register) data load w aiting f or acti v ation t r igger data load w aiting f or acti v ation t r igger w aiting f or ef f ecti v e gate input trg(register) ttrg(pin) t out (when outl=0) timer reloaded register underfl ow uf bit timer reloaded register dual reload function (g a te=0 : t r igger input) dual reload function (g a te=1 : gate input, h input inte rv al count) mb91590 series mn705-00009-3v0-e 726
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 39 5.3.5. compare one - shot operation the c ompare one - shot operation is shown below . when bit15, bit 14:mod[1:0] of the tmcsr register =10, and bit4:reld of the tmcsr register =0, the compar e one - shot operation in which the counter value (tmr) and the value of tmrlrb register are compared for each down count will be performed. after accepting a trigger, the value of the tmrlra register is loaded and the down count starts. when decrementing th e count from the value of a compare matched (tmr = tmrlrb), the tout output will be inverted. when an underflow occurs, count operations stopped, tout output is initialized, and the timer go into the activation trigger wait state. the value of tmrlra indic ates the time interval between the activation of a timer and the end of it and the value of tmrlrb indicates the counter value when an output of the h width of tout output starts. when outl="0" and tmr < tmrlrb, the tout output will become the "h level". figure 5- 12 tout interval, pulse width from the start of a down count to tmr = tmrlrb (while tmr is greater than or equal to tmrlrb), the following operation will be performed. ? tout output continues to hold the i nitial value. ? the timer continues to count. ? if a down count from tmr = tmrlrb occurs, the following operation will be performed. ? inverts tout output. ? the timer continues to count. (for the compare operation in interval timer mode, bit7:ef bit of tmcsr register will not be set.) if an underflow occurs, the following operation will be performed. ? sets bit2:uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? initializes tout output. ? the timer stops wit h 0xffff. ? timer is waiting for an activation trigger. the operation of the compare function changes depending on the setting relation between tmrlra and tmrlrb. trigger input tout external pin o utput cycle = tmrlra h width = tmrlrb mb91590 series mn705-00009-3v0-e 727
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: relo ad timer fujitsu semiconductor confidential 40 figure 5- 13 compare one - shot operation (1 / 2) when the register relation is as described above, the tout output is the l level until tmr and tmrlrb match after loading to the timer. when down counting from the comparison match (tmr = tmrlrb), the level is h until t he tout output is inverted and an underflow occurs. when an underflow occurs the tout output will be initialized. then, the timer will stop counting operation and turn into the activation trigger waiting state (for outl="0"). when the register relation is as described above, the tout output is the h level between an activation trigger generation and an underflow occurrence because tmr is already smaller than tmrlrb after loading to the timer. when an underflow occurs, the timer will turn into the activation trigger waiting state and the tout output will be the l level (for outl="0"). ? sets tmrlrb < tmrlra tout tout count clock count clock underflow underflow uf bit reload activation trigger activation trigger counting from register reloaded register reloaded tmrlra + 1 count count activation trigger waiting activation activation tmrlrb tmrlra tmrlra compare one-shot function (tmrlrb < tmrlra) ? sets tmrlrb > tmrlra tmrlra tmrlra tmrlra+1 tmrlra+1 compare one-shot function (tmrlrb > tmrlra) (for outl=0) comparison match by timer by timer (for outl=0) trigger waiting trigger waiting mb91590 series mn705-00009-3v0-e 728
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 41 figure 5- 14 compare one - shot operation (2 / 2) (for outl=0) tout (for outl=0) count clock count clock underflow underflow activation activation activation trigger waiting activation trigger waiting activation trigger waiting 1 count 1 count register reloaded register reloaded trigger waiting ? sets tmrlrb = tmrlra tmrlra tmrlra tmrlra+1 tmrlra+1 compare one - shot function (tmrlrb=tmrlra) ? sets tmrlrb = 0 tmrlra tmrl ra tmrlra+1 tmrlra+1 h l compare one - shot function (tmrlrb="0") by timer by timer trigger trigger activation trigger waiting activation tout when the register relation is as described above, tmrlrb will become bigger than tmr after 1 count. thus the tout output is the l level for 1 down count and then the h level until an underflow occurs. when an underflow occurs, the timer will turn into the activation trigger waiting state and the tout output will be the l level (for outl="0"). when the register relation is as described above, the tout output is the l level between down count start and an underflow occurrence because tmrlrb is always smaller than tmr. the level will remain to be l even when an underflow occurs (for outl="0"). mb91590 series mn705-00009-3v0-e 729
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 42 5.3.6. compare reload operation the c ompare reload operation is shown below . when bit15, bit 14:mod[1:0] of the tmc sr register =10, and bit4:reld of the tmcsr register =1, the timer compares a counter value (tmr) to the value of tmrlrb for each down count and if a compare matched (tmr = tmrlrb) is detected, a down count starts and the tout output will be inverted. when an underflow occurs, the compare reload operation will be performed, in which a value is loaded from tmrlra again and the down count operation starts. a load onto the counter starts from tmrlra. the value of tmrlra indicates the counter interval from a timer activation until a reload and the value of tmrlrb indicates the "h level width" after the tout output inverted from "l level output" to "h level output". when tmr + 1 = tmrlrb, tout output will invert to the "h level" (when outl=0). figure 5- 15 tout interval, pulse width from the start of a down count to tmr = tmrlrb (while tmr is greater than or equal to tmrlrb), the following operation will be performed. ? tout output continues to hold the i nitial value. ? count continues when a down count starts from tmr = tmrlrb, the following operation will be performed. ? inverts tout output. ? count continues. (for the compare operation in interval timer mode, bit7:ef bit of tmcsr register will not be set.) i f an underflow occurs, the following operation will be performed. ? sets bit2:uf bit of the tmcsr register. ? when interrupts are enabled (bit3:inte=1 of tmcsr register), an interrupt occurs. ? initializes tout output. ? reloads a value from tmrlra. ? the timer cont inues to count. the operation of a compare feature depends on the relationship between tmrlra and tmrlrb. tout external pin output cycle = tmrlra h width = tmrlrb mb91590 series mn705-00009-3v0-e 730
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 43 figure 5- 16 compare reload operation (1 / 2) tmrlra + 1 tmrlrb tmrlra + 1 tmrlrb tmrlra + 1 tmrlrb tmrlra tmrlra tmrlra tmrlra tmrlra tmrlra+1 tmrlra+1 tmrlra tmrlra+1 ? sets tmrlrb < tmrlra tout tout count clock count clock underflow underflow uf bit uf bit ef bit reload activation trigger counting from register register count count count count count count compare reload function (tmrlrb < tmrlra) trigger input ? sets tmrlrb > tmrlra compare reload function (tmrlrb > tmrlra) trigger input (for outl=0) comparison match reloaded by timer reloaded by timer (for outl=0) when the register relation is as described above, the tout output is the l level until tmr and tmrlrb match after loading to the timer. when down counting from the comparison match (tmr=tmrlrb), the level is h until the tout output is inverted and an underflow occurs. when an underflow occurs the tout output will be initialized. when an under flow occurs, the timer will reload from tmrlra and c ontinue counting operation (for outl="0"). when the register relation is as described above, the tout output is the h level after an activation trigger is generated and an underflow occurs because tmr is always smaller than tmrlrb. the level will remain to be h even when an underflow occurs. when an underflow occurs, the timer will load from tmrlra and continue counting operation (for outl="0"). mb91590 series mn705-00009-3v0-e 731
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapt er: reload timer fujitsu semiconductor confidential 44 figure 5- 17 compare reload operation (2 / 2) when the register relation is as described above, 1 count up after loading to the timer makes tmrlrb become bi gger than tmr. thus the tout output is the l level for 1 down count and then the h level until an underflow occurs. when an underflow occurs, the timer will reload from tmrlra and continue counting operation. the tout output will remain to be the l level. (for outl=0) when the register relation is as described above, the tout output is the l level between down count start and an underflow occurrence after loading to the timer because tmrlrb is smaller than tmr. the level will remain to be l even when an underflow occurs. tmrlra tmrlra tmrlra l tmrlra+1 tmrlra+1 tmrlra+1 tmrlrb tmrlrb tmrlrb tmrlra tmrlra tmrlra+1 tmrlra+1 tmrlra+1 tmrlra h l tout tout count clock count clock underflow down count from underflow uf bit uf bit ef bit activation trigger activation trigger 1 count 1 count 1 count 1 count register register ? sets tmrlrb = tmrlra compare reload function (tmrlrb = tmrlra) trigger input ? sets tmrlrb = 0 compare reload function (tmrlrb = "0") trigger input reloaded by timer (for outl=0) comparison match reloaded by timer (for outl=0) mb91590 series mn705-00009-3v0-e 732
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 45 5.3.7. capture mode the c apture m ode is shown below . when bit15, bit 14:mod[1:0] of the tmcsr register =11, the timer will perform capture operation. when a retrigger occurs , tmrlrb register captures the tmr value and sets bit7:ef of the tmcsr register. when you use ttrg input as the gate input (when bit8:gate=1 of the tmcsr register), generate a retrigger by bit0:trg of the tmcsr register. in a mode other than trigger, a capture will not be performed at a retrigger. the ef bit interrupt will also not be generated. the timer operation and the tout output will be the same for the single one - shot feature and the single reload feature. note: tout is not initialized in the one shot mode at retrigger. figure 5- 18 operation of capture 0 counter value trigger input retrigger input underflow underflow capture tmr to tmrlrb uf interrupt & reload (tmrlra) ef interrupt & capture (tmrlrb) & reload (tmrlra) tmrlra mb91590 series mn705-00009-3v0-e 733
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 46 figure 5- 19 flowchart of trigger input features in interval timer mode cnte=1? reld = 1? no no no no no yes yes yes yes ga te=0 and csl[2:0]=000 to 101 trg=1 or ttrg ef f ecti v e edge input reloads to the timer clo ck? count-1 underfl o w occurs? mb91590 series mn705-00009-3v0-e 734
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 47 figure 5- 20 flowchart in event counter mode cnte=1? csl [2:0] = 111 reld = 1? no no no no no yes yes yes yes trg=1? yes loads to the counter valid event input? count-1 underflow occurs? mb91590 series mn705-00009-3v0-e 735
chapter 20: reload timer 5 . operat ion fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 48 5.4. cascade input cascade i nput is shown below . when you select cascade input (bit11 to bit 9:csl[2:0]=110 of tmcsr re gister), you can use the timer's ch.0 output (tout0) for the input for ch.1 (ttrg1), ch.1 output (tout1) for the input for ch.2 (ttrg2), and ch.2 output (tout2) for the input for ch.3 (ttrg3). figure 5- 21 timer i nput/output in cascade input configuration timer ch.0 timer ch.1 (1) using ch.1 in cascade settings tot0 tin1 timer ch.1 timer ch.2 (2) using ch.2 in cascade settings tot1 tin2 timer ch.2 timer ch.3 (3) using ch.3 in cascade settings tot2 tin3 mb91590 series mn705-00009-3v0-e 736
chapter 20: reload timer 5 . operation fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 49 5.5. priority of concurrent operations the p riority of c oncurrent o perations is shown below . when two events to decide the timer operation occur simultaneously, t he priority of deciding th e operating state is indicated. 1. writing to register 2. trigger input 3. underflow 4. clock input when a set of each flag by the timer operation and a clear of a flag by register write occur concurrently, t he priority of deciding the operatiin is indicated. 1. setting flag by the timer operation 2. writing to a register for a clear of flag to the uf bit/ef bit mb91590 series mn705-00009-3v0-e 737
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 50 6. application note an a pplication n ote is shown below . this section shows the typical functions which can be realized with this timer. figure 6-1 example following are some configurations for use of example figure above. ppg ppg pwm pwc (reload input capture) (reload output compare) tout output (dual reload timer) tout output (dual one-shot timer) tout output reload timer tout output single one-shot timer tout output ttrg input counter value tmrlrb register tmrlra cnt_a cnt_b cnt_a tmrlra0 cnt_b tmrlra tmrlra reload reload reload activation trigger capture input (ttrg effective edge) underflow note: when the rising edge is specified as effective edge downcount from tmrlra interrupt can be generated ( set uf bit ) interrupt can be generated ( set ef bit ) activation trigger retrigger underflow compare match capture to the tmlrb downcount from tmrlra downcount from tmrlrb interrupt can be generated(set uf bit) 0 mb91590 series mn705-00009-3v0-e 738
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 51 table 6-1 example of configuration function mod[1:0] reld tmrlra tmrlrb single one - shot timer 00 ( single mode ) 0 mandatory - reload timer 00 ( single mode ) 1 mandatory - ppg (programmable pulse generator) 01 ( dual mode ) 0 or 1 mandatory mandatory pwm (pulse width modulator) 10 ( compare mode ) 1 mandatory mandatory pwc (pulse width counter) 11 ( capture mode ) 1 mandatory - mb91590 series mn705-00009-3v0-e 739
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 52 6.1. single one - shot timer the s ingle o ne- shot t imer is shown below . the single one - shot timer loads a value from the tmrlra register onto the counter and starts to decrement the counter (down count operation) when a t rigger is input. when an underflow occurs, the counting stops. the tout pin outputs the "h level" in counting and when an underflow occurs it will output the "l level". (when outl=0) [configuration] to use this timer as a single one - shot timer, configure a s follows. 1. when ttrg input is not used tmcsr tmrlra mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg count initial value setting 00 00 * 1 0 - * 2 0 * 3 - 1 s s : use at timer activation -: does not influence operation *1 : count clock divi sion setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *2 : tout output polarity setting outl=0 ------ initial value l=> count starts h=> underflow occurs l outl=1 ------ initial value h=> count starts l=> underflow occurs h *3 : interrupt request enab le setting inte=0------ interrupt disabled inte=1------interrupt enabled mb91590 series mn705-00009-3v0-e 740
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 53 2. when using ttrg input as a gate input tmcsr tmrlra mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg count initial value setting 00 * 1 * 2 1 - * 3 0 * 4 - 1 s s :u se at timer activation -: does not influence operation *1 : ttrg effective level setting trgm[1:0]=x0 ------ count only for l input interval trgm[1:0]=x1 ------ count only for h input interval *2 : count clock division setting csl[2:0]= 000 ------ division of peri pheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clo ck (pclk) by 64 *3 : tout output polarity setting outl= 0 ------ initial value l=> count starts h=> underflow occurs l outl= 1 ------ initial value h=> count starts l=> underflow occurs h *4 : interrupt request enable setting inte= 0 ------ interrupt disabled in te= 1 ------ interrupt en abled 3. when using ttrg input as a trigger input tmcsr tmrlra mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg count initial value setting 00 * 1 * 2 0 - * 3 0 * 4 - 1 s s : use at timer activation -: does not influence operation *1 : ttrg effective level setting trgm[1:0]= 00 ------ does not detect external trigger edge trgm[1:0]= 01 ------ rising edge trgm[1:0]= 10 ------ falling edge trgm[1:0]= 11 ------ both edges *2 : count clock division setting csl[2:0]= 000 ------ divisi on of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peri pheral clock (pclk) by 64 *3 : out output polarity setting outl= 0 ------ initial value l=> count starts h=> underflow occurs l outl= 1 ------ initial value h=> count starts l=> underflow occurs h *4 : interrupt request enable setting inte= 0 ------ interrupt dis abled inte= 1 ------ interrupt en abled [timer activation] follow the steps below to activate the timer. mb91590 series mn705-00009-3v0-e 741
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 54 ? input an activation trigger (a write of "1" to the trg bit or a n input of effective external edge from ttrg pin) ? input an effective level when you use ttrg pin input as the gate input figure 6-2 example of operation (outl = 0) tout (tm r lra + 1) counter value tmrlra 0x 0000 0xffff activation trigger underflow downcount mb91590 series mn705-00009-3v0-e 742
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 55 6.2. reload timer the r eload time is shown below . the reload timer loads from the tmrlra register onto the counter and repeats the down count operation each time underflow occ urs. the tout outputs the "l level" while the count is going on from the activation trigger to the occurrence of the first underflow, then the output will be inverted to the "h level" at the timing of the occurrence of the first underflow, inverting the ou tputs whenever an underflow occurs. when a retrigger occurs, tout output returns to its initial value. (when outl=0) [configuration] to use the timer as the reload timer, configure as follows. 1. when ttrg input is not used tmcsr tmrlra mod [1:0] trgm [1:0 ] csl [2:0] g at e ef outl reld inte uf cnte trg count initial value setting 00 00 * 1 0 - * 2 1 * 3 - 1 s s : use at timer activation -: does not influence operation *1 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *2 : tout o utput polarity setting outl=0 ------ initial value l=> count starts l=> invert whenever an underflow occurs outl=1 ------ initial value h=> count starts h=> invert whenever an underflow occurs *3 : interrupt request enable setting inte=0------ interrupt disabl ed inte=1------interrupt enabled mb91590 series mn705-00009-3v0-e 743
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 56 2. when using ttrg input as a gate input tmcsr tmrlra mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg count initial value setting 00 * 1 * 2 1 - * 3 1 * 4 - 1 s s : use at timer activation -: does not influe nce operation *1 : ttrg effective level setting trgm[1:0]=x0 ------ count only for ttrg=l input interval trgm[1:0]=x1 ------ count only for ttrg=h input interval *2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[ 2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *3 : out output polarity setting outl=0 ------ initial value l=> count starts l=> invert whenever an underflow occurs outl=1 ------ initial value h=> count starts h=> invert whenever an underflow occurs *4 : interrupt request enable setting inte=0------ interrupt disabled in te=1 ------interrupt enabled 3. when using ttrg input as a trigger input tmcsr tmrlra mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg count initial value setting 00 * 1 * 2 0 - * 3 1 * 4 - 1 s s : use at timer activation -: does not influence operation *1 : ttrg effective edge setting trgm[1:0]= 00 ------ does not detect external trigger edge trgm[1:0]= 01 ------ rising edge trgm[1:0]= 10 ------ falling edge trgm[1:0]= 11 ------ both edges *2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of periphe ral clock (pclk) by 64 *3 : out output polarity setting outl= 0 ------ initial value l=> count starts l=> invert whenever an underflow occurs outl= 1 ------ initial value h=> count starts h=> invert whenever an underflow occurs *4 : interrupt request enable sett ing inte= 0 ------ interrupt disabled inte= 1 ------ interrupt en abled [timer activation] follow the steps below to activate the timer. mb91590 series mn705-00009-3v0-e 744
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 57 ? input an activation trigger (a write of "1" to the trg bit or a n input of effective external edge from ttrg pin) ? input an effective level when you use ttrg pin input as the gate input figure 6-3 example of operation ( outl=0 ) tout (t mrlr a + 1) (t mrlr a + 1) counter value tmplra 0x0000 tmrlra 0x00 00 tmrlra activation trigger underflow downcount mb91590 series mn705-00009-3v0-e 745
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 58 6.3. ppg ppg is shown below . ppg is the feature which generates an output pulse by configuring l width/h width of the pulse. an activation trigger launches a load from tmrlra to the counter and the operation switches to load the value from tmrlrb and executes a down count when an underflow occurs. when reld=0, "activation trigger => tmrl ra load => down count => underflow => tmrlrb load => down count => underflow," then stops the down count. when reld=1, counter is loaded with tmrlra/tmrlrb alternatively and executes down count whenever an underflow occurs, such as activation trigger => tmr lra load => down count => u nderflow => tmrlrb load => down count => u nderflow => tmrlra load => down count => u nderflow => tmrlrb load and so on. the tout outputs the "l level" while counting until the occurrence of an underflow caused by the down count fr om tmrlra, and outputs the "h level" while counting until the occurrence of an underflow caused by the down count from tmrlrb. when a retrigger occurs, tout output returns to its initial value. note: tout is not initialized in the one shot mode at retrigg er. mb91590 series mn705-00009-3v0-e 746
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 59 [configuration] to use the timer as ppg, configure as follows. 1. when ttrg input is not used tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg (a) (b) 01 00 * 1 0 - * 2 * 3 * 4 - 1 s (a): the count initial value at an activation trigger/the reload value at an underflow caused by the count from the tmrlrb value (when reld=1) (b): the reload value at an underflow caused by the count from the tmrlra value s : use at timer activation -: does not influence operation * 1 : co unt clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral cl ock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 * 2 : tout output polarity setting outl= 0 ------ initial value l => count l from tmrlra => h when an underflow occurs => count h from tmrlrb => l when an underflow occurs ou tl= 1 ------ initial value h => count h from tmrlra => l when an underflow occurs => count l from tmrlrb => h when an underflow occurs *3 : reload setting when an underflow occurs reld= 0 ------ one - shot mode reld= 1 ------ reload mode *4 : interrupt request enable setting inte= 0 ------ interrupt disabled inte= 1 ------ interrupt en abled 2. when using ttrg input as a gate input tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg (a) (b) 01 * 1 * 2 1 - * 3 * 4 * 5 - 1 s (a): the c ount initial value at an activation trigger/the reload value at an underflow caused by the count from the tmrlrb value (when reld=1) (b): the reload value at an underflow caused by the count from the tmrlra value s : use at timer activation -: does not inf luence operation mb91590 series mn705-00009-3v0-e 747
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 60 * 1 : ttrg effective level setting trgm[1:0]= x0 ------ count only for ttrg=l input interval trgm[1:0]= x1 ------ count only for ttrg=h input interval * 2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 * 3 : tout output polarity setting outl= 0 ------ initial value l=> count l from tmrlra => h when an underflow occurs => count h from tmrlrb => l when an underflow occurs outl= 1 ------ initial value h=> count h from tmrlra => l when an underflow occurs => count l from tmrlrb => h when an underflow occurs *4 : reload setting when an underflow occurs reld=0------ one - shot mode reld=1------ reload mode *5 : interrupt request enable setting inte=0------ interrupt disabled inte=1------interrupt enabled mb91590 series mn705-00009-3v0-e 748
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 61 3. when using ttrg input as a trigger input tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg (a) (b) 01 * 1 * 2 0 - * 3 * 4 * 5 - 1 s (a): the count initial value at an activation trigger/the reload value at an underflow caused by t he count from the tmrlrb value (when reld=1) (b): the reload value at an underflow caused by the count from the tmrlra value s : use at timer activation -: does not influence operation *1 : ttrg effective edge setting trgm[1:0]= 00 ------ does not detect extern al trigger edge trgm[1:0]= 01 ------ rising edge trgm[1:0]= 10 ------ falling edge trgm[1:0]= 11 ------ both edges *2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (p clk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *3 : tout output polarity setting outl= 0 ------ initial value l=> count l from tmrlra => invert whenever an underflow occurs outl= 1 ------ initial value h=> count h from tmrlra => invert whenever an underflow occurs *4 : reload setting when an underflow occurs reld=0------ one - shot mode reld=1------ reload mode *5 : inte rrupt request enable setting inte=0------ interrupt disabled inte=1------interrupt enabled [timer activation] follow the steps below to activate the timer. ? input an activation trigger (a write of "1" to the trg bit or a n input of effective external edge f rom ttrg pin) ? input an effective level when you use ttrg pin input as the gate input figure 6-4 example of operation (outl=0) tout (t mr lr a + 1) (tm rl rb + 1) counter value tmplra 0000 tmrlrb 0 x0000 tmrlra activation trigger underflow downcount mb91590 series mn705-00009-3v0-e 749
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 62 6.4. pwm pwm is shown below . pwm is the feature which generates an output pulse by configuring the pulse interval and h width. an activation trigger launches a load from tmrlra to the counter and executes a down count. tout outputs the "l level" after an activation trigger and then outputs the "h level" when the counter value becomes smaller than the tmrlrb value. when an underflow occurs, tout output returns to its initial valu e. (when outl=0) when reld=0, "activation trigger => tmrlra load => down count => underflow, then counter stops the down count. when reld=1, counter is loaded with tmrlra, and it is decremented for each load whenever an underflow occurs, such as activation trigger => tmrlra load => down count => underflow => t mrlra load => down count, and so on. [configuration] to use the timer as pwm, configure as follows. 1. when ttrg input is not used tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg (a) (b) 10 0 * 1 0 - * 2 * 3 * 4 - 1 s (a): the count initial value when activation trigger occurs/the reload value at an underflow (when reld=1) (b): set the value to compare to the counter value (tmrlrb < tmrlra) *5 s : use at timer activation -: does not influence operation *1 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *2 : tout output polarity setting outl= 0 ------ initial value l=> count l from tmrlra => h, the counter value is smaller than tmrlrb outl= 1 -- ---- initial value h=> count h from tmrlra => l, the counter value is smaller than tmrlrb *3 : reload setting when an underflow occurs reld= 0 ------ one - shot mode reld= 1 ------ reload mode *4 : interrupt request enable setting inte= 0 ------ interrupt disabled inte= 1 ------ interrupt en abled *5 : to use tout output with l clip output, set to tmrlrb = 0. to use tout output with h clip output, set to tmrlrb = "tmrlra + 1". 2. when using ttrg input as a gate input mb91590 series mn705-00009-3v0-e 750
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 63 tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2: 0] g at e ef outl reld inte uf cnte trg (a) (b) 10 * 1 * 2 1 - * 3 * 4 * 5 - 1 s (a): the count initial value when activation trigger occurs/the reload value at an underflow (when reld=1) (b): set the value to compare to the counter value ( tmrlrb < tmrlra ) *6 s : use at timer activation -: does not influence operation *1 : ttrg effective level setting trgm[1:0]= x0 ------ count only for trgm=l input interval trgm[1:0]= x1 ------ count only for trgm= h input interval *2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division o f peripheral clock (pclk) by 64 *3 : tout output polarity setting outl= 0 ------ initial value l=> count l from tmrlra => h, the counter value is smaller than tmrlrb outl= 1 ------ initial value h=> count h from tmrlra => l , the counter value is smaller than tmrlrb *4 : reload setting when an underflow occurs reld=0------ one - shot mode reld=1------ reload mode *5 : interrupt request enable setting inte=0------ interrupt disabled inte=1------interrupt enabled *6 : to use tout output with l clip output, set to tmrlr b = 0. to use tout output with h clip output, set to tmrlrb = "tmrlra + 1". mb91590 series mn705-00009-3v0-e 751
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: re load timer fujitsu semiconductor confidential 64 3. when using ttrg input as a trigger input tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg (a) (b) 10 * 1 * 2 0 - * 3 * 4 * 5 - 1 s (a): th e count initial value when activation trigger occurs/the reload value at an underflow (when reld=1) (b): set the value to compare to the counter value (tmrlrb < tmrlra) *6 s : use at timer activation -: does not influence operation *1 : ttrg effective edge set ting trgm[1:0]= 00 ------ does not detect external trigger edge trgm[1:0]= 01 ------ rising edge trgm[1:0]= 10 ------ falling edge trgm[1:0]= 11 ------ both edges *2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl [2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *3 : tout outpu t polarity setting outl= 0 ------ initial value l=> count l from tmrlra => h, the counter value is smaller than tmrlrb outl= 1 ------ initial value h=> count h from tmrlra => l, the counter value is smaller than tmrlrb *4 : reload setting when an underflow o ccurs reld= 0 ------ one - shot mode reld= 1 ------ reload mode *5 : interrupt request enable setting inte= 0 ------ interrupt disabled inte= 1 ------ interrupt en abled *6 : to use tout output with l clip output, set to tmrlrb = 0. to use tout output with h clip output, set to tmrlrb = "tmrlra + 1". [timer activation] follow the steps below to activate the timer. ? input an activation trigger (a write of "1" to trg bit or a n input of effective external edge from ttrg pin) ? input an effective level when you use ttrg pin input as the gate input figure 6-5 example of operation (outl=0) tout tm rlr b + 1 tmrlra + 1 counter value tm rlra tm rlrb 0 000 t mrlra : activation trigger : compare-match : underflow : downcount mb91590 series mn705-00009-3v0-e 752
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 65 6.5. pwc pwc is shown below . pwc is the feature to measure the time interval between triggers to input. an activation trigger launches a load of a value from tmrlra onto the counter and executes a down count operation. a trigger input during a count enables the counter value at that time to be captured onto tmrlrb, which allows measuring the time interval between triggers to input. [configuration] to use the timer as pwc, configure as follows. tmcsr tmrlra tmrlrb mod [1:0] trgm [1:0] csl [2:0] g at e ef outl reld inte uf cnte trg (a) (b) 11 * 1 * 2 0 - * 3 * 4 * 5 - 1 s (a): the count initial value when activation trigger o ccurs/the reload value at an underflow (when reld=1) s : use at timer activation -: does not influence operation *1 : ttrg effective edge setting trgm[1:0]= 00 ------ does not detect external trigger edge trgm[1:0]= 01 ------ rising edge trgm[1:0]= 10 ------ fal ling edge trgm[1:0]= 11 ------ both edges *2 : count clock division setting csl[2:0]= 000 ------ division of peripheral clock (pclk) by 2 csl[2:0]= 010 ------ division of peripheral clock (pclk) by 8 csl[2:0]= 011 ------ division of peripheral clock (pclk) by 16 csl[2:0]= 100 ------ division of peripheral clock (pclk) by 32 csl[2:0]= 101 ------ division of peripheral clock (pclk) by 64 *3 : tout output polarity setting outl= 0 ------ initial value l=> count l from tmrlra => invert whenever an underflow occurs outl= 1 ------ initial value h=> count h from tmrlra => invert whenever an underflow occurs *4 : reload setting when an underflow occurs reld= 0 ------ one - shot mode reld= 1 ------ reload mode *5 : interrupt request enable setting inte= 0 ------ interrupt disabled inte= 1 ------ interrupt en abled [timer activation] follow the steps below to activate the timer. ? input an activation trigger (a write of "1" to trg bit or a n input of effective external edge from ttrg pin) while down counting, the counter value will be captured onto the tmrlrb whenever a trigger input occurs. the time interval between edges of the triggers to input will be obtained by the following formula. t = (the set value for tmrlra - the captured value for tmrlrb) peripheral clock (pclk) cycle division ratio set with csl mb91590 series mn705-00009-3v0-e 753
chapter 20: reload timer 6 . application note fujitsu semiconductor limited chapter: reload timer fujitsu semiconductor confidential 66 figure 6-6 ex ample of operation ( trgm=01 ) tmrlra cnt_a tmrlra cnt_b tmrlra tmrlrb cnt_ a cnt_b 0x xxxx counter value ttrg input activation trigger retrigger input downcount (reload) (reload) mb91590 series mn705-00009-3v0-e 754
chapter 21: free - run timer 1 . overview fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 1 chapter : f ree - run timer this chapter explains the free - run timer. 1. overview 2. features 3. configuration 4. registers 5. operation 6. setting 7. q&a 8. sample program 9. notes code : 21_mb91590_hm_e_freerun_00 3_ 2011112 7 mb91590 series mn705-00009-3v0-e 755
chapter 21: free - run timer 1 . overview fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 2 1. overview this section explains the overview of the free - run timer. the free - run timer consists of a 32 - bit up counter and a control circuit. the free - run timer can be used in combinatio n with input capture and output compare. figure 1-1 block diagram (overview) external clock (frck pin ) clear up counter compare clear register peripheral clock (pclk) overflow to input capture to output compare interrupt compare circuit mb91590 series mn705-00009-3v0-e 756
chapter 21: free - run timer 2 . features fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 3 2. features this section show the features of the free - run timer. ? format : 32- bit up counter ? number of units : 2 ( free - run timer 0 and free - run timer 1) + 2 (( free - run timer 2 and free - run timer 3) used as input capture for lsyn (lin sync field detection) only) ? clock source : one of 9 internal clocks ( peripheral clock ( pclk )/1, /2, /4, /8, /16, /32, /64, /128, /256) or one of two external clocks (frck0 , frck 1) ? count clear factors : ? software ? reset ? compare match (count value of the free - run timer matches the compare clear register) ? operation start/stop: the operation can be started and stopped by software. ? interrupt : compare clear interrupt ? count value : read/write enabled (writing is only enabled while counting is inactive) ? the 32 - bit free - run timer consists of a 32 - bit up counter, control register, 32 - bit compare clear register, and prescaler. ? a compare clear interrupt will be generated when a compare clear register matches the 32 - bit free - run timer upon comparison of the two. ? i f there is a compare match with reset, software clear or compare clear register, the counter value will be reset to " 00000000 h ". ? it is used as the reference count for output compare and input capture. mb91590 series mn705-00009-3v0-e 757
chapter 21: free - run timer 3 . configuration fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 4 3. configuration this section explains configuration of the free - run timer. figure 3-1 configuration d iagram ( d etailed) note : free - run timer 2 and 3 are used as input capture for lsyn only. therefore, they do not cooperate with output compare. also, no external clock is provided to support them (during clock selection, selecting "external clock" is disabled). clk p clk p / 2 clk p / 4 clk p / 8 clk p / 16 clk p / 32 c lk p / 64 clk p / 128 clk p / 256 free - run timer 0 to free - run timer 1 p er iphe ral clock (pclk) divider setting is prohibited clo ck selection compare clear match flag count clo ck timer data register n compare clear register n cancel timer initialization clear request timer clear counting ope ration no inter rupt request disa ble interrupt f ree - run timer interrupt interr upt request write 0 : flag clear counting ope ration stop in te rnal clock count value clear compare circuit exte rnal clock synchronization circuit n=0, 1 t o input capture and output compare clk [ 3 : 0 ] tccsn : bit3 - 0 ecke tccsn:bit15 sclr tccsn:bit4 stop tccsn:bit6 tccsn:bit9 icre iclr tccsn:bit8 tcdtn cpclrn 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 frckn 1 en a ble i nterrupt exte rnal clock 0 mb91590 series mn705-00009-3v0-e 758
chapter 21: free - run timer 4 . registers fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 5 4. registers this sec tion explains the registers of the free - run timer. table 4-1 registers m ap address register s register function +0 +1 +2 +3 0x0240 cpclr0 compare clear register 0 0x0244 tcdt0 timer data register 0 0x0248 tccsh0 tccsl0 reserved timer control register (upper bit) 0 timer control register (lower bit) 0 0x024c cpclr1 compare clear register 1 0x0250 tcdt1 timer data register 1 0x0254 tccsh1 tccsl1 reserved timer control register (upper bit) 1 timer control register (l ow er bit) 1 0x0 fa 0 cpclr 2 compare clear register 2 (only for lsyn) 0x0 fa 4 tcdt 2 timer data register 2 (only for lsyn) 0x0 fa 8 tccsh 2 tccsl 2 reserved timer control register high - order 2 (only for lsyn) timer control register low - order 2 (only for lsyn) 0x0 fa c cpclr 3 compare clear register 3 (only for lsyn) 0x0 fb 0 tcdt 3 time r data register 3 (only for lsyn) 0x0 fb 4 tccsh 3 tccsl 3 reserved timer control register high - order 3 (only for lsyn) timer control register low - order 3 (only for lsyn) mb91590 series mn705-00009-3v0-e 759
chapter 21: free - run timer 4 . registers fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 6 4.1. timer c ontrol r egister ( u pper b it) : tccsh t he bit configuration of the t imer c ontrol r egister ( u pper b it) is shown. this register is used to control the operation of the free - run timer. ? tccsh0 (free - run timer 0) : address 0248 h ( access: byte, half - word, word) ? tccsh1 (free - run timer 1) : address 0254 h ( access: byte, half - word, word) ? tccsh 2 (f ree - ru n timer 2 (only for lsyn) ) : address 0 fa8 h ( access: byte, half - word, word) ? tccsh 3 (free - run timer 3 (only for lsyn) ) : address 0 fb4 h ( access: byte, half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 ecke - - - - - iclr icre initial val ue 0 0 0 0 0 0 0 0 attribute r/w r0,wx r0,wx r0,wx r0,wx r0,wx r(rm1),w r/w [b it15 ] ecke : clock selection ecke count clock selection 0 internal clock 1 external clock ( frck0 and frck1 pins) * for tccsh2 (free - run timer 2 (only for lsyn)) and tccsh3 ( free - run timer 3 (only for lsyn)), this setting is disabled. ? when this bit is set to "0": internal clock is selected. to select the count clock frequency, you will also need to select the clock frequency selection bits (clk3 to clk0 : bit3 to bit0 ) of the t ccs l register. ? when this bit is set to "1": external clock is selected. the external clock is in put from the "frck" pin. therefore, enable external clock input by writing "0" to the bit of the port direction register (ddr) corresponding to the frck input pin and writing "0" to the bit of the corresponding port function register (pfr) to switch to port input state. if external clock is selected by the ecke bit, clock count will detect both edges. set the pulse width of the external clock to 4/f pclk or more . note : the setting change for the count clock selection bit must be performed while other peripheral modules using the free - run timer output (output compare and input capture) are inactive. [bit 14 to bit 10 ] - : undefined the read value is always "0". this does not affect the writing operation. mb91590 series mn705-00009-3v0-e 760
chapter 21: free - run timer 4 . registers fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 7 [bit 9 ] iclr : compare clear interrupt flag iclr state read write 0 no compare clear match clear the flag (iclr) 1 compare clear match no effect on operation ? this bit will be set to "1" when the compare clear val ue matches the 32 - bit free - run timer value. [bit 8 ] icre : compare clear interrupt request enabled icre operation 0 interrupt disabled 1 interrupt enabled ? when the icre bit and compare clear interrupt flag bit (iclr) are set to "1", an interrupt request for cpu will be generated. mb91590 series mn705-00009-3v0-e 761
chapter 21: free - run timer 4 . registers fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 8 4.2. timer c ontrol r egister ( l ower b it) : tccsl t he bit configuration of t imer c ontrol r egister ( l ower b it) is shown. this register is used to control the operation of the free - run timer. ? tccsl0 (free - run timer 0) : address 0249 h ( acc ess: byte, half - word, word) ? tccsl1 (free - run timer 1) : address 0255 h ( access: byte, half - word, word) ? tccsl 2 (free - run timer 2 (only for lsyn) ) : add ress 0 fa 9 h ( access: byte, half - word, word) ? tccsl 3 (free - run timer 3 (only for lsyn) ) : address 0 fb 5 h ( access: byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - stop - sclr clk3 clk2 clk1 clk0 initial value 0 1 0 0 0 0 0 0 attribute r0,wx r/w r0,wx r0,w r/w r/w r/w r/w [bit 7 ] - : undefined the read value is always "0". this does not affect t he writing operation. [bit 6 ] stop : timer enabled stop operation 0 count enabled (operation) 1 count disabled (stop) ? t he stop bit is used to start/stop counting of the 32 - bit free - run timer. ? when the stop bit is "0": counter of the 32 - bit free - run timer is started. ? when the stop bit is "1": counter of the 32 - bit free - run timer is stopped. note : if output compare is in use, the output compare operation will stop when the free - run timer stops. [bit 5 ] - : undefined the read value is always "0". this does n ot affect the writing operation. [bit 4 ] sclr : timer clear sclr state read write 0 the read value is always "0". writing "0" has no effect on operation . 1 clears the free - run timer. ? when this bit is set to "1", the count value of the free - run time r i s cleared to " 0000000 0 h " . the prescaler within the macro is also cleared at this time. mb91590 series mn705-00009-3v0-e 762
chapter 21: free - run timer 4 . registers fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 9 ? the value read out is always "0". note : if you set this bit to "1", timer clear will be performed at the next internal clock timing. [bit 3 to b it0 ] clk3 to clk0 : clock frequency selection (when internal clock is selected) clk3 clk2 clk1 clk0 clock frequency selection ( f pclk : peripheral clock (pclk)) count clock f pclk =16mhz f pclk =8mhz f pclk =4mhz f pclk =1mhz 0 0 0 0 1/f pclk 62.5ns 125ns 0.25 s 1 s 0 0 0 1 2/f pclk 125ns 0.25 s 0.5 s 2 s 0 0 1 0 4 / f pclk 0.25 s 0.5 s 1 s 4 s 0 0 1 1 8 / f pclk 0.5 s 1 s 2 s 8 s 0 1 0 0 16 / f pclk 1 s 2 s 4 s 16 s 0 1 0 1 32 / f pclk 2 s 4 s 8 s 32 s 0 1 1 0 64 / f pclk 4 s 8 s 16 s 64 s 0 1 1 1 128 / f pclk 8 s 16 s 3 2 s 128 s 1 0 0 0 256 / f pclk 16 s 32 s 64 s 256 s other settings D prohibit ? the frequency is changed at the same time as the setting change to the clock frequency selection bit. if internal clock is selected as the count clock of the free - run timer (clo ck selection bit (ecke= 0)), change the setting while other peripheral modules (output compare and input capture) using the free - run timer output are inactive. ? when the free - run timer is used as compare data for the output compare, the free - run timer clock frequency cannot be set as clk[3:0 ]= 0000 b . mb91590 series mn705-00009-3v0-e 763
chapter 21: free - run timer 4 . register s fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 10 4.3. compare clear register : cpclr t he bit configuration of the c ompare c lear r egister (cpclr) is shown. compare clear register is a 32 - bit register to be used for comparison with the free - run timer. ? cpclr0 (free - ru n timer 0) : address 0240 h ( access: word) ? cpclr1 (free - run timer 1) : address 024c h ( access: word) ? cpclr 2 (free - run timer 2 (only for lsyn) ) : address 0 fa 0 h ( access: word) ? cpclr 3 (free - run timer 3 (only for lsyn) ) : address 0 fac h ( access: word) bit 31 bi t 0 cl[31:0] initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 attribute r,w [bit 31 to b it0 ] cl[31:0] : compare clear ? the compare clear register is used for comparison with the count value of the 32 - bit free - run time r. if the count value of this register matches that of the free - run timer, the 32 - bit free - run timer will be reset to " 00000000 h " and an interrupt will be generated when the value set to this register matches the counter value. however, the value needs to be written while the timer is inactive ( the stop bit of timer state control register lower (tccsl) = 1 ). ? writing to this register during operation will have no meaning. ? when accessing this register, use a word access instruction. mb91590 series mn705-00009-3v0-e 764
chapter 21: free - run timer 4 . registers fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 11 4.4. timer data register : tcdt t he bit configuration of the t imer d ata r egister (tcdt) is shown. the timer data register is used for reading the count value of the 32 - bit free - run timer. ? tcdt0 (free - run timer 0) : address 0244 h ( access: word) ? tcdt1 (free - run timer 1) : address 0250 h ( acc ess: word) ? tcdt 2 (free - run timer 2 (only for lsyn) ) : address 0 fa 4 h ( access: word) ? tcdt 3 (free - run timer 3 (only for lsyn) ) : address 0 fb 0 h ( access: word) bit 31 bit 0 t[31:0] initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 attribute r,w ? the count value of the 32 - bit free - run timer can be read by reading the timer data register. ? timer value can be written to the free - run timer by writing to the timer data register. always write to this register while the free - ru n timer is inactive (timer control register lower (stop of tccsl = 1 )). ? when accessing this register, use a word access instruction. ? the 32 - bit free - run timer will be initialized as soon as any of the following occurs. ? reset ? the clear bit (sclr = 1) of the timer state control register (tccsl) ? the timer count value matches the compare clear register ? writing to this register while it is in operation will have no meaning. mb91590 series mn705-00009-3v0-e 765
chapter 21: free - run timer 5 . operation fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 12 5. operation this section explains the o peration s of the free - run timer. 5.1 . count operation of the free - run timer 5.2 . counting up 5.3 . timer clear 5.4 . clear operations of the free - run timer 5.5 . timer interrupt mb91590 series mn705-00009-3v0-e 766
chapter 21: free - run timer 5 . operation fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 13 5.1. count operation of the free - run timer this section explains the count operation of the free - run timer. the free - run timer will be incremented based on the input clock (internal clock or external clock). if the external clock mode (tccsh : ecke = 1) is selected, the free - run timer starts counting up by the rising and falling edges of the external input clock. the first rising and falling edges of the external clock immediately after the selection of external clock mode will be ignored. this means that the first falling edge will be ignored if the initial value of the external clock input is "1", and the first rising edge will be ignored if the initial value is "0". (1) reset (2) clearing of the free - run timer by reset (count value "00000000 h ") (3) count up operation by the free - run timer (4) compare clear match of the free - run timer and interrupt generation (5) clearing of the free - run timer by compare clear match (count value "00000000 h ") (6) repetition of step (3) to (5) (7) the free - run timer counts up in the clock obtained by dividing the internal clock (count clock). (8) the free - run timer counts up in the count clock obtained by synchronizing the external clock with the internal clock. count timing count of free - run timer reset compare clear match interrupt request clearing free - run timer count of free - run timer time ffff internal clock (f clk p /2) external pin (cki) count of free - run timer clearing by software clearing by software (internal clock) (1) (5) (2) count timing p e r iphe r al clo c k (clk p ) 00000000 h (2) (3) (4) (8) (5) (7) ( external clock f clk p /2 ) cpclr exte rnal clock input count clo ck count v alue n tccsh : ecke the first edge immediately after e xternal clo ck selection is ignored n+1 mb91590 series mn705-00009-3v0-e 767
chapter 21: free - run timer 5 . operation fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 14 5.2. counting up this section the explains counting up of the free - run timer. 32- bit free - run timer is an up counter. t he counter starts counting up from the timer data register (tcdt) configured in advance. it continues to count up until the count value matches the value of the compare clear register (cpclr). the counter will then be cleared to " 00000000 h " and start counting up again. figure 5-1 up counter operation ffffffff h bfffffff h 7fffffff h 3fffffff h 00000000 h count value reset time timer operation start compare clear match 7fffffff h compare clear register bfffffff h ffffffff h mb91590 series mn705-00009-3v0-e 768
chapter 21: free - run timer 5 . operation fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 15 5.3. timer clear this section explains timer clear of the free - run timer. the count value of the free - run timer will be cleared in any of the followings: ? when there is a match with the compare clear register ? when "1" is written to the sclr bit of the tccsl register while it is in operation ? when "00000000 h " is written to the tcdt register while it is in stop ? when it has been reset. the counter will be cleared as soon as it has been reset. when there is a match with the compare clear register, the counter will be cleared in synchronization with the count timing. figure 5-2 clear timing of the free - run timer compare clear register v alue n compare match count v alue n 00000000 h mb91590 series mn705-00009-3v0-e 769
chapter 21: free - run timer 5 . operation fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 16 5.4. each clear operations of the free- run timer this section explains each c lear o perations of the free - run timer. clearing of the free - run timer (4 types) (1) when i t has been reset (2) when "1" is written to sclr: bit4 of the tccsl register while it is in operation (3) when there is a match with the compare clear register (4) when "00000000 h " is written to the tcdt register while it is in stop reset clear count of free - run timer time clearing by software or compare match enable/disable operation (software) peripheral clock (clk p ) count timing (internal clock) n - 1 n compare match clearing free - run timer interrupt request timing of clearing by compare ma tch (1) (2) (3) (4) operation stop operation stop 0000000 h ?00000000 h ? write n - 1 n ?00000000? ?00000001? compare value=n count value compare value (1) (2) (3) (4) mb91590 series mn705-00009-3v0-e 770
chapter 21: free - run timer 5 . operation fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 17 5.5. timer interrupt this se ction explains t i mer interrupt of the free - run timer. for the free - run timer, you will be able to generate t he following type of interrupt. ? compare clear interrupt the compare clear interrupt will be generated when the timer value matches the value of the compare clear register (cpclr). figure 5-3 interrupt compare clear interrupt count value mb91590 series mn705-00009-3v0-e 771
chapter 21: free - run timer 6 . setting fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 18 6. setting this section explains setting of the free - run timer. table 6-1 settings require d for using the free - run timer configuration configured register setting method timer initialization condition setting timer control registers (tccs0 to tccs 3) see 7.4 . count clock setting internal clock selection see 7.1 . external clock selection see 7.2 . count operation start see 7.3 . for external clock, set the clock input pin s ( frck0 and frck1) for input. set the pins for peripher al input. see " chapter: i/o ports". table 6-2 settings required for performing free - run timer interrupt configuration configured register setting method free - run timer interrupt vector free - run timer interrupt level setting see " chapter: interrupt control". see 7.5 . free - run timer interrupt setting interrupt request clear i nterrupt request enable timer control registers (tccs0 to tccs 3) see 7.6 . table 6-3 settings required for stopping the free - run timer configuration configured register setting method free - run timer stop bit setting timer control registers (tccs0 to tccs 3 ) see 7.7 . mb91590 series mn705-00009-3v0-e 772
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 19 7. q&a this section e xplains q&a of the free - run timer. 7.1 . how to select internal clock dividers 7.2 . how to select the external clock 7.3 . how to enable/disable the count operation of the free - run timer 7.4 . how to clear the free - run timer 7.5 . about interrupt related registers 7.6 . how to enable compare clear interrupt 7.7 . how to stop the free - run timer operation mb91590 series mn705-00009-3v0-e 773
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 20 7.1. how to select internal clock dividers this section explains how to select internal clock dividers. there are nine types of internal clock dividers. you can configure it using the clock selection bits (tccs0 : ecke ) , ( tccs1 : ecke ) , ( tccs 2: ecke ), ( tccs 3: ecke) , and count clock bits (tccs0 : clk[3:0] ) , ( tccs1 : clk[3:0] ) , ( tccs 2: clk[3:0] ), ( tccs 3: clk[3:0]) . internal clock configuration clock selection bit (ecke) count clock bit s (clk[3:0]) to select f pcl k set "0" . set "0000" . to select 2/f pclk set "0" . set "0001" . to select 4/f pclk set "0" . set "0010" . to select 8/f pclk set "0" . set "0011" . to select 16/f pclk set "0" . set "0100" . to select 32/f pclk set "0" . set "0101" . to select 64/f pclk set "0" . set "0110" . to select 128/f pclk set "0" . set "0111" . to select 256/f pclk set "0" . set "1000" . mb91590 series mn705-00009-3v0-e 774
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 21 7.2. how to select the external clock this section explains how to select the external clock. you can configure it using the clock selection bits (tccs0 : ecke ), ( tccs1 : ecke), data direction bits and po rt function bits. to set to external clock input configuration pin pulse width (h width, l width) free - run timer 0 set the clock selection bit (ecke) to "1". set the frck 0 pin for peripheral input. (see " chapter: i/o ports".) frck0 4/f pclk or higher fre e- run timer 1 set the frck 1 pin for peripheral input. (see " chapter: i/o ports".) frck1 note : no external clock is provided to support free - run timer 2 (only for lsyn) and 3 (only for lsyn) (during clock selection, selecting "external clock" is disabled ). mb91590 series mn705-00009-3v0-e 775
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 22 7.3. how to enable/disable the count operation of the free - run timer this section explains how to enable/disable the count operation of the free - run timer. set the count operation bits (tccs0 : stop ) , ( tccs1 : stop ) , ( tccs 2: stop ), ( tccs 3: stop) . operation coun t operation bit (stop) to operate the free - run timer set "0" . to stop the free - run timer set "1" . mb91590 series mn705-00009-3v0-e 776
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 23 7.4. how to clear the free- run timer this section explains how to clear the free - run timer. you can clear the free - run timer using the following method. ? set usi ng the clear bits (tccs0 : sclr ) , ( tccs1 : sclr ) , ( tccs 2: sclr ), ( tccs 3: sclr) . operation clear bit (sclr) to clear the free - run timer write "1" . ? p erform a reset. when a reset is performed (rstx pin input, watchdog reset, software reset, etc.), the free - run ti mer will be cleared to its initial state. ? write "00000000 h " while the free - run timer is inactive. if "00000000 h " is written while the free - run timer is inactive, the count value will be "00000000 h ". ? overflow of the free - run timer will result in the count value returning to "00000000 h ". ? it will be cleared if there is a match with the compare clear register. mb91590 series mn705-00009-3v0-e 777
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 24 7.5. about interrupt related registers this section explains interrupt related registers. free - run timer interrupt vector and free - run timer interrupt level settings the relationship between free - run timer numbers, interrupt levels and interrupt vectors is as shown in " c. list of interrupt vector " in " appendix ". for details of the interrupt levels and interrupt vectors, see " chapter: interrupt control (interru pt controller) ". number interrupt vector (default) interrupt level setting bit (icr[4:0]) free - run timer 0 #50 address: 0fff34 h interrupt level register (icr34) address: 00462 h free - run timer 1 #51 address: 0fff30 h interrupt level register (icr35) addres s: 00463 h free - run timer 2 (only for lsyn) #50 address: 0fff34 h interrupt level register (icr34) address: 00462 h free - run timer 3 (only for lsyn) #51 address: 0fff30 h interrupt level register (icr35) address: 00463 h since interrupt request flag s (tccs 0: iclr), (tccs1 : iclr), (tccs 2: iclr) , (tccs 3: iclr) will not be cleared automatically, clear th e flags using software before returning from interrupt processing. (write "0" to the iclr bit) mb91590 series mn705-00009-3v0-e 778
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 25 7.6. how to enable compare clear interrupt this section explains how to enable compare clear interrupt . enable interrupt request, interrupt request flag interrupt enable setting can be performed using interrupt request enable bits (tccs0 : icre ) , ( tccs1 : icre ) , ( tccs 2: icre ), ( tccs 3: icre) . operation compare clear interrupt request enable bit (icre) interrupt disabled set "0" . interrupt en abled set "1" . clearing of the interrupt request can be configured using interrupt flag bits (tccs0 : iclr ) , ( tccs1 : iclr ), ( tccs 2: iclr), ( tccs 3: iclr) . operation compare clear interrupt flag bit (i clr) interrupt request clear write "0". mb91590 series mn705-00009-3v0-e 779
chapter 21: free - run timer 7 . q&a fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 26 7.7. how to stop the free - run timer operation this section explains how to stop the free - run timer operation. set using the count operation bits (tccs0 : stop ) , ( tccs1 : stop ) , ( tccs2 : stop ), ( tccs3 : stop) . see " 7.3 . how to enable/disable the count operation of the free - run timer ". mb91590 series mn705-00009-3v0-e 780
chapter 21: free - run timer 8 . sample program fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 27 8. sample program t his section explains s ample p rogram of the free - run timer. setting procedure example 1 free - run timer 0, clock=pclk/2^6, count the number of compare matches using interrupt processing. < initial setting > - free - run timer ch . 0 control register name.bit name control register setting clock selection ? compare interrupt request flag ? compare interrupt request enabled ? counting operation >> tcdt clear >> count clock ? tccsh0/tccsl0 .ecke . iclr .icre .stop .clr .clk3 -0 timer data value setting tcdt0 - interrupt - related register name. bit name sets an interrupt level. icr34 i flag setting (ccr) - variable setting - free - run timer ch . 0 activation register name.bit name count operation activation tccs0 .stop < interrupt > - interrupt processing register name.bit name clearing of interrupt request flag tccs0.iclr (any process) variable counting < interrupt vector > vector table setting ( note ) clock - related settings and the setting of __set_il (numeric value) need to be configured in advance. see ? chapter: clock ? and ? chapter: interrupt control (interrupt controller) ? program example 1 void free_run_timer0_sample(void) { freerun0_initial(); freerun0_start(); } void freerun0_initial(void) { io_tccs1.word = 0x0041; /* setting value =0000_0000_0100_0 001 */ /* bit15 = 0 ecke internal clock source */ /* bit14 - 10= 00000 reserved bit */ /* bit9 = 0 iclr compare interrupt request flag */ /* bit8 = 0 icre compare interrupt disabled */ /* bit7 = 0 reserved bit */ /* bit6 = 1 stop count disabled */ /* bit5 = 0 reserved bit */ /* bit4 = 0 sclr initializati on of sclr free - run timer value (no) */ /* bit3 - 0 = 0001 clk3 - 0 count clock pclk/2=32mhz/2 */ io_tcdt0 = 0x0000; /* initialization of timer data value */ io_icr[34].byte = 0x10; /* free - run timer 0 interrupt level setting (any value) */ __ei(); /* interrupt enabled */ count = 0; } void freerun0_start(void) { io_tccs0.bit.stop = 0; /* bit6 = 0 stop count enabled */ } __interrupt void free _run_timer0_int(void) { io_tccs0.bit.iclr = 0; /* bit9 = 0 clearing of iclr compare match flag */ count++; } specification of interrupt routine required in vector table #pragma intvect free_run_timer0_int 50 mb91590 series mn705-00009-3v0-e 781
chapter 21: free - run timer 9 . notes fujitsu semiconductor limited chapter : free - run timer fujitsu semiconductor confidential 28 9. notes t his section explains notes of the free - run timer. ? clear timing of the free - run timer ? when a reset is performed (rstx pin input, watchdog reset, software reset, etc.) , the counter will stop counting after initializing to "00000000 h ". ? a software clear (tccsh : sclr=1) clears the counter as soon as the clear request is generated. however, in the case of compare match, the counter is cleared in the same timing as the counting up. ? counter clear operation (software, compare match) will only be enabled while the free - run timer is in operation. to clear the counter while the free - run timer is in stop, you need to write " 00000000 h " to the timer count data register. ? writing to the timer data register ? always write a value to the free - run timer while the free - run timer is inactive (stop = "1" ), using a word access instruction. ? external clock operation ? the timings of the compare match output and generation of interrupt of the external clock will be the next count clock timing after the compare match. therefore, in order to the generate compare match outpu t and interrupt, 1 clock (external clock) must at least be input after the compare match. ? read - modify - write ? compare clear interrupt flag bits of the timer control reg ister are "1" when read using a read - modify - write instruction . mb91590 series mn705-00009-3v0-e 782
chapter 22: output compare 1 . overview fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 1 chapter : output compare this chapter explains the output compare. 1. overview 2. features 3. configuration 4. registers 5. operation 6. setting 7. q&a 8. sample program 9. notes code : 22_mb91590_hm_e_outputcom_00 7 _201111 27 mb91590 series mn705-00009-3v0-e 783
chapter 22: output compare 1 . overview fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 2 1. overview this section explains the overview of the output compare. the output compare consists of a 32- bit compare register, a compare output latch, and a compare control register. wh en the 32 - bit free - run timer value matches the compare register value, the output level is inverted and an interrupt also can be generated. figure 1-1 block diagram (overview) output compare 0 comp latch comp latch output compare 1 output compare 2 comp latch comp l atch output compare 3 ocu0 ocu1 ocu2 ocu3 toggle output toggle output interrupts interrupts from free - run timer mb91590 series mn705-00009-3v0-e 784
chapter 22: output compare 2 . features fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 3 2. features this section explains the features of the output compare. figure 2-1 output waveform ? type : 32 - bit compare register 4 + comp a re c ircuit ? corresponding timer : free - run timer 0 or 1 is used ? number : 4 channels ? operation by compare match ? pin output value invert (toggle output) ? interrupt occurrence ? count accuracy : peripheral clock (pclk/2, pclk/4, pclk/8, pclk/16, pclk/32, pclk/64, pcl k/128, pclk/256) (depend ent on the free - run timer) note : the setting of the peripheral clock (pclk) divided by 1 is prohibited. ? toggle change width (t): 1 count accuracy to 100000000 h count accuray ? interrupt : compare match interrupt ? others : ? output level initial valu e setting is enabled. ("h"/"l") ? unused pins as ocu output can be used as general - purpose ports. ? four compare registers can be used for independe n ce. ? output pins and interr u pt flags correspond to the compare register. ? output pins can be inverted with the use of two compare registers. (function only for ocu1, ocu3) ? the initial value of each output pin can be set. ? when the ou t put compare register matches the 32 - bit free - run timer, an interrupt can be generated. t 1 or t(max.) 2 (ocu0,2 pin) 2 1 toggled output 2 channels pwm output 1 channel t 1 or t(max.) 2 1 2 (ocu1,3) (ocu1,3 pin) t t t t 1 mb91590 series mn705-00009-3v0-e 785
chapter 22: output compare 3 . configuration diag ram fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 4 3. configuration diagram this secti on explains the configuration dia g ram of the output compare. figure 3-1 configuration diagram (detail) ocsl01 : bit4 output compare 0 to 3 f rom free- r un timer match ocu0 inter r upt ocu2 inter r upt ocu1 inter r upt ocu3 inter r upt latch inv ersion match latch inv ersion latch compare 0 compare 1 latch compare register 0, 2 compare ope r ation stop no inter r upt request inter r upt request disa b le inter r upt enab le inter r upt lo w fi x ed * wr ite ena b led only when compare ope r ation stops inver t latch of ocu1, 3 only when there is a match with occp1, 3 inver t latch of ocu1, 3 only when there is a match with occp0, 2 or occp1, 3 high fi x ed wr ite 0 : flag clear ena b le compare ope r ation compare ope r ation stop ena b le compare ope r ation compare register 1, 3 lo w fi x ed * wr ite ena b led only when compare ope r ation stops high fi x ed no inter r upt request inter r upt request wr ite 0 : flag clear disa b le inter r upt enab le inter r upt iop0 ioe0 o td0 o td1 ocu1 ocu3 exte r nal pin ocu0 ocu2 exte r nal pin occp2 occp0 occp3 occp1 cst0 cst0 cst1 cst1 ocsl23 : bit1 ocsl01 : bit1 ocsl23 : bit0 ocsl01 : bit0 ocsl01 : bit6 ocsl23 : bit6 ioe0 iop0 o td0 cmod ocsh01 : bit8 ocsh23 : bit8 cmod ocsh23 : bit12 ocsh01 : bit12 ocsl23 : bit4 iop1 iop1 ocsl23 : bit7 ocsl01 : bit7 ocsl23 : bit5 ocsl01 : bit5 ioe1 ioe1 ocsh23 : bit9 ocsh01 : bit9 o td1 mb91590 series mn705-00009-3v0-e 786
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 5 4. registers this section explains the registers of the ou tput compare. table 4-1 registers map address register s register function +0 +1 +2 +3 0x02e8 occp0 compare register 0 0x02ec occp1 compare register 1 0x02f0 ocfs01 reserved ocsh01 ocsl01 free - run timer selec tion register 01 output control register 01 upper output control register 01 lower 0x02f4 occp2 compare register 2 0x02f8 occp3 compare register 3 0x02fc ocfs23 reserved ocsh23 ocsl23 free - run timer selection register 23 output control register 23 upper output control register 23 lower mb91590 series mn705-00009-3v0-e 787
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 6 4.1. free -run timer selection register : ocfs t he bit configuration of the f ree - run t imer s election r egister is shown below . the free - run timer to compare is selected. ? ocfs01 ( free - run timer selection 01) : address 02f0 h ( acces s: byte, half - word, word) b it 7 b it 6 b it 5 b it 4 bit3 bit2 bit1 bit0 D D D D D D sel1 sel0 initial value D D D D D D 1 1 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w ? ocfs23 ( free - run timer selection 23) : address 02fc h ( access: byte, half - word , word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 D D D D D D sel3 sel2 initial value D D D D D D 1 1 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w [b it 7 to b it 2 ] - : undefined writing to these bits does not affect the operation of the output compare. [b it 1 , bit0 ] seln : free - run timer selection sel n (n=0~3) operating mode 0 f ree - run timer 0 1 f ree - run timer 1 mb91590 series mn705-00009-3v0-e 788
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 7 4.2. output control register (upper bit) : ocsh t he bit configuration of the o utput c ontrol r egister (upper b it) is shown below . this reg ister is to control operations of the output compare 0, 1, 2, 3. ? ocsh01 ( output compare 01) : address 02f2 h ( access: byte, half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 D D D cmod reserved reserved otd1 otd0 initial value D D D 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w0 r/w0 r,w r,w ? ocsh23 ( output compare 23) : address 02fe h ( access: byte, half - word, word) bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 D D D cmo d reserved reserved otd3 otd2 initial value D D D 0 0 0 0 0 attribute r1,wx r1,wx r1,wx r/w r/w0 r/w0 r,w r,w [b it15 to b it13 ] - : undefined writing to these bits does not affect the operation of the output compare . [b it12 ] cmod : compare mode cmod ope rating mode 0 independent operation (ocu0 to ocu 3 pins output level invert operation is independent.) ? ocu0, ocu 2 pins: when the free - run timer value corresponds to the compare register 0, 2 (occp0, occp2) value, the output is inverted. ? ocu 1, ocu 3 pins: when the free - run timer value corresponds to the compare register 1, 3 (occp1, occp3) value, the output is inverted. the comparison t a rget free - run timer is selected by ocfs01 and ocfs23 registers. 1 coordinated operation ? ocu0, ocu 2 pins: when the free - run timer value corresponds to the compare register 0, 2 (occp0, occp2), the output is inverted. ? ocu1, ocu 3 pins: when the free - run timer value corresponds to either the compare register (0 or 1) or (2 or 3), the output is inverted. the comparison target free - run timer is selected by ocfs01 and ocfs23 registers. ? when the compare register 0, 1 and 2, 3 have the same value, the operation is the same one as when only one compare register is used. [b it11 , b it10 ] reserved always set these bits to "0". mb91590 series mn705-00009-3v0-e 789
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 8 [b it9 ] otd : pin level setting (output compare 1,3) this bit specifies the pin output level (initial value) when output from ocu1, ocu 3 pins is allowed. otd1, 3 operation 0 ocu1, ocu 3 pins output lev el (initial value) is set to "l" . 1 ocu1, ocu 3 pins output level (initial value) is set to "h" . when output from ocu1, ocu 3 pins is performed, the setting of a general - purpose port is required. the setting should be performed after the compare operation is stopped. with the reading operation, the output compare pin output is read. [b it8 ] otd : pin level setting (output compare 0, 2 ) this bit specifies the pin output level (initial value) when output from ocu0, ocu 2 pins output is enabled. otd0, 2 operati on 0 ocu0, ocu 2 pins output level (initial value) is set to "l" . 1 ocu0, ocu 2 pins output level (initial value) is set to " h " . when ocu0, ocu 2 pins output is performed, the setting of a general - purpose port is required. the setting should be performed a fter the compare operation is stopped. with the reading operation, the output compare pin output is read. mb91590 series mn705-00009-3v0-e 790
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 9 4.3. output control register (lower bit) : ocsl t he bit configuration of the o utput c ontrol r egister (lower b it) is shown below . this register is to contro l operations of the output compare 0, 1, 2, 3. ? ocsl01 ( output compare 01) : address 02f3 h ( access: byte, half - word, word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iop1 iop0 ioe1 ioe0 D D cst1 cst0 initial value 0 0 0 0 1 1 0 0 attribute r(rm1),w r(rm1),w r/w r/w r1,wx r1,wx r/w r/w ? ocsl23 ( output compare 23) : address 02ff h ( access: byte, half - word, word) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 iop3 iop2 ioe3 ioe2 D D cst3 cst2 initial value 0 0 0 0 1 1 0 0 attribute r(rm1),w r(rm1),w r/w r/w r1,wx r1,wx r/w r/w [b it7 ] iop : interrupt request flag (output compare 1, 3) iop1, 3 state read write 0 without interrupt request flag (iop1, iop 3) is cleared. 1 with interrupt requ est no effect on operations ? this bit becomes "1" when the count value of free - run timer (tcdt) corresponds to the output compare compare register ( occp1, occp 3). ? the interrupt request becomes enabled when the interrupt enable bit (ioe1, ioe 3) is "1" . [bi t6 ] iop : interrupt request flag (output compare 0, 2 ) iop0, 2 state read write 0 without interrupt request flag (iop 0, iop 2 ) is cleared. 1 with interrupt request no effect on operations ? this bit becomes "1" when thecount value of free - run timer (tcdt ) corresponds to the output compare compare register ( occp0, occp 2). ? the interrupt request becomes enabled when the interrupt enable bit (ioe0, ioe 2) is "1" . mb91590 series mn705-00009-3v0-e 791
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 10 [b it5 ] ioe : interrupt request enable (output compare 1, 3 ) ioe1, 3 state 0 output compare 1, 3 interrupt request is disabled. 1 output compare 1, 3 interrupt request is en abled. ? this bit is used to "enable" the output compare interrupt for the compare register 1, 3. ? while "1" is written to this bit, if the compare match interrupt flag bit (iop1, i op 3) is set, the output compare interrupt is generated. [b it4 ] ioe : interrupt request enable (output compare 0, 2) ioe0, 2 state 0 output compare 0, 2 interrupt request is disabled. 1 output compare 0, 2 interrupt request is en abled. ? this bit is used to "enable" the output compare interrupt for the compare register 0, 2. ? while "1" is written to this bit, if the compare match interrupt flag bit (iop0, iop2 ) is set, the output compare interrupt is generated. [b it3 , bit 2 ] - : undefined writing to these b its does not affect the operation of the output compare . [b it1 ] cst : operatio n enable (output compare 1, 3 ) cst1,3 operation 0 operation of the output compare 1, 3 is stopped. 1 operation of the output compare 1, 3 is enabled. ? this bit enables the comp are operation for the count value of free - run timer (tcdt) and the output compare compare register. ? the compare registers ( occp1, occp 3) must be set with values before the compare operation is enabled. ? because the output compare is synchronized with the fr ee - run timer, when the free - run timer is stopped, the output compare also is stopped. [b it0 ] cst : operatio n enable (output compare 0, 2 ) cst0, 2 operation 0 operation of the output compares 0, 2 is stopped. 1 operation of the output compares 0, 2 is en abled. ? this bit enables the compare operation for the count value of free - run timer (tcdt) and the output compare compare register. ? the compare registers ( occp0, occp 2) must be set with values before the compare operation is enabled ? because the output com pare is synchronized with the free - run timer, when the free - run timer is stopped, the output compare operation also is stopped. mb91590 series mn705-00009-3v0-e 792
chapter 22: output compare 4 . registers fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 11 4.4. compare register : occp t he bit configuration of the c ompare r egister is shown below . these registers set the values to be compa re d with the 32 - bit free - run timer count value. ? occp0 ( output compare 0) : address 02e8 h ( access: word) ? occp1 ( output compare 1) : address 02ec h ( access: word) ? occp2 ( output compare 2) : address 02f4 h ( access: word) ? occp3 ( output compare 3) : address 02f8 h ( ac cess: word) bit 31 bit 0 op[31:0] initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 attribute r/w ? the compare registers occp0 to occp 3 are compared with the count value of free - run timer (tcdt) . ? when the occp register values correspond to the 32 - bit free - run timer value, a compare signal is generated and an output compare interrupt flag is set. the compare value is reflected after the write instruction is completed. therefore, the compare value change during operation might generate an interrupt twice per one free -ru n counting if the newly written compare value is larger than the previous compare value. ? in addition, when the corresponding ocu of the port function register (pfr) is set and output is enabled, the output level corresponding to the compare register is inverted. ? for access to this register, use a wor d access instruction. mb91590 series mn705-00009-3v0-e 793
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 12 5. operation this section explains the o peration s of the output compare. 5.1 . output compare output (independent invert) cmod = "0" 5.2 . output compare output ( coordinated invert) cmod = "1" 5.3 . output compare operation timing mb91590 series mn705-00009-3v0-e 794
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 13 5.1. output compare output (independent invert) cmod = "0" this section explains the output compare output (independent invert). (1) a compare value is set. (2) compare operation is enabled (cst = 1) (3) free - run timer count up (example of one count per four clocks) (4) a free - run timer value is compared with a compare value and they match (compare match) (5) ocu output level is inverted. (6) a compare match interrupt request is generated. (clkp) mb91590 series mn705-00009-3v0-e 795
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 14 5.2. output compare output (coord i nated invert) cmod = "1" this section expl ains the output compare output ( c oordinated invert). (1) values of compare 0 and compare 1 are set. (2) compare operation is enabled. (3) free - run timer count up (4) compare 1 match (5) ocu1 output level is inverted. (6) compare1 match interrupt (7) free - run timer count up (8) compare 0 match (9) ocu0 output level is inverted. when c mod = 1 , ocu1 output level also is inverted. (10) compare 0 match interrupt inter r upt request 0 ocu0 output (2) (1) count of free-run timer 1 ffffffff h bfffffff h 00000000 h compare register 0 (8) cst 0 (6) (4) (5) compare register 1 cst 1 40000000 h ocu1 output cmod=0 cmod=1 interrupt request 1 (1) (2) (5) (9) (10) time bfffffff h (3) cst 0 40000000 h cst 1 (7) clearing by software clearing by software ocu0 output ocu1 output (9) mb91590 series mn705-00009-3v0-e 796
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 15 5.3. output compare operation timing this section explains the output c ompare o peration t iming . with the use of two pairs of compare registers, the output level can be changed. (for cmod = 1) the output compare can invert the output as well as generate an interrupt when the free - run timer value matches the specified compare register value and a compare match singal is generated. the output invert timing on compare match is synchronized with the counter count timing. mb91590 series mn705-00009-3v0-e 797
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 16 5.3.1. compare register write compare r egister w rite is shown below . the compare operation with the counter value is not performed on compare regist e r rewrite. figure 5-1 comp a re register write timing counter value n n+1 n+2 m n+3 n+1 compare clear register 0 value compare register 0 write l n+3 compare clear register 1 value compare register 1 write compare 0 stop compare 1 stop a match signal is not generated mb91590 series mn705-00009-3v0-e 798
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 17 5.3.2. compare match, interrupt compare match, i nterrupt are shown below . figure 5-2 compare match, interrupt timing counter value n n+1 n+2 n n+3 count clock pin output interrupt compare register value compare match mb91590 series mn705-00009-3v0-e 799
chapter 22: output compare 5 . operation fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 18 5.3.3. pin output this section shows the p in o utput . figure 5-3 pin output timing counter v alue v alue of co mpare register compare match pin output mb91590 series mn705-00009-3v0-e 800
chapter 22: output compare 6 . setting fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 19 6. setting this sectio n explains settings of the output compare. table 6-1 configuration necessary for use of output compare configuration register to be configured setting method setting of the free - run timer see " chapter: free - run t imer". - setting of the compare value compare register: (occpx) see 7.1 . setting of the compare mode output conrtol register (ocshxx, ocslxx) see 7.2 . compare operation stop see 7.3 . setting of the compare pin output initial level see 7.4 . setting of ocu0 to ocu 3 pins to output set each pin for peripheral output. see " chapter: i/o ports", for the setting method. the free - run timer clear timer control register (tccs) see " chapter: free - run timer". see 7.6 . compare operation enable (activation) output conrtol register (ocsh x x, ocslxx) see 7.7 . table 6-2 items necessary for interrupt execution configuration register to be configured setting method setting of output compare interrupt vector and output compare interrupt level see " chapter: interrupt control ( interrupt controller ) ". see 7.8 . setting of output compare interrupt ? interrupt request clear ? interrupt request enable output conrtol register (ocshxx, ocslxx) see 7.10 . mb91590 series mn705-00009-3v0-e 801
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 20 7. q&a this section explains q&a of the output compare. 7.1 . how c an i s et the c ompare v alue? 7.2 . how c an i s et the c ompare m ode? (example with ocu1) 7.3 . how c an i e nable/ d isable the c ompare o peration? (example with ocu0,1) 7.4 . how c an i s et the c ompare p in o utput i nitial l evel? (example with ocu0,1) 7.5 . how c an i s et the c ompare p in ocu0 to ocu 1 for o utput? 7.6 . how c an i c lear the f ree - run t imer? 7.7 . how c an i e nable the c ompare o peration? 7.8 . interrupt r elated r egister? 7.9 . interrupt t ype? 7.10 . how c an i e nable the i nterrupt? 7.11 . calculation m ethod for the c ompare v alue? mb91590 series mn705-00009-3v0-e 802
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 21 7.1. how can i s et the compare value? this section explains how to set the compare value. write the compare value to the compare register occpx. mb91590 series mn705-00009-3v0-e 803
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 22 7.2. how can i s et the compare m ode? (example with ocu1) this section explains how to set the compare mode. set with the compare mode bit (ocsh01 : cmod) operation compare mode bit to invert t he ocu1, ocu 3 pins output when the free - run timer value matches the compare register 1 (occp1) set (ocsh01 : cmod) to "0". to invert the ocu1 pin output when the free - run timer value matches either the compare register 0 (occp0) or the compare register 1 (o ccp1) set (ocsh01 : cmod) to "1". regardless of the cmod bit, the operation is as follows: ? regardless of the compare mode bit (ocsh01 : cmod) setting, the ocu0 output is inverted when the free - run timer value matches the compare register (occp0). mb91590 series mn705-00009-3v0-e 804
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 23 7.3. how can i enable/disable the compare o peration? (example with ocu0, ocu1) this section explains how to enable/disable the compare operation. set the compare operation enable bit (ocsl01 : cst0), (ocsl01 : cst1). operation compare compare operation enable bit to stop (dis able) the compare operation compare 0 set (ocsl01 : cst0) to "0" . compare 1 set (ocsl01 : cst1) to "0" . to enable the compare operation compare 0 set (ocsl01 : cst0) to "1" . compare 1 set (ocsl01 : cst1) to "1" . mb91590 series mn705-00009-3v0-e 805
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 24 7.4. how can i s et the compare pin o utput initial l evel? (example with ocu0, ocu1) this section explains how to set the compare pin output initial level. set the compare pin output specification bit (ocsh01 : otd0), (ocsh01 : otd1). operation compare pin output specification bit to set the compare 0 pin to "l " set (ocsh01 : otd0) to "0" . to set the compare 0 pin to " h " set (ocsh01 : otd0) to "1" . to set the compare 1 pin to "l" set (ocsh01 : otd1) to "0" . to set the compare 1 pin to " h set (ocsh01 : otd1) to "1" . mb91590 series mn705-00009-3v0-e 806
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 25 7.5. how can i s et the compare pin ocu0, ocu1 for o utput ? this section explains how to set the compare pin ocu0 , ocu1 for output. set the pin for peripheral output. for setting method, see " chapter: i/o ports". mb91590 series mn705-00009-3v0-e 807
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 26 7.6. how can i clear the free- run t imer? this section explains how to clear the free - run timer. set the cl ear bit (tccs : sclr) of the free - run timer used. operation clear bit (sclr) to clear the free - run timer write "1". for other methods, see "chapter : free - run t imer ". mb91590 series mn705-00009-3v0-e 808
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 27 7.7. how can i enable the compare o peration? this section explains how to enable the compare op eration. set the compare operation enable bit (ocsl01 : cst0, ocsl01 : cst1, ocsl23 : cst2, ocsl23 : cst3). see " 7 .3 how c an i e nable/ d isable the c ompare o peration? ( example with ocu0, ocu1) ". mb91590 series mn705-00009-3v0-e 809
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 28 7.8. interrupt related register? this section explains the interrupt related register. both the output compare interrput vector and the output compare interrupt level are set. the relation among the output compare number, interrupt l evel, and interrupt vector is shown in the tab l e below: for the interrupt level and interrupt vector, see " cahpter: interrupt control (interrupt controller) ". number interrupt vector (default) interrupt level setting bit (icr [ 4:0 ] ) output c ompare 0/1 # 58 address: 0fff14 h interrupt level register (icr42) address: 0046a h output c ompare 2/3 # 59 address: 0fff10 h interrupt level register ( icr43) address: 0046b h the interrupt request flag (ocsl01 : iop0, ocsl01 : iop1, ocsl23 : iop2, ocsl23 : iop3) are not cleared aut omatically. before recovering from the interrupt process, write "0" to each bit to clear with software. mb91590 series mn705-00009-3v0-e 810
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 29 7.9. interrupt t ype? this section explains the interrupt type. the interrupt has one type only. it is generated by a compare match. mb91590 series mn705-00009-3v0-e 811
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 30 7.10. how can i enable the i nterrupt? this section explains how to enable the interrupt. set the interrupt request enable bit (ocsl01 : ioe0, ocsl01 : ioe1, ocsl23 : ioe2, oc sl 23: ioe3) for the interrupt enable. operation interrupt r equest e nable b it (ocsl01 : ioe0, ocsl01 : ioe1, ocsl23 : ioe2, oc sl 23 : ioe3) interrupt disable set "0" . interrupt enable set "1" . set the interrupt request flag bit (ocsl01 : iop0, ocsl01 : iop1, ocsl23 : iop2, ocsl23 : iop3) for the interrupt request clear. operation interrupt request flag bit (ocsl01 : iop0, ocsl01 : iop1, ocs l23 : iop2, ocsl23 : iop3) interrupt request clear write "0". mb91590 series mn705-00009-3v0-e 812
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chap ter : output compare fujitsu semiconductor confidential 31 7.11. calculation m ethod for the compare value? this section explains the calculation method for the compare value. 7.11.1 . toggle o utput p ulse 7.11.2 . pwm o utput mb91590 series mn705-00009-3v0-e 813
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 32 7.11.1. toggle o utput pulse this section explains the t oggle o utput p ulse . (example) to calculate a two - phas e pulse with ocu0, ocu 1, cycle: a, and one - fourth phase difference ? freeruntimer.cpclr = (a/2) -1 ? output compare.occp0 = (a/2)(3/4) -1 ? output compare.occp1 = (a/2)(1/4) -1 ? output compare.ocsh01.cmod = 0 are setting. a a / 2 ocu0 ocu1 mb91590 series mn705-00009-3v0-e 814
chapter 22: output compare 7 . q&a fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 33 7.11.2. pwm o utput this section explains th e pwm o utput . (example) to calculate the pwm with ocu0, ocu 1, cycle: a, and duty 1/4 ? freeruntimer.cpclr = (a/2) -1 ? output compare.occp0 = (a/2)(1/2) -1 ? output compare.occp1 = (a/2)(1/4) -1 ? output compare.ocsh01.cmod = 1 are s etting. a a / 2 ocu1 mb91590 series mn705-00009-3v0-e 815
chapter 22: output compare 8 . sample program fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 34 8. sample program th is section explains a s ample p rogram . configuration procedure example 1 .2 channels independent output compare operation (7fff, bfff) interrupt occurrence compare no clear 1. initial setting - free - run timer ch. 1 control register name.bit name setting of control register clock selection >> compare interrupt request flag >> compare interrupt request enable >> counting operation >> tcdt clear >> count clock >> tccsh1,tccsl11 .ecke .iclr .icre .stop .sclr .clk3 - 0 setting of the timer data v alue tcdt1 - port register name.bit name port ocu0 output setting see " chapter: i/o ports" port ocu 1 output setting - output compare control register name.bit name free - run timer selection setting of contr ol register pin output level invert operation> > pin output level specification>> interrupt request flag >> interrupt request enable>> operation enable setting >> ocfs 01 ocsh01,ocsl01 .cmod .otd1,otd0 .iop1,iop0 .ioe1,ioe0 .cst1,cst0 setting of compare v alue ch 0 setting of compare v alue ch 1 occp0 occp1 - in terrupt relation register name.bit name setting of an interrupt level. icr42 icr43 setting of i flag (ccr) 2. activation - output compare activation register name.bit name interrupt control ocsl01.ioe1 compare operation activation ocsl01.cst1 ocsl01.cst0 - free - run timer ch 1 activation register name.bit name counting operation activation tccs1.stop 3 . interrupt - interrupt process register name.bit name clearing of interrupt request flag ocsl01.iop0 (any process) ...... clearing of interrupt request flag ocsl01.iop1 (any process) ...... 4 . interrupt vector - setting of the vector table (note) clock - related setting and setting of __set_il(numerical value) in advance are required. see ? chapter: clock ? and ? chapter : interrupt control (interrupt controller) ? . program example 1 void output 01_sample(void) { freerun1_initial(); output01_initial(); output01_start(); freerun1_start(); } void freerun 1 _initial(void) { io_tccs1.word = 0x0041; /* setting value = 0000_0000_0100_0001 */ /* bit15 = 0 ecke internal clock source */ /* bit14 - 10 =0 reserved bit */ /* bit9 = 0 iclr compare interrupt flag clear */ /* b it8 = 0 iclr interrupt disable */ /* bit7 = 0 reserved bit */ /* bit6 = 1 stop counting disable */ /* bit5 = 0 reserved bit */ /* bit4 = 0 sclr free - run timer value (no) initialization */ /* bit3 - 0 = 0001 clk3-0 count cl ock pclk/2=32mhz/2 */ io_tcdt1 = 0x0000; /* timer data value initialization */ } void out put0 1 _initial(void) { port_setting_ocu0_out(); /* set the ocu0 pin for peripheral in put. */ port_setting_ocu1_out(); /* set the ocu1 pin for peripheral in put. */ io_ocfs 01.hword = 0x 00 03; /* select the free - run timer 1. */ io_ ocs 01.hword = 0x ec0c; /* setting value = 1110_1100_0000_11 00 */ /* bit15 - 13 = 111 undefined bit */ /* bit12 = 0 cmod ch . 0, ch . 1 level invert */ /* bit11 - 10 = 11 undefined bit */ /* b it9 - 8 = 00 otd1,otd0 compare pin output 0 */ /* bit7 - 6 = 00 iop1,iop0 output compare no match */ /* bit5 - 4 = 00 ioe1,ioe0 output compare interrupt disable */ /* bit3 - 2 = 11 undefined bit */ /* bit1 - 0 = 00 cst1,cst0 compare operation disable */ io_occp0 = bfff /* setting of compare register ch .0 */ io_occp1 = 7fff /* setting of compare register ch .1 */ io_icr[42].byte = 0x10; /* output compare ch . 0 interrupt level setting (any value) */ io_icr[43].byte = 0x10; /* output compare c h.1 interrupt level setting (any value) */ __ei(); /* interrupt enable */ } void out put0 1 _start(void) { io_o cs01.hword = 0xec3c; /* bit5 - 4 = 11 ioe1,ioe0 output compare interrupt enable */ io_ocs01.hword = 0xec3f; /* bit1 - 0 = 11 cst1,cst0 compare operation enable */ } void freerun 1 _start(void) { io_tccs1.bit.stop = 0; /* bit4 = 0 stop counting enable */ } __interrupt void input0_int(void) { io_ocsl01.byte & = 0xbf; /* bit6 = 0 iop0 clearing of interrupt flag */ ?? } __interrupt void input0_int(void) { io_ocsl01.byte & = 0x7f; /* bit7 = 0 iop1 clearing of interrupt flag */ ?? } interrupt routine specification with the vector table is required. #pragma intvect output0_int 58 #pragma intvect output 1 _int 5 9 mb91590 series mn705-00009-3v0-e 816
chapter 22: output compare 8 . sample program fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 35 configuration procedure example 2 .compar e for two pairs output of ch1 compare operation (7fff, bfff) compare is cleared with a cycle of a larger compare value. interrupt occurrence 1. initial setting - control of free - run timer ch .1 register name.bit name setting of control register clock selection>> compare interrupt request flag >> compare interrupt request enable >> counting operation >> tcdt clear>> count clock >> tccsh1,tccsl1 .ecke .iclr .icre . stop .sclr .clk3 - 0 setting of the timer data value tcdt1 - port register name.bit name port ocu1 output setting see " chapter: i/o port". - output compare control register name.bit name free - run timer selection setting of control register pin output level invert operation >> pin output level specification >> interrupt request flag >> interrupt request enable >> operation enable setting >> ocfs 01 ocsh01,ocsl01 .cmod .otd1,otd0 .iop1,iop0 .ioe1,ioe0 .cst1,cst0 setting of the compare value ch0 setting of the compare value ch1 occp0 occp1 - in terrupt relation register name.bit name setting of an interrupt level. icr42 icr43 setting of i flag (ccr) 2. activation - output compare activation register name.bit name interrupt control ocsl01.ioe1 compare operation activation ocsl01.cst1 ocsl01.cst0 - free - run timer ch1 activation register name.bit name counting operation activation tccs1.stop 3 . interrupt - interrupt process register name.bit name clearing of interrupt reque st flag ocsl01.iop0 (any process) ...... 4 . interrupt vector - setting of the vector table (note) clock - related setting and setting of __set_il(numerical value) in advance are required. see ? chapter: clock ? and ? chapter: interrupt contro l (interrupt controller) ? . program example 2 void output23_sample(void) { freerun1_initial(); output01_initial(); output01_start(); freerun1_start(); } void freerun 1 _initial(void) { io_tccs1.word = 0x0041; /* setting value =0000_0000_0100_0001 */ /* bit 15 = 0 ecke internal clock source */ /* bit14 - 10 =0 reserved bit */ /* bit9 = 0 iclr interrupt flag clear */ /* bit8 = 0 iclr interrupt disable */ /* bit7 = 0 reserved bit */ /* bit6 = 1 stop counting disable */ /* bit 5 = 0 reserved bit */ /* bit4 = 0 sclr free - run timer value (no) initialization */ /* bit3 - 0 = 0001 clk3 -0 count clock pclk/2=32mhz/2 */ io_tcdt1 = 0x0000; /* timer data value initialization */ } void out put0 1 _initial(void) { port_setting_ocu0_out(); /* set the ocu1 pin for peripheral in put. */ io_ocfs 01.hword = 0x 00 03; /* select the free - run timer 1. */ io_ ocs 01.hword = 0x ec0c; /* setting value = 1110_1100_0000_11 00 */ /* bit15 - 13 = 111 undefined bit */ /* bit12 = 0 cmod ch. 0,ch .1 level invert */ /* bit11 - 10 = 11 undefined bit */ /* bit9 - 8 = 00 otd1,otd0 compare pin output 0*/ /* bit7 - 6 = 00 iop1,iop0 output compare no match */ /* bit5 - 4 = 00 ioe1,ioe0 output compare interrupt disable */ /* b it3 - 2 = 11 undefined bit */ /* bit1 - 0 = 00 cst1,cst0 compare operation disable */ io_occp0 = bfff /* setting of compare register ch . 0 */ io_occp1 = 7fff /* setting of compare register ch .1 */ io_icr[42].byte = 0x10; /* output compare ch . 0 interrupt level setting (any value) */ io_icr[43].byte = 0x10; /* output compare ch .1 interrupt level setting (any value) */ __ei(); /* interrupt enable */ } void out put0 1 _start(void) { io_ocs01.hword = 0xec3c; /* bit5 - 4 = 11 ioe1,ioe0 output compare interrupt enable */ io_ocs01.hword = 0xec3f; /* bit 1 - 0 = 11 cst1,cst0 compare operation enable */ } void freerun 1 _start(void) { io_tccs1.bit.stop = 0; /* bit4 = 0 stop counting enable */ } __interrupt void input0_int(void) { io_ocsl01.byte & = 0xbf; /* bit6 = 0 iop0 clearing of interrupt flag */ ?? io_ocsl01.byte & = 0x7f; /* bit7 = 0 iop1 clearing of interrupt flag */ ?? } interrupt routine specification with the vector table is required. #pragma intvect output 1 _int 5 9 mb91590 series mn705-00009-3v0-e 817
chapter 22: output compare 9 . notes fujitsu semiconductor limited chapter : output compare fujitsu semiconductor confidential 36 9. notes this section explains t he notes of the output compare. ? about the compare stop interval during compare operation for one count right after the writing of a compare value to the compare register, there is no compare operation as shown below. ? for the setting of cmod= "1" and occp0 = occp1, occp2 = occp3, when compare match occurs, the port inverts only once. ? when the output level of compare pins (ocu0, ocu1, ocu2, ocu3) is specified, first stop the compare operation, and then specify it. ? because the output compare is synchronized with the free - run timer, when the free - run timer is stopped, the compare operation also is stopped. ? when the compare mode bit is set to cmod = "1" also, the interrupt operation occurs for each ocu0, ocu1, ocu2, ocu3 independent ly. ? when the free - run timer is used as the compare data of the output compare, the setting of "0000 b "(1/f pclk ) is disabled for the free - run timer clock frequency tccsl : clk[3:0]. ? read - modify - write when the interrupt request flag bits (iop0), (iop1), (iop2), (iop3) are read with read - modify - write (rmw) instruction , "1" is read. n - 2 n - 1 n n+1 n+2 n+3 x n writing to comp are register compare timing compare stop interval in this case, a match signal is not generated. n - 2 n - 1 n n+1 n+2 n+3 x n count value of free - run timer compare register value mb91590 series mn705-00009-3v0-e 818
chapt er 23: input capture 1 . overview fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 1 chapter : input capture this chapter explains the input capture. 1. overview 2. features 3. configuration 4. register 5. operation 6. setting 7. q&a 8. sample program 9. notes code : 23_mb91590_hm_e_inputcap_00 5 _2011112 7 mb91590 series mn705-00009-3v0-e 819
chapt er 23: input capture 1 . overview fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 2 1. overview this section explains the overview of the input capture. the i nput capture stores the count value of the 32 - bit free - run timer at the timing when the signal from the external sou rce is detected. the time between signals can then be calculated from the count values that have been recorded repeatedly. an interrupt can be generated when an effective edge from the external input pin is detected. figure 1-1 block diagram l in sync field detection free - run timer capture buffer edge detection circuit external pin icu interrupt mb91590 series mn705-00009-3v0-e 820
chapt er 23: input capture 2 . features fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 3 2. features this section explains features of the input capture. ? f ormat : edge detection circuit + 32 - bit buffer (capture register) ? number of units : 6 (input capture 0 to 5) + 2 ( input capture 6, 7 fo r lsyn ( lin sync field detection) only ? edge detection : rising/falling/both edges ? interrupt : edge detection interrupt ? capture value : timer count value (00000000 h to ffffffff h ) ? timer : input capture 0 to 5 : use free - run timer 0 or 1. input capture 6, 7 for lsyn only : use free - run timer 2 or 3. ? precision: p eripheral clocks (pclk ) /1, /2, /4, /8, /16, /32, /64, /128, /256) (count clock of the free - run timer) count value of free-run timer capture signal buffer value 1fffffff h 1fffffff h t mb91590 series mn705-00009-3v0-e 821
chapt er 23: input capture 3 . configuration fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 4 3. configuration this section expla ins the configuration of the input capture. figure 3-1 block diagram ( detailed; per channel ) note : input captures 6 and 7 are for lsyn only. no external pin is provided to support the m. p60 edge detection polarity capture data register 0 external pin icu/lin sync field from free - run timer from port data register edge detection circuit ipcp0 (cp31 - cp 0) ca pture port reading ice0 ic p 0 ddr6:bit 0 ics01:bit 6 ics01:bit4 only input eg01 - 00 ics01:bit1 - 0 enable output 0 1 no edge detection rising edge detection falling edge detection det ection of both edges no interrupt request interrupt request write 0: flag clear disable interrupt enable interrupt mb91590 series mn705-00009-3v0-e 822
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 5 4. registers this section explains registers of the input capture. ? table of base addresses (base_addr) and external pins table 4-1 table of base addresses (base_addr) and external pins channel base_addr external pin icu input 0 0x02c4 icu0 / icu0_1 / icu0_2 1 0x02c8 icu1 / icu1_1 / icu1_2 2 0x02d0 icu2 / icu2_1 / icu2_2 3 0x02d4 icu3 / icu3_1 / icu3_2 4 0x02dc icu4 / icu4_1 / icu4_2 5 0x02e0 icu5 / icu5_1 / icu5_2 6 0x0fd0 none (only for lsyn) 7 0x0fd4 none (only for lsyn) mb91590 series mn705-00009-3v0-e 823
chapt er 23: input capture 4 . r egisters fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 6 table 4-2 registers m ap address register s register function +0 +1 +2 +3 0x02c4 ipcp0 input capture data register 0 0x02c8 ipcp1 input capture data register 1 0x02cc icfs01 reserved lsyns 0 ics01 free - run timer selection register 01 lin synch field switching register 0 input capture control register 01 0x02d0 ipcp2 input capture data register 2 0x02d4 ipcp3 input capture data register 3 0x02d8 icfs23 reserved ics23 free - run timer selection register 23 input capture control register 23 0x02dc ipcp4 input capture data register 4 0x02e0 ipcp5 input capture data register 5 0x02e4 icfs45 reserved ics45 free - run timer selection register 45 input capture control register 45 0x0 fd0 ipcp 6 input capture data register 6 ( only for lsyn ) 0x0 fd4 ipcp 7 input capture data register 7 ( only for lsyn ) 0x0 fd8 icfs 67 reserved lsyns 1 ics 67 free - run timer selection register 67 ( only for lsyn ) lin synch field switching register 1 ( only for lsyn ) input capture control register 67 ( only for lsyn ) mb91590 series mn705-00009-3v0-e 824
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 7 4.1. input c apture data register : ipcp this section explains the bit configuration for the i nput c apture d ata r egister (ipcp) . this register can be used to hold and read the count value of the free - run timer using a change in the input signal from the external sourc e as a trigger. ? ipcp0 ( input capture 0) : address 02c4 h ( access: word) ? ipcp1 ( input capture 1) : address 02c8 h ( access: word) ? ipcp2 ( input capture 2) : address 02d0 h ( access: word) ? ipcp3 ( input capture 3) : address 02d4 h ( access: word) ? ipcp4 ( input capture 4) : address 02dc h ( access: word) ? ipcp5 ( input capture 5) : address 02e0 h ( access: word) ? ipcp6 ( input capture 6 ( only for lsyn)) : address 0fd0 h ( access: word) ? ipcp7 ( input capture 7( only for lsyn)) : address 0fd4 h ( access: word) bit 31 bit 0 cp[31:0] in itial value x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x attribute r,wx note : when accessing this register, use a word access instruction. no data can be written to this register. mb91590 series mn705-00009-3v0-e 825
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 8 4.2. free - run t imer selection r egister : icfs this section explains the bit configuration for the f ree - run t imer s election r egister (icfs) . this register selects the capture source free - run timer. ? icfs01 ( free - run timer selection 01) : address 02cc h ( access: byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D D D D D D sel1 sel0 initial value D D D D D D 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w ? icfs23 ( free - run timer selection 23) : address 02d8 h ( access: byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D D D D D D sel3 sel2 initial value D D D D D D 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w ? icfs45 ( free - run timer selection 45) : address 02e4 h ( access: byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D D D D D D sel5 sel4 ini tial value D D D D D D 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w ? icfs67 ( free - run timer selection 67 ( only for lsyn)) : address 0fd8 h ( access: byte, half - word, word) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D D D D D D sel 7 sel 6 initi al value D D D D D D 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r/w [ bit7 to bit 2 ] - : undefined this does not affect the writing operation. mb91590 series mn705-00009-3v0-e 826
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 9 [b it1 , bit 0 ] seln : free - run timer selection sel{0,1,2,3,4,5} operation 0 free - run timer 0 1 free - r un timer 1 sel{ 6 , 7 } operation 0 free - run timer 2 1 free - run timer 3 mb91590 series mn705-00009-3v0-e 827
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 10 4.3. input c apture c ontrol register : ics this section explains the bit configuration the i nput c apture c ontrol r egister (ics) . this register is used to control the input capture. ? ics01 ( i nput capture 0, 1) : address 02cf h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 initial value 0 0 0 0 0 0 0 0 attribute r(rm1),w r(rm1),w r/w r/w r/w r/w r/w r/w ? ics23 ( input capture 2, 3) : address 02db h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icp3 icp2 ice3 ice2 eg31 eg30 eg21 eg20 initial value 0 0 0 0 0 0 0 0 attribute r(rm1),w r(rm1),w r/w r/w r/w r/w r/w r/w ? ics45 ( input capture 4, 5) : addr ess 02e7 h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icp5 icp4 ice5 ice4 eg51 eg50 eg41 eg40 initial value 0 0 0 0 0 0 0 0 attribute r(rm1),w r(rm1),w r/w r/w r/w r/w r/w r/w ? ics67 ( input capture 6, 7 (only for lsyn) ) : address 0fdb h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 icp 7 icp 6 ice 7 ice 6 eg 71 eg 70 eg 61 eg 60 initial value 0 0 0 0 0 0 0 0 attribute r(rm1),w r(rm1),w r/w r/w r/w r/w r/w r/w mb91590 series mn705-00009-3v0-e 828
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 11 [b it7 , bit 6 ] icpn : input capture interrupt request flag icpn state read write 0 no interrupt request clear the flag 1 interrupt request present (edge detected) no effect on operation ? this flag will be set to "1" when the signal change (edge) selected in the capture effective edge selection bit (eg[n1:n0) is detected in the input signal from the external pin. ? to enable the cpu interrupt request, you need to enable interrupt request enable setting (icen= 1 ). * icpn: n corresponds to the input capture channel numbers. [b it5, bit 4 ] icen : inpu t capture interrupt request enabled icen operation 0 interrupt disabled 1 interrupt enabled an input capture interrupt is generated when the input capture interrupt request flag is set to "1" while the input capture interrupt request enable bit is set t o "1". * icen: n corresponds to the input capture channel numbers. [b it3 to bit 0 ] egn1, egn0 : input capture n effective edge selection egn1 egn0 edge selection 0 0 input capture stopped 0 1 rising edge 1 0 falling edge 1 1 both edges (rising and falli ng edges) ? these bits are used to select the capture effective edge(s) for the input capture signal from the external pin. ? the i nput capture will be in stop if the effective edge selection bit is " 00 b ". * egn1, egn0: n corresponds to the input capture channel numbers. mb91590 series mn705-00009-3v0-e 829
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 12 4.4. lin synch field s witching register : lsyns this section explains the bit configuration for the lin synch field s witching r egister (lsyns) . ? lsyns 0 (input capture) : address 02ce h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D D lsyn5 lsyn4 lsyn3 lsyn2 lsyn1 lsyn0 initial value D D 0 0 0 0 0 0 attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w [b it7 , bit 6 ] - : undefined the read value is always "1". this does not affect the writing operation. [b it 5 to bit 0 ] lsyn 5 to lsyn0 : inp ut capture 5 to 0 input selection lsyn n ( n=0 to 5 ) input selection 0 external pin input (icu n ) 1 lin synch field detection signal input from lin - uart ch . ( n +2) note : the input for the input capture must be switched while the capture is inactive (ics : eg[ n1:n0]=00). when the capture operation is enabled (ics : eg[n1:n0] is other than "00") and input is switched while the signal level of the external pin input and the state of the lin synch field detection signal (level) are different, edges will be detected and will operate as capture effective edges. ? lsyns1 ( input capture (only for lsyn) ): address 0fda h ( access: byte, half - word, word ) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 D D D D reserved lsyn 7 lsyn 6 initial value D D D D 0 0 0 0 attribute r1,wx r1 ,wx r1,wx r1,wx r0,w0 r0,w0 r/w r/w [b it7 to bit 4 ] - : undefined the read value is always "1". this does not affect the writing operation. [b it 3 , bit 2 ] reserved always write "0" to these bits. the read value is "0". mb91590 series mn705-00009-3v0-e 830
chapt er 23: input capture 4 . registers fujitsu semiconductor limited chapter : input captu re fujitsu semiconductor confidential 13 [b it 1 , bit 0 ] lsyn7, lsyn6 : input capture 7, 6 input selection lsynn (n= 6 , 7 ) input selection 0 disconnected 1 lin synch field detection signal input from multi - function serial interface ch . (n - 6) note : the input for the input capture must be switched while the capture is inactive (ics : eg[n1:n0]= 00). mb91590 series mn705-00009-3v0-e 831
chapt er 23: input capture 5 . operation fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 14 5. operation this section explains the operation of the input capture. when a set effective edge is detected, the 32 - bit input capture can retrieve the value of the 32 - bit free - run timer into the capture register and generate an interrupt. t his section explains the input capture operation. mb91590 series mn705-00009-3v0-e 832
chapt er 23: input capture 5 . operation fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 15 5.1. capture a nd i nterrupt t imings this section explains capture and interrupts timings of the input capture . (1) rising edge of the input signal (2) internal signal generated by edge detection (synchronized to the peripheral clock) (3) free - run timer value is recorded to the capture register (capture). (4) input capture interrupt is generated ( icp(0 to 5 )= 1, for lsyn icp6=(6, 7)=1 ). inter r upt request count of free - run timer 0 peri pheral clock (clk p ) input capture effective edge n n+1 free - run timer 0 n+1 capture register interrupt request input capture (1) (2) (3) (4) ffffffff h 00000000 h n n+1 n+1 enable free - run timer operation n n+1 (1) (2) (3 (4) mb91590 series mn705-00009-3v0-e 833
chapt er 23: input capture 5 . operation fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 16 5.2. edge d etection specifications for i nput c apture an d their o perations this section explains e dge d etection s pecifications for the i nput c apture a nd t heir o perations . ? when rising edge is selected (1) rising edge of the input signal is detected. (2) free - run counter value is reco rded to the capture register (capture). (3) input capture interrupt is generated. ? when falling edge is selected (4) falling edge of the input signal is detected. (5) free - run counter value is recorded to the capture register (capture). (6) input capture in terrupt is generated. count value of free-run timer 0 time count value a count value b count value c count value d falling edge interrupt request input capture rising edge capture data register interrupt request input capture capture data register interrupt request input capture capture data register both edges clearing flag by software (1) (2) (5) (4) (3) (8) (7) (6) (9) (10) (11) (12) (13) fffff ff f h 0000 0000 h overflow (ivf) (1) (2) (5) (4) (3) (8) (7) (6) (9) (10) (11) (12) (13) enable free-run timer operation mb91590 series mn705-00009-3v0-e 834
chapt er 23: input capture 5 . operat ion fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 17 ? both edges (7) rising edge of the input signal is detected. (8) free - run counter value is recorded to the capture register (capture). (9) input capture interrupt is generated. (10) interrupt request flag (ics01 : icp0), (ics01 : icp1), ( ics23 : icp2), (ics23 : icp3), (ics45 : icp4), (ics45 : icp5), for lsyn (ics67:icp6), for lsyn(ics67:icp7) is cleared using software. (11) falling edge of the input signal is detected. (12) free - run counter value is recorded to the capture register (cap ture). (13) input capture interrupt is generated. mb91590 series mn705-00009-3v0-e 835
chapt er 23: input capture 6 . setting fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 18 6. setting this section explains setting of the input capture. table 6-1 settings required for using input capture configuration configured register setting method free - run timer setting see " chapter: free - run timer ". D free - run timer activation setting for switching inputs between input pins icu0 to icu5 and input capture if the linkage function for l in _uart or multi - function serial interface is used: lin synch field switching register (lsyns 0 ), (lsyns1) external input: settings of the lin synch field switching register (lsyns 0 ), icu0 to icu 5 pin s (see " chapter : i/o ports" ) . see 7.2 . effective edge polarity selection for external input input capture control registers (ics01), (ics23), (ics45) input capture control register ( only for lsyn) (ics67) see 7.1 . table 6-2 settings required for performing input capture interrupt configuration configured register setting method input capture interrupt vector and input capture interrupt level settings see " chapter : interrupt control (interrupt controller) ". see 7.3 . input capture interrupt setting interrupt request clear interrupt request enable input capture control registers (ics01), (ics23), (ics45) input capture control r egister (only for lsyn) (ics67) see 7.5 . mb91590 series mn705-00009-3v0-e 836
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 19 7. q&a this section explains q&a of the input capture. 7.1 . effective edge polarity of external input : types and how to select 7.2 . how to enable external input pins (icu0, icu1 , icu2, icu3, icu4, icu5) 7.3 . about interrupt related registers 7.4 . about interrupt types 7.5 . how to enable interrupt 7.6 . how to measure the pulse width of the input signal mb91590 series mn705-00009-3v0-e 837
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 20 7.1. effective edge polarity of external input: types and how to select this section explains types of the effective edge polarity of external input and the selection method . t here are 3 types of the effective edge polarity: rising, falling and both edges. you can configure it using the effective edge polarity bits of the external input (ics01 : eg[01:00]), (ics01:eg[11:10]), (ics23 : eg[21:20]), (ics23:eg[31:30]), (ics45 : eg[41:40]), (ics45:eg[51:50]), (ics67:eg[61:60]), (ics67:eg[71:70]) . operation effective edge polarity bits o f the external input (eg[01:00]), (eg[11:10]), (eg[21:20]), (eg[31:30]), (eg[41:40]), (eg[51:50]), (eg[61:60]), (eg[71:70]) to select rising edge select "01". to select falling edge select "10". to select both edges select "11". mb91590 series mn705-00009-3v0-e 838
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : inp ut capture fujitsu semiconductor confidential 21 7.2. how to enable external input pins (icu0, icu1 , icu2, icu3, icu4, icu5) this section explains how to enable external input pins (icu0 to icu5). set the lsyns 0 register for external pin input. also, set the icu0 to icu 5 pin s for peripheral input. for information on the setting m ethod, see " chapter : i/o ports". mb91590 series mn705-00009-3v0-e 839
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 22 7.3. about interrupt related registers this section explains interrupt related registers. input capture interrupt vector and input capture interrupt level settings see " 3. list of interrupt vector " in " appendix " for interrupt nu mber . for details of the interrupt levels and interrupt vectors, see " chapter : interrupt control (interrupt controller) ". interrupt request flags (ics01 : icp0), (ics01 : icp1), (ics23 : icp2), (ics23 : icp3), (ics45 : icp4), (ics45 : icp5), (ics67 : icp6) and (ics67 : ic p7) are not cleared automatically. therefore, clear the input capture interrupt request flags (icp0, icp1, icp2, icp3, icp4, icp5, icp6, icp7) by writing "0" using software before returning from interrupt processing. mb91590 series mn705-00009-3v0-e 840
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 23 7.4. about interrupt types this section explains interrupt types. there is only 1 type of interrupt. it is generated when an edge is detected in the input signal. mb91590 series mn705-00009-3v0-e 841
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 24 7.5. how to enable interrupt this section explains how to enable interrupt. enable interrupt request, interrupt request flag you can configure the interrupt enable setting using the following interrupt request enable bits : (ics01 : ice0 ), ( ics01 : ice1 ), ( ics23 : ice2 ), ( ics23 : ice3 ), ( ics45 : ice4 ), ( ics45 : ice5 ), ( ics67 : ice6 ), ( ics67 : ice7) operation interrupt request enable bits (ice0), (ice1), (ice2), (ice3), (ice4), (ice5), (ice6), (ice7) interrupt disabled set "0" . interrupt enabled set "1" . you can clear the interrupt request using the following interrupt request flags : (ics01 : icp0 ), ( ics01 : icp1 ), ( ics23 : icp2 ), ( ics23 : icp3 ), ( ics45 : icp4 ), ( ics45 : icp5 ), ( ics67 : icp6 ), ( ics67 : icp7) operation interrupt request flag bits (icp0), (icp1), (icp2), (icp3), (icp4), (icp5), (icp6), (icp7) interrupt request clear write "0" . mb91590 series mn705-00009-3v0-e 842
chapt er 23: input capture 7 . q&a fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 25 7.6. how to measure the pulse width of the input signal this section explains how to measure the pulse width of the input signal. ? "h" width measurement enable detection of both edges. ensure that the rising edge is detected first, followed by the falling edge. pulse width = {value recorded at falling edge (input capture register value) + " 1 00000000 h " no. of overflows - value recorded at rising edge (input capture register value)} count clock width of the free - run timer example : value recorded at falling edge = 23200000 h , value recorded at rising edge = a6350000 h , no. of overflows = 1, count clock = 125ns ==> pulse width = ( 23200000 h + 100000000 h - a6350000 h ) 125ns = 261.972s ? interval measurement enable rising (or falling) edge detection. the specified edge is detected twice. cycle = {2nd recorded value (input capture register valu e) + "100000000 h " no. of overflows - {1st recorded value (input capture register value) count clock width of the free - run timer mb91590 series mn705-00009-3v0-e 843
chapt er 23: input capture 8 . sample program fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 26 8. sample program t his section explains the s ample p rogram of the input capture. setting procedure example 1 detect the ris ing edge of the pulse for input to icu0 and record the value of free - run timer. this process is repeated twice to measure the time from one trigger to another. however, reading and calculation of the capture value are to be handled as interrupt processes. 1. initial setting - free- run time r ch. 0 c ontrol register name.bit.name control register setting clock selection ? compare interrupt request flag ? compare interrupt request enable ? counting operation ? tcdt clear count clock ? tccs0 .ecke .ic lr .icre .stop .sclr .clk3 - 0 timer data value setting tcdt0 -port register name.bit name port icu0 input setting see "chapter: i/o ports". - input capture control register name.bit name control register setting interrupt request flag ? interrupt request enabled ? ch1 effective edge polarity selection ? ch0 effective edge polarity selection ? i cs0 .icp1,icp0 .ice1,ice0 .eg11,eg10 .eg01,eg00 - interrupt - related register name.bit name sets an interrupt level. icr36 i f lag setting (ccr) - variable setting 2. activation - input capture ch . 0 activation register name.bit name interrupt control ics01.ice0 - free- run timer ch. 0 activation register name.bit name count operation activation tccs0.stop 3 . interrupt - interrupt processing register name.bit name clearing of interrupt request flag ics01.icp0 ( any process ) ...... 4 . interrupt vector - vector table setting (note) clock - related settings and the setting of __s et_il (numeric value) need to be configured in advance. see ?chapter: clock ? and ?chapter: interrupts control (interrupts controller ) ? . program example 1 void input0_sample_1(void) { freerun0_initial(); input0_initial(); input0_start(); freerun0_start(); } void freerun0_initial(void) { io_tccs0.word = 0x0041; /* setting value =0000_0000_0100_0001 */ /* bit15 = 0 ecke internal clock source */ /* bit14 - 10 =0 reserved bit */ /* bit9 = 0 interrupt flag clear */ /* bit8 = 0 interrupt disable d */ /* bit7 = 0 reserved bit */ /* bit6 = 1 */ /* bit5 = 0 reserved bit */ /* bit4 = 0 */ /* bit3 - 0 = 0001 */ io_tcdt0 = 0x0000; /* initialization of timer data value */ } void input0_initial(void) { port_setting_icu0_in(); /* se t the icu0 pin for peripheral input. */ io_ics01.byte = 0x01; /* setting value =0000_0001 */ /* bit7 to 6 = 00 icp1, 0 no effective edge detected */ /* bit5 to 4 = 00 ice1, 0 interrupt disabled */ /* bit3 to 2 = 00 eg11, eg10 ch. 1 no edge detected */ /* bit1 to 0 = 01 eg01, eg00 ch. 0 rising edge detected */ io_icr[36].byte = 0x10; /* input capture ch . 0 interrupt level setting (any value) */ __ei(); /* interrupt enabled */ count = 0; } void input0_start(void) { io_ics01.bit.ice0 = 1; /* bit4 = 1 ice0 ch. 0 interrupt enabled */ } void freerun0_start(void) { io_tccs0.bit.stop = 0; /* bit6 = 0 stop count enabled */ } __interrupt void input0_int(void) { io_ics01.bit.icp0 = 0; /* bit6 = 0 clearing of icp0 effective edge detection flag */ if(count==0) data1 = io_ipcp0; /* free - run timer value is recorded. (1st time) */ else if(count==1) { data2 = io_ipcp0; /* free - run timer value is recorded. (2nd time) */ cycle = (data2 - data1)*125; /* time is measured. */ count = 0; } } count++; specification of interrupt routine required in vector table #pragma intvect input0_int 52 mb91590 series mn705-00009-3v0-e 844
chapt er 23: input capture 9 . notes fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 27 9. notes this section explains notes of the input capture. ? input capture register the input capture register value is undefined after a reset. reading of the input capture register must be perfor med in word(32 - bit mode) access . ? read - modify - write the input capture interrupt request bits (icp0), (icp1), (icp2), (icp3), (icp4), (icp5) , (icp6) and (icp7) are "1" when read using a read - modify - write (rmw) instruction. mb91590 series mn705-00009-3v0-e 845
chapt er 23: input capture 9 . notes fujitsu semiconductor limited chapter : input capture fujitsu semiconductor confidential 28 mb91590 series mn705-00009-3v0-e 846
chapter 24: real - tim e clock(rtc) 1 . overview fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 1 chapter : real - time clock(rtc) this chapter explains the real - time clock (rtc). 1. overview 2. features 3. configuration 4. register 5. operation 6. setting 7. q&a 8. sample program 9. notes code : 24_mb91590_hm_e_rtc_00 5_ 2011112 7 mb91590 series mn705-00009-3v0-e 847
chapter 24: real - tim e clock(rtc) 1 . overview fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 2 1. overview this section explains the overview of the real - time clock (rtc). the real - time clock (watch timer) consists of the timer control register, sub - second register, second/ mi nute/ hour/ d ay registers, 1/2 clock frequency divider, sub - second counter(22 - bit down counter) and second/ minute/ hour/ d ay counters. the real - time clock operates as the real - world timer and provides the real - world time r information. figure 1-1 block diagram ( overview) sub - second register sub - second counter 0.5 s econd counter second counter interrupt rtc clock wot external pin 1/2 divider minute hour day mb91590 series mn705-00009-3v0-e 848
chapter 24: real - tim e clock(rtc) 2 . features fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 3 2. features this section explains features of the real - time clock (rtc). ? function : counts the number of days and time (day/ hour/ minute/ second) (operations are kept on in the wacth mode too. ) the default values of the number of days and time can be modified. ? operation clock : rtc c lock ( see "chapter : clock" for the selection of the clock source of the rtc clock. see "chapter : rtc/wdt1 calibration " for the correction when a sub - clock (only dual clock product) is selected as a source. ) ? interrupt : interrupts can be generated based on five intervals: 0.5second, 1second, 1minute, 1hour, and 1day. in addition, interrupts at any interval (from short interval to long interval) can be generated by changing the sub - second value. mb91590 series mn705-00009-3v0-e 849
chapter 24: real - tim e clock(rtc) 3 . configuration fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 4 3. configuration this section explains the configuration of the real - time clock (rtc). figure 3-1 conf iguration diagram inte2 0 1 mb91590 series mn705-00009-3v0-e 850
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : r eal - time clock(rtc) fujitsu semiconductor confidential 5 4. registers this section explains register s of the real - time clock (rtc). table 4-1 register s map address register s register function +0 +1 +2 +3 0x0 55c reserved re served wtdr day/ hour/minute/second registers(day) 0x0 560 reserved wtcr rtc control register 0x0 564 reserved wtbr sub - second register 0x0 568 wthr wtmr wtsr reserved day/hour/minute/second registers(hour) day/hour/minute/second registers(minute) day/hour/ minute/second registers(second) mb91590 series mn705-00009-3v0-e 851
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 6 4.1. rtc control register : wtcr t he bit configuration of the rtc c ontrol r egister (wtcr) is shown below . this register controls the operations of the real - time clock module. ? wtcrh : address 0 561 h (access: byte) ? wtcrm : address 0 562 h (access: byte, half - word) ? wtcrl : address 0 563 h (access: byte, half - word) bit 23 bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 - - - - - - inte4 int4 initial value - - - - - - 0 0 attribute r1,wx r1,wx r1,wx r1,wx r1,wx r1,wx r/w r(rm1), w bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 inte3 int3 inte2 int2 inte1 int1 inte0 int0 initial value 0 0 0 0 0 0 0 0 attribute r/w r(rm1), w r/w r(rm1), w r/w r(rm1), w r/w r(rm1), w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserve d reserved reserved reserved run updt reserved st initial value 0 0 0 0 0 0 0 0 attribute r/w0 r/w0 r/w0 r/w0 r,wx r(rm0),w r/w0 r/w this register will be initialized by all reset source without the return reset from watch mode (power shut - down). [b it2 3 to bit 18 ] - : undefined the read value is always "1". the data writing does not affect the operation. [b it17 ] inte4 : 0.5 second interrupt request enable inte4 operation 0 0.5 second interrupt request disable d 1 0.5 second interrupt request enable d mb91590 series mn705-00009-3v0-e 852
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 7 [b it16 ] int4 : 0.5 second interrupt request flag int4 state read write 0 0.5 second interrupt request not generated flag clear 1 0.5 second interrupt request generated this does not affect the operations when the frequency division output of the borrow signal of the sub - second counter (22 - bit down counter) is enabled, the flag will be set to "1". [b it15 ] inte3 : 1 day interrupt request enable inte3 operation 0 1 day (24 hours) interrupt request disable d 1 1 day (24 hours) interrupt request enable d [b it14 ] int3 : 1 day interrupt request flag int3 state read write 0 1 day (24 hours) interrupt reques not generated flag clear 1 1 day (24 hours) interrupt request generated this does not affect the operations when overflow occurs in the hour counter, the flag will be set to "1". mb91590 series mn705-00009-3v0-e 853
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time c lock(rtc) fujitsu semiconductor confidential 8 [b it13 ] inte2 : 1 hour interrupt request enable inte2 operation 0 1 hour interrupt request disable d 1 1 hour interrupt request enable d [b it12 ] int2 : 1 hour interrupt request flag int2 state read write 0 1 hour interrupt request not generated flag clear 1 1 hour interrupt request generated this does not affect the operations when overflow occurs in the minute counter, the flag will be set to "1". [b it11 ] inte1 : 1 minute interrupt request enable inte1 operation 0 1 min ute interrupt request disable d 1 1 minute interrupt request enable d [b it10 ] int1 : 1 minute interrupt request flag int1 operation read write 0 1 minute interrupt request not generated flag clear 1 1 minute interrupt request generated this does not a ffect the operations when overflow occurs in the second counter, the flag will be set to "1". [b it9 ] inte0 : 1 second interrupt request enable inte0 operation 0 1 second interrupt request disable d 1 1 second interrupt request enable d [b it8 ] int0 : 1 second interrupt request flag int0 state read write 0 1 second interrupt request not generated flag clear 1 1 second interrupt request generated this does not affect the operations when overflow occurs in the 0.5 second counter, the flag will be set to "1". mb91590 series mn705-00009-3v0-e 854
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 9 [b it7 to bit 4 ] reserved these bits must always be written to "0". [b it3 ] run : operation state run state 0 real - time clock module is stopped 1 real - time clock module is running [b it2 ] updt : update updt state/operation read write 0 update comp leted this does not affect the operations 1 updating the counter values of the hour/ minute/ second counters are updated to day/ hour/minute/ second register values respectively. before writing "1" to the update bit (updt), set the value to be updated i n the day/ hour/ minute/ second registers. update for day/ hour/ minute/ second registers will be performed when reload occurs at the sub - second counter ( 22 - bit down counter) . when the counter value is updated, the updt bit will be cleared by hardware. ho wever, when update is completed at the same time as writing "1", the updt bit will not be cleared to "0". [b it1 ] reserved this bit must always be written to "0". [b it0 ] st : start st operation 0 real - time clock module is stopped. all the counters are clea red. 1 values set at day/hour/minute/second registers are loaded into day/hour/minute/second counters, and the real - time clock starts to run. note : when writing "1" to the start bit (st) from rtc stop state (st=0) (rtc operation start), do not write "1" to the update bit (updt) at the same time as the start bit. ( while st=0, writing "1" as byte immediate value to the st bit and the updt bit at the same time is prohibited. ) note : to write "1" to the update bit (updt), do it while rtc is working (st=1). mb91590 series mn705-00009-3v0-e 855
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 10 note : while the update bit (updt) is "1", writing "0" to the start bit (st) (rtc stop) is prohibited . mb91590 series mn705-00009-3v0-e 856
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rt c) fujitsu semiconductor confidential 11 4.2. sub -second register : wtbr t he bit configuration of the sub- second r egister (wtbr) is shown below . this register contains the reload value of the sub - se cond counter (22 - bit down counter) . ? wtbrh : address 0 565 h ( access: byte) ? wtbrm : address 0 566 h ( access: byte) ? wtbrl : address 0 567 h ( access: byte) wtbrh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - d21 d20 d19 d18 d17 d16 initial value - - x x x x x x attribute r1,wx r1,wx r/w r/w r/w r/w r/w r/w wtbrm bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d15 d14 d13 d12 d11 d10 d9 d8 initial value x x x x x x x x attribute r/w r/w r/w r/w r/w r/w r/w r/w wtbrl bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 d7 d6 d5 d4 d3 d2 d1 d0 initial value x x x x x x x x attribute r/w r/w r/w r/w r/w r/w r/w r/w this register will be initialized by all reset source without the reset return from watch mode (power shut - down) . the sub - second register contains the reload value used in the sub - second counter(22 - bit down counter). this value will be reloaded as soon as the sub - second counter (22 - bit down counter) becomes "0". to modify the sub - second register, confirm that no rel oad operations are being performed during the writing instruction. otherwise, the sub - second counter (22 - bit down counter) will load a wrong value that combines both new and old data bytes. generally, it is recommended to perform update while the st bit is "0". while the sub - second register is set to "0", the sub - second counter(22 - bit down counter) will not run at all. t he sub - second register settings for counting 0.5 second are as follows: table 4-2 wtbr setting e xample rtc clock frequency wtbr setting value 32 k hz 0x001f3f 4mhz 0x0f423f mb91590 series mn705-00009-3v0-e 857
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 12 4.3. day/hour/minute/second r egister : wtdr/ wthr/ wtmr/ wtsr t he bit configuration of the day/hour/minute/second r egister (wtdr/wthr/wtmr/wtsr) is shown below . these registers indicate the time information of the real - time clock (day/ hour/ minute/ second). ? wtdr ( day register ) : address 0 55e h ( access: half - word) ? wthr ( hour register ) : address 0 568 h ( access: byte, half - word) ? wtmr ( minute register ) : address 0 569 h ( access: byte, hal f- word) ? wtsr ( second register ) : address 0 56a h ( access: byte) wtdr bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 n15 n14 n13 n12 n11 n10 n9 n8 initial value 0 0 0 0 0 0 0 0 attribute r,w r,w r,w r,w r,w r,w r,w r,w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 n7 n6 n5 n4 n3 n2 n1 n0 initial value 0 0 0 0 0 0 0 0 attribute r,w r,w r,w r,w r,w r,w r,w r,w wthr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - - h4 h3 h2 h1 h0 initial value - - - 0 0 0 0 0 attribu te r1,wx r1,wx r1,wx r,w r,w r,w r,w r,w wtmr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - m5 m4 m3 m2 m1 m0 initial value - - 0 0 0 0 0 0 attribute r1,wx r1,wx r,w r,w r,w r,w r,w r,w mb91590 series mn705-00009-3v0-e 858
chapter 24: real - tim e clock(rtc) 4 . registers fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 13 wtsr bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 - - s5 s4 s3 s2 s1 s0 initial value - - 0 0 0 0 0 0 attribute r1,wx r1,wx r,w r,w r,w r,w r,w r,w this register will be initialized by power - on reset source. ? the second/ minute/ h our/ day registers contain day and time information. binary - coded notation is used for second, minute, hour, and day. ? when the register is read out, the counter value will be read out. the written data will be loaded to the counter after the updt bit is set to "1". ? as word access is not available, perform access for the respective registers. ? word access is not available for the number of days register either. in addition, be sure to perform halfword access for the number of days register as the number of days is counted using a 16 - bit counter. as byte access may cause carry during read, having the possibility of getting an inappropriate read value, byte access and word access are prohibited . ? set the hour/minute/second registers within the following ranges: h our (wthr) : 0 to 17 h (0 hour to 23 hours) minute (wtmr) : 0 to 3b h (0 minute to 59 minutes) second (wtsr) : 0 to 3b h (0 second to 59 seconds) ? confirm that there are no contradictions among the values output from the four registers: day/hour/minute/second registers. the following example may occur. [ex.] output value "1 day, 23 hours, 59 minutes, 59 seconds", "0 day, 23 hours, 59 minutes, 59 seconds". "1 day, 0 hour, 0 minute, 0 second", "1 day, 22 hours, 59 minutes, 59 seconds", 1 day, 23 hours, 0 minute, 0 second, "2 days, 0 hour, 0 minute, 0 second" figure 4-1 diagram of d ay, h our, m inute and s econd r egister t ransitions ? when the operation clock frequency is obtained by dividing the frequency of the main clock by 2 (while pll is stopped), the wrong values m ay be read out from the hour/minute/second registers. this is caused due to synchronization adjustment between reading operations and count operations. therefore, it is recommended to use second interrupts in the trigger for reading instructions. ? to restar t operations with the duration the counter has stopped as the initial value, read the day/hour/minute/second registers prior to restart and write these values to the day/hour/minute/second registers to start. ? as this series does not provide the rtc detecti on reset function, the day/hour/minute/second registers are cleared only in case of power - on reset. therefore, when the microcomputer internal low voltage detection flag is set, the day/hour/minute/second register s are recommended to be cleared. 0 mi n ute 59 mi n utes ?? ?? 59 mi n utes 0 mi n ute ?? ?? ?? 59 mi n utes 0 mi n ute ?? da y register 0 d ay 2 d ays 1 d ay if 1 day , 23 hour s , 59 mi n utes is output, the current hour depends on the reading order of the register s. 23 hours 0 hour hour register ?? 22 hours 23 hours 0 hour mi n ute register ?? 1 d ay , 0 hou r , 0 mi n ute 0 d ay , 23 hour s, 59 mi n utes 1 d ay , 23 hour s , 0 mi n ute 1 d ay , 22 hour s , 59 mi n utes 2 d ays , 0 hou r , 0 mi n ute 1 d ay , 23 hour s , 59 mi n utes mb91590 series mn705-00009-3v0-e 859
chapter 24: real - tim e clock(rtc) 5 . operation fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 14 5. operation this section explains the operation of the real - time clock (rtc). this section explains the operations of the real - time clock. figure 5-1 operation descriptions for the real - time clock (1) use the start bit (st = "0") to reset the sub - second counter (22 - bit down counter) and day/ hour/ minute/ second timers (0) , and then stop them. sub second counter clear clear clear clear clear clear 0.5 second counter second mi n ute hour day w atch mode da y (n), hour (h), mi n ute (m), and second (s) register v alues 65535 d ays 23h 59m 59s 0.5s 000000 0f423f sub second v alue in w atch mode exte r nal inter r upt input (22-bit d o wn counter) st (3) (16) (17) (17) (17) (17) (17) (17) (17) (5) (5) (4) (4) (4) (4) (7) (8) (8) (9) (10) (10) (11) (11) (12) (13) (9) (1) (1) (1) (1) (1) (1) (2) (2) (6) (14) (15) (15) wot s m h n (real-time clo c k output) day, hour, minute and second counters r un wtbr wtsr wtmr wthr wtdr h h mb91590 series mn705-00009-3v0-e 860
chapter 24: real - tim e clock(rtc) 5 . operation fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 15 (2) ? write the values of day/ hour/ minute/ second to day/ hour/ minute/ second registers: wtdr, wthr, wtmr, wtsr by software. ? write "0f h ", "42 h ", "3f h " to sub - second registers: wtbrh, wtbrm, wtbrl by software . ? initialize the interrupt request bits (int0, int1, int 2, int3, int4), and set the interrupt request enable bits (inte0, inte1, inte2, inte3, inte4) (enable interrupts to be used) . (3) set the start bit (st) to "1". (4) use the start bit (st= "1" ) to load the values in the day/ hour/ minute/ second registers: w tdr, wthr, wtmr, wtsr to the day/ hour/ minute/ second timers. (5) moreover, as the count value of the sub - second counter (22 - bit down counter) i s "000000 h ", load the values in second registers: wtbrh, wtbrm, wtbrl to the sub - second counter (22 - bit down co unter). (6) the operation flag (run) becomes "1". (7) the sub - second counter (22 - bit down counter) starts to count using a clock obtained by dividing the main clock frequency by 2 (4/2mhz). (8) when the sub - second counter(22 - bit down counter) becomes "000000 h " , load the sub - second register value "0f423 h " to the sub - second counter(22 - bit down counter). in addition, an interrupt reque st of 0.5 second counter occurs. moreover, when the real - time clock output enable is set (wot pin output enable), a n "h" level with a width twice as long as that of the main clock is output to the wot pin. (example: for main clock 4mhz, "h" output with a width of 500ns ) (9) after the 0.5 second counter is counted up, it is cleared at the next count up, the second counter of the day/ hour/ minute/ second counters is counted up, and a second interrupt request occurs. (10) the second counter of the day/ hour/ minute/ second counters is counted up, it is cleared at the next count up when the value is "59", the minute counter is counted up, and the minute interrupt request occurs at this time. (11) the minute counter of day/ hour/ minute/ second counters is counted up, it is cleared at the next count up when the value is "59", the hour counter is counted up, and the hour interrupt requ est occurs at this time. (12) the hour counter of the day/ hour/ minute/ second counters is counted up, it is cleared at the next count up when the value is "23", the day counter is counted up, and the day interrupt request occurs at this time. (13) the day counter of the day/ hour/ minute/ second counters is counted up, it is cleared at the next count up when the value is "65535". (14) move to the watch mode by software. the real - time clock will continue to run in the watch mode. (15) input a signal from a n interrupt pin (intxx) to restore from the watch mode and restart cpu. (16) set the start bit (st) to "0". (17) use the start bit st= "0" to clear(reset) the sub - second counter (22 - bit down counter) and the day/ hour/ minute/ second counters, and then stop them. mb91590 series mn705-00009-3v0-e 861
chapter 24: real - tim e clock(rtc) 6 . setting fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 16 6. setting this section explains setting of the real - time clock (rtc). table 6-1 settings required for starting the real - time clock settings setting registers setting procedure setting of the reload value (s ub- second register) sub - second register (wtbrh, wtbrm, wtbrl) see 7.1 . initialization of the real - time clock rtc control register (wtcr) see 7.2 setting of number of days, time (day/hour/minute/se cond) day/ hour/ minute/ second registers (wtdr,wthr, wtmr, wtsr) see 7.3 . startup of the real - time clock rtc control register (wtcr) see 7.4 . table 6-2 settings required for knowing the time settings setting registers setting procedure reading of number of days and time day/ hour/ minute/ second registers (wtdr,wthr, wtmr, wtsr) see 7.6 . table 6-3 settings required for stopping the real - time clock settings setting registers setting procedure stop of the real - time clock rtc control register (wtcr) see 7.7 . table 6-4 settings required for performing real - time clock interrupts settings setting registers setting procedure setting of the rtc interrupt vector and the rtc interrupt level see " chapter : interrupt control (interrupt controlle r) " . see 7.10 . rtc interrupt setting interrupt request clear interrupt request enable rtc control register (wtcr) see 7.11 . mb91590 series mn705-00009-3v0-e 862
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 17 7. q&a this section explains q&a of the real - time clock (rtc). 7.1 . how to s et the 0.5 s econd c ount i nterval? 7.2 . how to i nitialize the r eal - time c lock? 7.3 . how to s et/ u pdate n umber of d ays ( d ay) and t ime (hour/minute/second)? 7.4 . how to s tart/ s top the c ount of the r eal - time c lock? 7.5 . how to c onfirm t hat th e r eal - time c lock i s r unning? 7.6 . how to k now the n umber of d ays and t ime? 7.7 . how to s top the r eal - time c lock? 7.8 . how to c alibrate the r eal - time c lock? 7.9 . what a re i nterrupt r elated r egisters? 7.10 . what a re the i nterrupt t ypes an d h ow to s elect t hem? 7.11 . how to e nable i nterrupts? mb91590 series mn705-00009-3v0-e 863
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 18 7.1. how to set the 0.5 s econd c ount interval? this section explains how to set the 0.5 second count interval. stop the real - time clock, and set the value indicated in table 4-2 wtbr setting example to the sub - second register ( wtbr ) according to the rtc clock frequency. mb91590 series mn705-00009-3v0-e 864
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 19 7.2. how to initialize the real- time clock? this section explains how to initialize the real - time clock. perform ini tialization using the start bit (wtcr : st). write "0" instead of "1" to the start bit to reset all the bits of the hour/ minute/ second counters and the subsecond counter (22 - bit down counter) to "0" (initialization) and to stop counting. mb91590 series mn705-00009-3v0-e 865
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 20 7.3. how to s et/ update n umber of d ays ( d ay) and time (hour/minute/second)? this section explains how to set/update number of days (day) and time (hour/minute/second). write the values in day/ hour/ minute/ second registers ( wtdr, wthr, wtmr, wtsr ) , and then update them using the update bit (updt). operation update bit (updt) to update the day/ hour/ minute/ second counters set to "1" mb91590 series mn705-00009-3v0-e 866
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 21 7.4. how to s tart/ s top the c ount of the real- time clock? this section explains how to start/stop the count of the real - time clock. use the start bit (wt cr: st) to set. operation start bit (st) to stop the count of the real - time clock set to "0" to start the count of the real - time clock set to "1" mb91590 series mn705-00009-3v0-e 867
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 22 7.5. how to c onfirm t hat the real- time clock is r unning? this section explains how to confirm that the real - time clock is running. confirm using the operation flag (wtcr : run) . operation operation flag (run) the real - time clock has stopped "0" can be read the real - time clock is running "1" can be read mb91590 series mn705-00009-3v0-e 868
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 23 7.6. how to k now the n umber of d ays and t ime? this section explains how to know the number of days and time. they can be known by reading day/ hour/ minute/ second registers: wtdr, wthr, wtmr, wtsr. however, as word access is not available, access to the respective registers is required. as the time may be misread when the value is read in the boundary of the hour/minute count, perform multiple reads and use the logically correct time. example: when read from second: 1 day 2 hours 59 minutes 59 seconds => 1 day 3 hours 59 minutes 59 seconds => 1 day 3 hours 0 minute 0 secon d when read from hour: 1 day 2 hours 59 minutes 59 seconds => 1 day 2 hours 0 minute 0 second => 1 day 3 hours 0 minute 0 second mb91590 series mn705-00009-3v0-e 869
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 24 7.7. how to s top the real- time clock? this section explains how to stop the real - time clock. see " 7.4 how to s tart/ s top the c ount of the r eal - time c lock? ". mb91590 series mn705-00009-3v0-e 870
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 25 7.8. how to calibrate the real-time clock? this section explains how to calibrate the real - time clock. when the sub clock ( only dual clock product ) is s elected as the rtc clock, the ratio of main clock: sub clock can be used for calibration. see " chapter : rtc/wdt1 calibration". mb91590 series mn705-00009-3v0-e 871
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 26 7.9. what are i nterrupt related registers? this section explains interrupt related registers. setting of rtc interrupt vector and the rtc interrupt level the following table shows the relationship between interrupt levels and interrupt vectors. for details on interrupt levels and interrupt vectors, see " chapter : interrupt control (interrupt controller) ". interrupt vector (default) interr upt level setting bit(icr[4 : 0]) #37 (0fff68 h ) interrupt level register icr21 (00455 h ) the interrupt request flags (int0, int1, int2, int3, int4) are not automatically cleared. therefore, use software to clear the flags prior to restoration from interrupt processing. (write "0" to int0, int1, int2, int3, int4 bits) mb91590 series mn705-00009-3v0-e 872
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 27 7.10. what a re the i nterrupt types and h ow to select t hem? this section explains the interrupt types and selection method. there are five interrupt factors as follows: interrupt factor interrupt reque st bit interrupt request enable bit time (1second) count timing int0 inte0 time (minute) count timing int1 inte1 time (hour) count timing int2 inte2 1 day count timing int3 inte3 time(0.5 second) count timing int4 inte4 as interrupt occurs by or of t hese five factors, select using the interrupt request enable bit. mb91590 series mn705-00009-3v0-e 873
chapter 24: real - tim e clock(rtc) 7 . q&a fujitsu semiconductor limited chapter : real - time clock(rt c) fujitsu semiconductor confidential 28 7.11. how to enable i nterrupts? this section explains how to enable interrupts. use the interrupt request e nable bits (wtcr : inte0, wtcr: inte1, wtcr: inte2, wtcr : inte3, wtcr : inte4) to perform the op eration. operation setting procedure interrupt request enable bits (inte0, inte1, inte2, inte3, inte4) to disable interrupts set to "0" to enable interrupts set to "1" use the interrupt req uest bits (wtcr : int0, wtcr : int1, wtcr : int2, wtcr : int3) to cle ar interrupt requests. operation setting procedure interrupt request bits (int0, int1, int2, int3, int4) to clear interrupt requests write "0" mb91590 series mn705-00009-3v0-e 874
chapter 24: real - tim e clock(rtc) 8 . sample program fujitsu semiconductor limited chapter : real - time clock(rtc) fujitsu semiconductor confidential 29 8. sample program this section explains the sample program of the real - time clock. setting procedure example 1 start to count the real - time clock from 10 days 10 hours 10 minutes 00 second, enable the external interrupt (int0) for "h" level detection, and move to the watch mode. restore from the watch mode in case of external interrupt detection, and read the time of the real - time clock. rtc initialization rtc startup, interrupt level setting external interrupt settings move to the watch mode reading rtc after restoration from the watch mode |
